Post-Processed Acquisition & Tracking of GPS C/A L1 Signals · In this thesis, two GPS C/A L1 signal acquisition algorithms are implemented and evaluated, the Parallel Frequency Space

Post-Processed Acquisition & Tracking of GPS C/A L1Signals

A Software-Defined Receiver Approach

Gonçalo Martins Tomé

Thesis to obtain the Master of Science Degree in

Electrical and Computer Engineering

Supervisors: Professor José Eduardo Charters Ribeiro da Cunha SanguinoProfessor António José Castelo Branco Rodrigues

Examination Committee

Chairperson: Professor Nuno Cavaco Gomes HortaSupervisor: Professor José Eduardo Charters Ribeiro da Cunha Sanguino

Member of the Committee: Professor Fernando Duarte Nunes

May 2015

II

Aos meus amigos, a minha famılia e em especial a memoria do meu primo David.

”It is precisely facts that do not exist, only interpretations. . . ”

Friedrich Nietzsche

”If your plan is for 1 year, plant rice; If your plan is for 10 years, plant trees;

If your plan is for 100 years, educate children.”

Confucius

Also to Jaime & Joana!

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IV

Acknowledgments

I would like to thank Professor Jose Sanguino for giving me the opportunity to do this project and guide

me in its realization, also for helping me with its knowledge and dedication.

I would also like to thank some of my mathematics professors throughout the years, Manuel Matias,

Isabel Dias and Manuel Ricou.

Last but not least, thanks to my family and friends without whom, all of these years would have been

for naught.

My wholeheartedly thank you.

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Resumo

O desempenho de um receptor de sistemas de navegacao por satelite depende da sua arquitectura, dos

algoritmos de processamento de sinal implementados e dos sinais sob os quais processa. A actualidade

dos receptores disponıveis comercialmente neste momento nao permitem alterar a sua arquitectura, ou

os seus algoritmos de processamento de sinal. O futuro destes receptores envolve varias constelacoes

de satelites (GPS, GLONASS, GALILEO, etc...) e a possibilidade de se processarem varios tipos de

sinais diferentes ao mesmo tempo, o que contrasta com a maior parte dos receptores encontrados

hoje em dia. A flexibilidade oferecida por uma perspectiva de Radio Definido por Software permite que

diferentes arquitecturas e algoritmos sejam implementados e avaliados em cenarios reais.

O objectivo desta dissertacao e o desenvolvimento de uma plataforma em software para a implementacao

e avaliacao de receptores GPS numa perspectiva de Radios Definidos por Software chamada SDR4GPS.

Nesta dissertacao sao implementados e avaliados dois metodos de aquisicao de sinais GPS C/A

L1, a procura em paralelo no espaco da frequencia e a procura em paralelo da fase de codigo. Tambem

e implementado e avaliado o acompanhamento tanto do desvio de Doppler na frequencia da portadora

L1, assim como da fase do codigo C/A ao longo do tempo, com duas malhas Costas inter-dependentes

de maneira a desmodular os bits da mensagem de navegacao.

Palavras-chave: GPS, SDR, Aquisicao, Acompanhamento, Processamento de Sinais, SDR4GPS.

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Abstract

The performance of a Global Navigation Satellite System (GNSS) receiver depends on its architecture,

on the implemented signal processing algorithms and on which signals it processes. Commercially

available receivers do not allow the user to change its architecture, nor its signal processing algorithms.

The future of these GNSS receivers involves multiple constellation systems (GPS, GLONASS, GALILEO,

etc...) and the possibility of processing multiple different signals at the same time, which is in contrast

with the majority of receivers in use today. The flexibility provided by the Software-Defined Radio (SDR)

approach allows different receiver architectures and algorithms to be tested and evaluated in real-life

scenarios.

The objective of this thesis is the development of a software platform devoted to the implementation

and evaluation of GNSS receivers following a SDR approach.

In this thesis, two GPS C/A L1 signal acquisition algorithms are implemented and evaluated, the

Parallel Frequency Space Search and the Parallel Code Phase Search. The tracking of the Doppler

frequency offset from the L1 carrier and the C/A code phase are also implemented and evaluated using

two inter-dependant Costas Loops, so as to successfully demodulate the incoming navigation message.

Keywords: GPS, SDR, Acquisition, Tracking, Signal Processing, SDR4GPS.

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Contents

Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Resumo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VII

Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IX

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XV

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XVIII

Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XXI

Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XXIV

1 Introduction 1

1.1 Motivation and Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 Goal and Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.3 Proposed Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.4 Limitations and Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.5 State Of The Art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Theoretical Background 7

2.1 GPS C/A L1 Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1.1 Signal Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1.2 C/A Code Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1.3 Doppler Frequency Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1.4 Demodulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.2 Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.2.1 Parallel Frequency Space Search . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.2.2 Parallel Code Phase Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.2.3 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.3 Carrier and Code Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.1 Second-Order Phase-Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.3.2 Carrier Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.3.3 Code Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3 Software Implementation 27

3.1 Practical Concerns Regarding Complex Signal Processing . . . . . . . . . . . . . . . . . 28

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3.2 Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.2.1 Frequency Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.2.2 Circular Cross-Correlation and Detection . . . . . . . . . . . . . . . . . . . . . . . 30

3.2.3 Refined Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.2.4 Final Acquisition Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.3 Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.3.1 Correlators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.3.2 Discriminators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.3.3 Calculating Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.3.4 Digital Loop Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.3.5 Numerical Controlled Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.3.6 Final Tracking Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.4 Final Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4 Results 41

4.1 Scenarios Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.2 Acquisiton . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.2.1 Skipping Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.2.2 Search Grid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.2.3 Integration Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.2.4 Frequency Refinement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.3 PLL Tracking Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.3.1 Loop Noise Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.3.2 Loop Damping Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

4.3.3 Loop Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.3.4 NCO Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.3.5 Discriminators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

4.4 DLL Tracking Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

4.4.1 Correlator Spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

4.4.2 Loop Noise Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4.4.3 Loop Damping Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4.4.4 Loop Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4.4.5 NCO Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4.4.6 Discriminators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5 Conclusions 61

5.1 Achievements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.1.1 Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.1.2 Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

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Bibliography 67

A Extended Mathematical Analysis 69

A.1 Second Order PLL System H(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

A.2 Noise Bandwidth Bn of H(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

A.3 Bilinear Transform of F (s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

A.4 Inverse Z-Transform of F (z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

B C/A Code Generation 73

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List of Tables

2.1 P and C/A code characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2 Navigation Message, L1 and L2 carrier rates and lengths/period. . . . . . . . . . . . . . . 9

2.3 Minimum received RF signal strength for block IIA, IIR, IIR-M, IIF and III satellites. . . . . 10

2.4 Number of iterations and complexity of several acquisition algorithms. . . . . . . . . . . . 17

2.5 Various types of Costas phase lock loop discriminators. . . . . . . . . . . . . . . . . . . . 22

2.6 Various types of delay lock loop discriminators. . . . . . . . . . . . . . . . . . . . . . . . . 25

4.1 Recorded signal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.2 Acquisition text output of SDR4GPS without PFSS. . . . . . . . . . . . . . . . . . . . . . . 46

4.3 Acquisition text output of SDR4GPS with PFSS. . . . . . . . . . . . . . . . . . . . . . . . 47

B.1 Code Phase assignments for C/A code generation. . . . . . . . . . . . . . . . . . . . . . . 74

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List of Figures

2.1 Simplified legacy GPS satellite signal structure. . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 The effect of BPSK modulation on the L1 carrier wave with the C/A code and the naviga-

tion message data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3 Frequency domain representation of the GPS C/A signal and the thermal noise power. . . 11

2.4 Autocorrelation of PRN 1 and cross correlation of PRN 1 and 2. . . . . . . . . . . . . . . . 12

2.5 Basic demodulation scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.6 Code removal from the incoming baseband signal. . . . . . . . . . . . . . . . . . . . . . . 14

2.7 Search grid representing carrier frequency and code phase signal location. . . . . . . . . 15

2.8 Block diagram of the parallel frequency space search algorithm. . . . . . . . . . . . . . . 16

2.9 Equivalent frequency domain model of a PLL. . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.10 Costas loop block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.11 I and Q phasor diagram showing the phase error between the incoming carrier wave and

the local carrier wave replica. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.12 Comparison between various Costas phase locked loop discriminator responses. . . . . . 23

2.13 Typical code tracking loop block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.14 Example of a in lock code loop with the prompt replica having the highest normalized

correlation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.15 Comparison between various DLL discriminator responses when correlator spacing = 0.5. 25

3.1 Block diagram of the parallel code phase search algorithm. . . . . . . . . . . . . . . . . . 31

3.2 PSD of incoming signal after successful C/A code removal. . . . . . . . . . . . . . . . . . 32

3.3 Flow diagram of the acquisition algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.4 Second-order phase lock loop filter F (z). . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.5 Comparison of early, prompt and late correlation values . . . . . . . . . . . . . . . . . . . 37

3.6 Block diagram of the combined DLL and PLL tracking loops. . . . . . . . . . . . . . . . . . 38

3.7 Flow diagram of the tracking algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.8 Flow diagram of the SDR4GPS program. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.1 Transient anomaly present in the signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.2 Damaged acquisition bar output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.3 Normal signal recording. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

XVII

4.4 Normal acquisition bar output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.5 PCPS acquisition map plot for PRN 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.6 PCPS acquisition map plot for PRN 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.7 PCPS acquisition correlation PI = 1ms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45




4.11 Acquisition map where the integration period does not include a bit transition. . . . . . . . 46

4.12 Acquisition map where the integration period does include a bit transition. . . . . . . . . . 46

4.13 Unsuccessful tracking of PRN 20 with doppler shift value from PCPS acquisition. . . . . . 47

4.14 Successful tracking of PRN 20 with doppler shift value from PFSS acquisition. . . . . . . 48

4.15 FFT of incoming signal after C/A code removal. . . . . . . . . . . . . . . . . . . . . . . . . 48

4.16 Filtered PLL discriminator output for several values of PLL noise bandwidth Bn. . . . . . . 49

4.17 Bits of the navigation message for several values of PLL noise bandwidth Bn. . . . . . . . 50

4.18 Filtered PLL discriminator output for several values of PLL damping ratio ζ. . . . . . . . . 51

4.19 Zoomed in filtered PLL discriminator output for several values of PLL damping ratio ζ. . . 51

4.20 Filtered PLL discriminator output for several values of PLL loop gain Kd. . . . . . . . . . . 52

4.21 Filtered PLL discriminator output when using different discriminators. . . . . . . . . . . . . 53

4.22 Correlation results and DLL discriminator output for several values of correlator spacing. . 54

4.23 Bits of the navigation message for several values of correlator spacing. . . . . . . . . . . . 55

4.24 Filtered DLL discriminator and Bits of the navigation message for several values of DLL

noise bandwidth Bn. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4.25 Filtered DLL discriminator and Bits of navigation message for several values of DLL damp-

ing ratio ζ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4.26 Filtered DLL discriminator and Bits of navigation message for several values of DLL loop

gain Kd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.27 Filtered DLL discriminator output when using different discriminators. . . . . . . . . . . . . 59

5.1 Flow diagram of a possible future SDR4GPS program. . . . . . . . . . . . . . . . . . . . . 64

B.1 G1 shift register generator configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

B.2 G2 shift register generator configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

B.3 Example of a C/A code generation structure. . . . . . . . . . . . . . . . . . . . . . . . . . 75

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Nomenclature

Symbol Designation

F {.} discrete Fourier transform operation

Fc {.} continuous or analog Fourier transform operation

νdm maximum doppler velocity towards the observer

ωkdoppler doppler frequency shift from the L1 carrier frequency of satellite k

ωn natural frequency of the second order system

τ1 numerator time constant of the voltage controlled oscillator transfer function

τ2 denominator time constant of the voltage controlled oscillator transfer function

θi input signal of the PLL frequency domain model

θo output signal of the PLL frequency domain model

ϕ phase difference (error) between the incoming signal and the locally generated

replica

ζ damping factor of the second order system

A amplitude of the incoming signal

Bn noise bandwidth of the second order system

c speed of light

Ck(t) C/A code sequence assigned to satellite k

CA[k] discrete Fourier transform of ca[n]

ca[n] discrete representation of the locally generated C/A code signal

Dk(t) navigation message data sequence of satellite k

E early DLL correlator output energy

e[n] noise induced by the low pass filter around the C/A code, distorting the P code

XIX

F (s) filter transfer function of the PLL frequency domain model

F (z) discrete frequency domain representation of F (s)

Fc center frequency of the L1 carrier frequency

fo approximate nominal reference frequency of a GPS satellite atomic clock

Fs sampling frequency of the recorded signal

fC/Adopplermaximum doppler frequency shift of the C/A code frequecy

fdoppler(f) maximum doppler frequency shift as seen by a stationary observer on the earth’s

surface

fL1doppler maximum doppler frequency shift of the L1 carrier frequecy

fL1 carrier frequency of the L1 band

fL2 carrier frequency of the L2 band

H(s) transfer function of the PLL frequency domain model

I[n] in-phase (real) component of the incoming signal

Ik in-phase arm of the Costas loop when tracking satellite k

IE early correlator output of the in-phase component of the incoming signal

IL late correlator output of the in-phase component of the incoming signal

IP prompt correlator output of the in-phase component of the incoming signal

kb Boltzmann’s constant

Kd loop gain of the PLL frequency domain model

Ko voltage controlled oscillator gain

L late DLL correlator output energy

M iterations of the Parallel Code Phase Search algorithm

N iterations of the Frequency Space Search algorithm

N(s) voltage controlled oscillator transfer function of the PLL frequency domain model

N(z) discrete frequency domain representation of N(s)

O iterations of the Serial Search algorithm

P k(t) P code sequence assigned to satellite k

P0 zero padding of the fast Fourier transform used to increase its resolution

XX

PC C/A code signal power

PI integration period over which the satellite signals are searched for

PPL1 P code signal power on L1 band

PPL2 P code signal power on L2 band

PThermalNoise thermal noise power

Q[n] quadrature (imaginary) component of the incoming signal

Qk quadrature arm of the Costas loop when tracking satellite k

QE early correlator output of the quadrature component of the incoming signal

QL late correlator output of the quadrature component of the incoming signal

QP prompt correlator output of the quadrature component of the incoming signal

rik cross-correlation between the PRN codes of satellites i and k

rkk autocorrelation of the PRN code of satellite k

ResolutionFFT fast Fourier transform resolution used in the parallel code phase search algorithm

sk(t) signal transmitted from satellite k

Tset settling time of the second order system

X[k] discrete Fourier transform of x[n]

x[n] discrete representation of the incoming signal

y[n]NCODLLimplemented output equation of N(z) for the DLL

y[n]NCOPLLimplemented output equation of N(z) for the PLL

y[n]NCO output equation of N(z)

Z[k] discrete Fourier transform of z[n]

z[n] circular cross-correlation between x[n] and ca[n]

XXI

XXII

Glossary

ADC Analog-to-Digital Converter

BPSK Binary Phase-Shift Keying

C/A Coarse / Acquisition

CDMA Code Division Multiple Access

CW Continuous Wave

DBZP Double-Block Zero-Padding

DFT Discrete Fourier Transform

DLL Delay-Locked Loop

DSP Digital Signal Processor

DSSS Direct Sequence Spread Spectrum

FMDBZP Fast Modified Double-Block Zero-Padding

GLONASS GLObal’naya NAvigatsionnaya Sputnikowaya

Sistema

GNSS Global Navigation Satellite System

GPS Global Positioning System

I/Q In-Phase / Quadrature

IDFT Inverse Discrete Fourier Transform

IF Intermediate Frequency

IT Instituto de Telecomunicacoes

MDBZP Modified Double-Block Zero-Padding

NCO Numerically Controlled Oscillator

NRZ Non-Return-To-Zero

PCPS Parallel Code Phase Search

PFSS Parallel Frequency Space Search

PLL Phase-Locked Loop

PRN Pseudo Random Noise

PSD Power Spectrum Density

P Precision

RF Radio Frequency

SDR4GPS Software Defined Radio for GPS

XXIII

SDR Software-Defined Radio

SS Serial Search

SV Satellite Vehicle

USB Universal Serial Bus

USRP Universal Software Radio Peripheral

XXIV

Chapter 1

Introduction

This chapter starts with a brief overview of the subject regarding this work whilst also disclosing the

motivation for its development. After establishing the goals and objectives the proposed approach is

then presented. The current State-of-the-Art concerning the scope of the work is also presented.

1

1.1 Motivation and Overview

The main motivation for this thesis, results from the following considerations. The performance of a

Global Navigation Satellite System (GNSS) receiver depends on its architecture, on the implemented

signal processing algorithms and on which signals it processes. Commercially available receivers do

not allow the user to change its architecture, nor its signal processing algorithms. The future GNSS

scenario involves multiple constellation systems and the possibility of processing multiple different sig-

nals. This is in contrast with the majority of receivers in use today (one constellation/one signal – Global

Positioning System (GPS) L1). The flexibility provided by the Software-Defined Radio (SDR) approach

allows different receiver architectures and algorithms to be tested and evaluated in real-life scenarios.

This approach can be used in real-time or in post-processing, based on data previously recorded.

Currently operating GNSS systems, like the GPS, and the GLObal’naya NAvigatsionnaya Sput-

nikowaya Sistema (GLONASS), are being modernized and new signals are being added to their interface

specifications, [1], [2]. The window of opportunity to process and explore these signals is available only

to those who have control over the design of the receiver’s acquisition and tracking loops. New GNSS

systems, like the European Galileo, and the Chinese BeiDou, are being developed now, having already

signals in space, available only to those involved in the receiver development, [3], [4]. A SDR approach

would allow experiments, and comparisons with the existing systems, to be made with the few signals

already in space, particularly of the Galileo system, with some coverage over Europe. Current hi-grade

commercial GNSS receivers give access, typically, to pseudoranges, carrier phases, Doppler measure-

ments, and the satellite’s navigation messages. This is the lowest processing level interface a user may

address, for research purposes and application development. In most cases, no information is available

regarding the algorithms used to produce these observables. Often this leads to situations were a given

navigation algorithm works with a specific receiver, but not with others. Questions like “Are the outputted

pseudoranges being smoothed with the carrier phase measurements?” often have no answer, which

leaves the researcher with the task of guessing what is being done inside the receiver tracking loops.

This is particularly important for the development of high accuracy (centimetre level) differential posi-

tioning algorithms. With no control over the receiver architecture and algorithms, the characterization

of new approaches on the receiver design (signal acquisition and tracking loops) has to rely exclusively

on simulation, and in many cases those approaches are/will never be tested on real scenarios. The

research infrastructure, to be developed in this work, will allow the Instituto de Telecomunicacoes (IT)

GNSS Monitoring Station to expand its scientific research to the area of GNSS receiver design, based

on the signal processing of real data. Some of the universities involved in the design of GNSS receivers

(Aalborg University [5], University of Colorado [6], Universitat Politecnica de Catalunya [7], University of

Calgary [8], and the University of New South Wales [9]) have been developing their own approaches on

software defined receivers for GNSS. More details regarding their approaches are presented in section

1.5.

2

1.2 Goal and Objectives

The main goal of this work is the development of a software framework devoted to the implementation

of GNSS receivers, following a SDR approach. The framework to be developed should allow different

architectures and algorithms to be tested, firstly in post-processing then in real-time, with real GNSS

signals, by switching software signal processing modules, developed by the user/researcher. It is also

an objective of this work, the integration of the developed framework in the IT GNSS Monitoring Station

complementing the existing IT research infrastructure.

1.3 Proposed Approach

The envisioned approach was to develop a customized software Intermediate Frequency (IF) GNSS

receiver written in MATLAB R©, capable of acquiring and tracking multiple GNSS satellite signals, de-

code each satellite navigation message, and compute the receiver position based on the IF samples

provided by the hardware Radio Frequency (RF) front end. Regarding the used acquisition algorithm,

there were several options to choose from, including the more complex Double-Block Zero-Padding

(DBZP) [10] along with its several variants such as the Modified Double-Block Zero-Padding (MDBZP)

[11] and the Fast Modified Double-Block Zero-Padding (FMDBZP) [12], but the implemented algorithms

ended up being the simpler parallel improvements over the Serial Search (SS), the Parallel Frequency

Space Search (PFSS) and the Parallel Code Phase Search (PCPS) algorithms [13]. For the tracking

algorithm, the usual code and frequency inter-dependant Costas loops were implemented [14]. Due to

time constraints, only the acquisition and tracking of GPS C/A L1 signals was accomplished, within a

modular framework called Software Defined Radio for GPS (SDR4GPS) designed to be able to add and

exchange processing modules with ease, allowing to test and evaluate their performance.

1.4 Limitations and Challenges

This is a project with a heavy signal processing software development, involving real GNSS signals,

aiming to develop a GNSS receiver in software, almost from scratch. Thus, one of the major challenges

is related with the receiver implementation itself, due to the complexity of the algorithms and processes

involved. Performance issues of the implemented algorithms will also be a concern as the receiver will

eventually have to work in real-time, with signals from multiple satellites, apart from being able to work

with previously recorded data. Additional challenges will be faced in the signal acquisition and tracking

for the new GNSS systems, like the Galileo system, due to the fact that these systems use new/different

signals from GPS, and are still in a development phase.

3

1.5 State Of The Art

SDR is a technology that allows part of the hardware of a radio device to be replaced with a software

architecture, running on an appropriate digital processor. Such an approach allows the development of

reconfigurable terminals, thanks to the ease of access to every single functional block, implemented in

software. This characteristic happens to be very useful for system designers that are provided with a

valuable tool for testing and comparing different architectures, implemented as different software mod-

ules. The use of this technology, for the receiver development, is a very flexible approach in a multi-

standard receiver scenario, as is the case of GNSS. SDR platforms are now being developed and offer

GNSS development capability to a variety of users/researchers that have not previously had sufficient

resources to be engaged in that area. Signal processing algorithms in software-defined receivers are

typically implemented on general purpose Digital Signal Processors (DSP), with only minimal dedicated

hardware components to the RF front end. The trend that has been observed in the SDR evolution is to

place the analog-to-digital signal conversion (ADC) as close as possible to the antenna, in the chain of

front end components.

Traditionally, baseband operations in GNSS receivers have been implemented using dedicated hard-

ware due to cost, power, and speed constraints. Up until recently, GNSS SDRs were limited to post-

processing applications operating on raw samples recorded from an RF front end. However, with modern

DSPs, real-time GNSS SDRs are becoming more prevalent. Such SDRs are typically implemented in

high-level textual-based languages, such as C/C++. Processor-specific optimization techniques are of-

ten utilized for computationally expensive baseband operations. Every GNSS manufacturer uses this

approach for their receiver development, based on their own SDR platforms. Commercial GNS SDR

receivers are feely available since the early 2000s, with NORDNAV R30 being one of the first real-time

GNSS SDR [15], (spin-off of Lulea University, in Sweden). Nowadays, every research institute, that is in-

volved in GNSS receiver design, use software receivers as core tools in their research, if they do not want

to support their research exclusively on simulations. The NAMURU (Navigational Apparatus Made at

UNSW for Reconfiguraion by Users) software-defined GNSS receiver, from the University of New South

Wales, in Australia, is one of such examples [16]. Another example is the GSNRxTM software-based

GNSS receiver platform, developed by the PLAN Group of the Department of Geomatics Engineering

at the University of Calgary [17]. Some of these development initiatives have been conducted in an

open source philosophy. That’s the case of the successful collaboration between the Colorado Center

for Astrodynamics Research, of the University of Colorado, and the Danish GPS Center, of the Aalborg

University, that crystallized in the following threefold endeavour towards GNSS-SDR systems:

• a book called “A Software-Defined GPS and Galileo Receiver - A Single-Frequency Approach”

[18];

• a complete GPS software receiver (developed by the Danish GPS Center), implemented using

MATLAB R©, allowing users to change various parameters and immediately see their effects on the

overall performance of the receiver;

• a Universal Serial Bus (USB) dongle GNSS RF front-end, co-developed by the University of Col-

4

orado Aerospace Department and SiGe Semiconductor [19].

Another example of an open source approach is the GNSS-SDR project, of the Centre Tecnologic de

Telecomunicacions de Catalunya, whose aim is to provide an open source GNSS software-defined re-

ceiver [20][21]. Their proposed software receiver targets multi-constellation/multi-frequency architec-

tures, pursuing the goals of efficiency, modularity, interoperability, and flexibility demanded by user do-

mains that require non-standard features. In December 2012, they extended the receiver functionality of

their platform to acquire, track and demodulate the navigation message of the Galileo E1 open signal,

including both E1B data and the E1C pilot components [22]. Although this project is still far from full-

featured commercial software receivers, it constitutes a free platform that can be continuously improved

by peer-reviewing and contributions from researchers and developers around the world, unleashing the

potential of collaborative research in the field of GNSS software receivers.

5

6

Chapter 2

Theoretical Background

The content of this section represent the basic concepts and technical information required to under-

stand the development and implementation of the GPS software-defined receiver subject of this work.

Firstly, the GPS Coarse/Acquisition (C/A) L1 signal structure is presented, exploring its characteristics

and properties followed by the theoretical demodulation of the incoming signal, showing how the nav-

igation message can be extracted. Next, a description of some acquisition algorithms is presented,

studying their characteristics and advantages in regards to one another. Lastly, the carrier and code

tracking methods going to be implemented in this work are shown with a detailed description of their

performance.

7

2.1 GPS C/A L1 Signal

In order to design a software-defined GPS receiver, the L1 C/A signal characteristics and properties

must be studied so as to properly process them at the receiver side. This section explores the GPS

C/A L1 signal structure, how it is generated and in what conditions it reaches a receiver on the earth’s

surface.

2.1.1 Signal Structure

The GPS satellites transmit the legacy signals (called so, to distinguish them from the modernized sig-

nals) on two carrier frequencies called L1 (1575.42 MHz), the primary frequency and L2 (1227.6 MHz), the

secondary frequency. The navigation messages they transmit are Direct Sequence Spread Spectrum

(DSSS) modulated by a spread spectrum code with a unique Pseudo Random Noise (PRN) sequence,

with the C/A code belonging to a family of 1023-bit Gold codes. Those PRN sequences are uniquely

associated with each satellite vehicle (SV) and are transmitted in the same carrier frequencies through

a Code Division Multiple Access (CDMA) scheme. To be able to track a specific satellite, while receiving

all signals from all visible satellites at the same time, one must take advantage of the CDMA scheme

in place and discover the C/A code phase and doppler frequency shift from the L1 carrier of that spe-

cific satellite, at that moment and replicate the PRN sequence with the discovered code phase for that

satellite and replicate the carrier wave including the doppler shift to properly bring the desired navigation

message down to baseband.

The following block diagram represents the legacy GPS satellite signal structure

Figure 2.1: Simplified legacy GPS satellite signal structure.

8

Observing the previous figure, it is clear that the resulting L1 and L2 signals use the same atomic

clock with a nominal reference frequency of fo = 10.23 MHz, which also provides timing to every other

signal generator block that requires a clock. Although it is presented that fo = 10.23 MHz, this is not true,

as to appear that value to an observer on the ground, an actual value of fo = 10.22999999543 MHz is

used to compensate for relativistic effects. The L2 signal is not part of the objective of this work, so it will

not be studied in great detail. The L1 signal is the result of adding the bitwise xor operation between the

Precision (P) code and the navigation message, to the bitwise xor operation between the C/A code and

the navigation message. Before both signals are added, they are modulated using a Binary Phase-Shift

Keying (BPSK) scheme unto the L1 carrier with a 90o phase offset between them. Again, since the

purpose of this work is to acquire and track L1 C/A signals, the P code will not be much delved into. The

following tables resume some of the information in figure 2.1

P Code C/A Code

Chip Rate fo = 10.23 Mchip/s fo/10 = 1.023 Mchip/s

Chip Length 29.3 m 293.1 m

Code Length 2.3547× 1014 chips 1023 chips

Code Period 266.4 days 1 ms

Table 2.1: P and C/A code characteristics.

L1 Carrier L2 Carrier Navigation Message

Ratefo × 154 fo × 120 fo/2046000

1.57542 GHz 1.2276 GHz 50 bps

Length / Period 19 cm 24.4 cm 20 ms

Table 2.2: Navigation Message, L1 and L2 carrier rates and lengths/period.

hence, the signal transmitted from satellite k can be described as

sk(t) =√

2PC(Ck(t)⊕Dk(t)

)sin(2πfL1t) +

+√

2PPL1(P k(t)⊕Dk(t)

)cos(2πfL1t) +

+√

2PPL2(P k(t)⊕Dk(t)

)cos(2πfL2t) (2.1)

where PC , PPL1 and PPL2 are the powers of the signals with C/A or P codes, Ck is the C/A code

sequence assigned to satellite number k, P k is the P code sequence assigned to satellite number k,

Dk is the navigation message data sequence and fL1 and fL2 are the carrier frequencies of L1 and L2

respectively [23].

The first term of equation 2.1, the L1 C/A signal can be symbolically visualized in figure 2.2

9

Carrier

FinalSignal

C

C ⊕ D

D

Figure 2.2: The effect of BPSK modulation on the L1 carrier wave with the C/A code and the navigation

message data.

2.1.2 C/A Code Properties

As mentioned in subsection 2.1.1, the C/A spreading sequences used in GPS signals belong to a unique

family of PRN codes (called so, because of their noiselike properties), known as the Gold codes. The

specific PRN code transmitted by each satellite is a deterministic sequence resulting of the modulo-2

sum of two maximum-length sequences of length N = 2n − 1 (in the case of GPS C/A, n = 10, thus

N = 1023). The C/A code generation is explained in detail in annex B.

After its generation, the C/A code is used to spread the navigation message over a null-to-null bandwidth

of BW = 2× 1.023 MHz onto the L1 carrier. The signal is then transmitted, where it reaches the earth’s

surface with a guaranteed minimum signal power of −158.5 dBm, according to the following table [1]

SV Blocks ChannelSignal

P code C/A code

IIA/IIRL1 −161.5 dBW −158.5 dBW

L2 −164.5 dBW −164.5 dBW

IIR-M/IIFL1 −161.5 dBW −158.5 dBW

L2 −161.5 dBW −160.0 dBW

IIIL1 −161.5 dBW −158.5 dBW

L2 −161.5 dBW −158.5 dBW

Table 2.3: Minimum received RF signal strength for block IIA, IIR, IIR-M, IIF and III satellites.

10

Assuming a worst case scenario of a received power of −158.5 dBW (−128.5 dBm), this means that

the received GPS signal power is actually below the thermal noise floor, as defined by the following

equation

PThermalNoise = kb × t×BW = 8.47× 10−15 W ≈ −110.72 dBm (2.2)

where kb = 1.38 × 10−23 J/K, t = 300 K and BW = 2.046 MHz. The following figure represents the

Power Spectral Density (PSD) of the C/A signal in regard to the thermal noise

−5 −4 −3 −2 −1 0 1 2 3 4 5−200

−190

−180

−170

−160

−150

−140

−130

−120

−110

−100

Frequency [MHz]

Pow

er [d

Bm

]

GPS C/A signalNoise floor, 2MHz BW

Figure 2.3: Frequency domain representation of the GPS C/A signal and the thermal noise power.

This masking of the GPS C/A signal by the thermal noise conceals any evidence of a GPS signal

presence from the observer. This is a feature of the CDMA spread spectrum signal and requires the

appropriate signal processing to acquire and process the signal.

One of the main sought after characteristics of the C/A code, is its autocorrelation and correlation

properties. The PRN codes have two important correlation properties that make them particularly useful

in the CDMA scheme that GPS uses. For one, the PRN codes have nearly no cross correlation, meaning,

for any two non-return-to-zero (NRZ) PRN codes Ci and Ck of satellites i and k, the non normalized

cross correlation can be written as

rik(m) =

1022∑l=0

Ci(l)Ck(l +m) ≈ 0 for all m (2.3)

Another useful property is that except for zero lag, a PRN code has nearly no auto-correlation. This

property is used when searching for satellites in the acquisition stage of a GPS positioning algorithm,

because the detection of a correlation peak, indicates that a perfectly aligned code as been found,

11

allowing the algorithm to know the current phase of the PRN code being transmitted from the satellite

associated with that PRN code. The non normalized autocorrelation for any NRZ PRN code Ck of

satellite k, can be written as

rkk(m) =

1022∑l=0

Ck(l)Ck(l +m) ≈ 0 for |m| ≥ 1 (2.4)

The following figures represent the non normalized autocorrelation for PRN 1 for all 1023 possible

chip shift and also represents the cross correlation of PRN 1 and 2 for every 1023 chip shift.

0 100 200 300 400 500 600 700 800 900 1000

0

200

400

600

800

1000

chip

Cor

rela

tion

valu

e

Autocorrelation of PRN 1

0 100 200 300 400 500 600 700 800 900 1000

0

200

400

600

800

1000

chip

Cor

rela

tion

valu

e

Cross correlation of PRN 1 and 2

Figure 2.4: Autocorrelation of PRN 1 and cross correlation of PRN 1 and 2.

The non normalized autocorrelation peak magnitude is equal to 1023, while the other values are

inferior to 65, which is also true for cross correlation.

2.1.3 Doppler Frequency Shift

An important phenomenon to have in consideration when studying GPS signals, is the doppler frequency

shift caused by the satellite motion both on the L1 carrier and the C/A code. Its influence must be un-

derstood when performing both the acquisition and tracking of the GPS signal.

The maximum doppler frequency shift for a GPS satellite signal as seen by a stationary receiver on

the earth’s surface is calculated as [24]

fdoppler(f) =f × νdm

c(2.5)

12

where c is the speed of light, νdm ≈ 929 m/s is the maximum doppler velocity towards the observer

which is along the horizon direction and f is the frequency of the signal in question. For the L1 carrier

frequency and the C/A code frequency their respective maximum doppler frequency shifts are calculated

as

fL1doppler =1575.42× 106 × 929

3× 108≈ ± 4.9 kHz (2.6)

fC/Adoppler=

1.023× 106 × 929

3× 108≈ ± 3.2 Hz (2.7)

A 3.2 Hz doppler shift for the C/A code means that for a typical 1 millisecond of GPS C/A L1 signal (a

period) is recorded, the real period of the recorded signal can be shortened or enlarged up to approx-

imately 3.2 ns, whose influence can be neglected, since a chip period is approximately 978 ns. On the

other hand, a frequency shift of approximately 5 kHz on the L1 carrier cannot be neglected due to the fact

that, to successfully begin tracking the C/A L1 signal to extract the navigation message, an approximate

carrier frequency must used to remove the L1 carrier and a maximum doppler shift of approximately 5

kHz is well beyond the tracking capabilities.

2.1.4 Demodulation

To properly track the GPS signal and extract the navigation message, both the C/A code and the L1

carrier must be removed from the incoming signal, in order to achieve this, two phase-locked loops are

required, one to track the L1 carrier frequency or phase and another to track the C/A code. The following

figure represents a basic demodulation scheme.

Carrier wave replica with

detected doppler shift

PRN code replica with

detected code phase

Navigation messageIncoming signal

Figure 2.5: Basic demodulation scheme.

To recover the navigation message, firstly the incoming signal must be brought to bandbase by mix-

ing it with a local L1 carrier replica (having into account the detected doppler frequency shift obtained

in acquisition), then the C/A code is removed, by multiplying a local C/A code replica (using the code

phase shift also obtained in acquisition), this step is also called despreading, because the frequency

spectrum of the resulting signal that was spread out over the bandwidth of the chipping rate of 2× 1.023

MHz, now returns to the original bandwidth of 50 Hz, the bandwidth of the navigation message.

Returning to the GPS C/A L1 signal transmitted by satellite k represented by equation 2.1, after being

sampled, downconverted and filtered can be described as

13

sk[n] = Ck[n]Dk[n]cos[ωkdopplern1

FS] + e[n] (2.8)

where ωkdoppler is the doppler frequency shift from the L1 carrier associated with satellite k, FS is the

sampling frequency and e[n] is the noise induced by low pass filter around the C/A code, distorting the P

code. Ignoring the noise term, to remove the remaining doppler frequency shift from the L1 carrier, the

incoming signal is multiplied with a local identical doppler frequency shift replica, yielding

sk[n]cos[ωkdopplern1

FS] = Ck[n]Dk[n]cos[ωkdopplern

1

FS]cos[ωkdopplern

1

FS]

=1

2Ck[n]Dk[n] +

1

2cos[2ωkdopplern

1

FS]Ck[n]Dk[n] (2.9)

As seen in the previous equation, the resulting signal is composed of two terms, the navigation message

multiplied by the C/A code already brought to baseband and the multiplication of the navigation message

by the C/A code frequency shifted to twice the doppler frequency shift. Ignoring the one half fraction, by

applying a low pass filter, the second term is removed thus resulting in the navigation message multiplied

by the C/A code alone


FS] = Ck[n]Dk[n] (2.10)

The final step is to remove the C/A code and this is accomplished by multiplying the previous equation

with a local C/A code replica perfectly aligned in time with the incoming C/A code signal, which results

in successfully extracting the navigation message for satellite k.


FS]Ck[n]⇒ Dk[n] (2.11)

Recoverednavigationmessage

Alignedcode

Signal aftercarrierremoval

Figure 2.6: Code removal from the incoming baseband signal.

14

2.2 Acquisition

The motivation of acquisition is to detect visible satellites and estimate the coarse values of the L1

carrier doppler shift from its central frequency of 1575.42 MHz and the code phase of the C/A code being

transmitted. The code phase of the C/A code refers to the time alignment of the PRN code associated

with a specific satellite. It is necessary to know the code phase in order to generate a local PRN code

that is perfectly aligned with the incoming code, to be able to perfectly remove it. In order to search for

the carrier doppler shift, a 500 Hz step is sufficient [24]. The simplest method of searching for both these

values, is to simply try each possible combination of carrier frequency and code phase in the generated

signal, this method is called Serial Search acquisition.

Code Phase (Chips)

Code Phase (Bin)

Frequency (kHz)

Frequency (Bin)

1 1023

1 2 N-1 N

+5

-5

M

M-1

2

1

...

...

... ...Signal Location

Detected Bin

Real Continuous

Values

Discrete Space Search

Grid

Figure 2.7: Search grid representing carrier frequency and code phase signal location.

Although this approach to discovering both values has a very straightforward implementation, its

search cycle can be very exhausting and ends up being the main weakness of this simple search

method.

A possible solution to this problem is the parallelization of one of the search parameters, either the

doppler frequency shift, or the code phase. The following subsections describe the theory behind two

standard methods of parallelized acquisition to demonstrate the possibility of implementing an efficient

method in a software-defined receiver.

15

2.2.1 Parallel Frequency Space Search

The first method of acquisition using the parallelization of one of its search parameters to be discussed,

is the Parallel Frequency Space Search. As the name suggests, this algorithm of acquisition employs

a Fast Fourier Transform (FFT) over the incoming signal, thus paralleling the doppler frequency shift

search, reducing the necessary frequency search steps to solely one operation per code phase search

step. If the code phase of the generated C/A code is properly aligned in time with the C/A code phase

of the incoming signal the multiplication of both will perfectly remove the latter from the incoming signal,

allowing the FFT operation to evidentiate a peak in magnitude in the resulting signal, representing the

CW signal (continuous wave) of the doppler frequency shifted L1 carrier from the original frequency of

1.57542 GHz. If the code is not properly aligned in time with the code of the incoming signal, or the

C/A signal is not present in the current frequency search step, the FFT of the resulting multiplication of

the generated with the incoming signal will not correctly demodulate the C/A L1 signal and as such, the

incoming signal will remain below the thermal noise and consequently not visible in the FFT.

The implementation of the PFSS algorithm is be represented by the following block diagram.

PRN code

generator

Fourier

transform| |

2Output

Incoming

signal

Figure 2.8: Block diagram of the parallel frequency space search algorithm.

If a peak is indeed detected through the selected acquisition metric, the doppler frequency shift

value is obtained by evaluating the index of the resulting FFT and the C/A code phase value is obtained

evaluating the chosen code phase shift applied to the generated C/A code.

2.2.2 Parallel Code Phase Search

The second method of acquisition using the parallelization of one of its search parameters, is called

Parallel Code Phase Search and it uses the multiplication-convolution duality property to parallelize the

C/A code phase search into just one operation per doppler frequency shift search step.

In the SS algorithm, the method of obtaining the doppler frequency shift and C/A code phase of

the incoming signal is to generate a local replica of the satellite to search for (individually varying its

frequency shift from the L1 carrier and the code phase of the generated C/A code) and calculate how

much that generated signal correlates with the incoming signal, by integrating the resulting multiplica-

tion of both. The PCPS algorithm parallelizes the correlation operation and code phase shift search by

multiplying both signals frequency spectrum with each other (having complex conjugated one of them)

16

thus corresponding to a correlation operation in the time domain, having in each signal sample, the cor-

relation value between both signals when one of them is shifted from zero that number of samples.

If a satellite signal is present in the incoming signal (i.e. the frequency shift applied to the incoming

signal is a symmetric approximation, within ±500 Hz, of the doppler frequency shift), the output of the

algorithm will have a correlation peak in the sample corresponding to the code phase shift between the

incoming signal and the local replica of the C/A code. If no satellite signal is present in that frequency

search step, or the searched satellite is not present in the recorded signal at all, then the correlation

output of the PCPS algorithm will not have a distinct peak at any index.

An in-depth explanation of how the PCPS algorithm works and is implemented, including a more

detailed mathematical analysis, is presented in subsection 3.2.2.

2.2.3 Comparison

The before mentioned algorithms of acquisition can be compared by two main characteristics, their

implementation complexity and how many iterations of the base operation they run.

Algorithm Iterations Complexity

Serial Search O Low

Parallel Frequency Space Search N Medium

Parallel Code Phase Search Search M High

Table 2.4: Number of iterations and complexity of several acquisition algorithms.

where

M = ceil

(settings.doppler max− settings.doppler min

settings.doppler step

)+ 1

N = floor (settings.sampling frequency × settings.integration period)

O = M ×N

and settings.doppler max and settings.doppler min are the maximum and minimum doppler fre-

quency shift to search for, settings.doppler step is the frequency search step, settings.sampling frequency

is the sampling frequency of the signal and settings.integration period is the evaluation period chosen,

over which the C/A code is searched for, typically no less than one period, 1 ms.

Regarding the precision of the acquired doppler frequency shift and code phase values, all discussed

algorithms, upon successful satellite detection, obtain the same value of C/A code phase, but their

estimated doppler frequency shift may differ. Both the SS and PCPS algorithms measure the same

doppler frequency shift (within a maximum error of 500/2 = 250 Hz as seen in section 2.2), because

17

both algorithms use the same method of frequency translation by complex exponential multiplication,

but since the PFSS uses a FFT for satellite detection, the precision of the observed doppler frequency

shift depends on the resolution of that same FFT operation. The resolution of the FFT is calculated as

ResolutionFFT =Fs

2dlog2(Fs×PI)e+P0(2.12)

where Fs represents settings.sampling frequency, the sampling frequency of the signal, PI repre-

sents settings.integration period, the integration period over which the signal is searched for satellites,

and P0 represents settings.fft length power, the zero padding of the FFT used to increase its resolu-

tion. If no padding is used (P0 = 0) and a typical value of 1 ms of settings.integration period is used,

the previous equation yields

ResolutionFFT ≈1

PI= 1000Hz (2.13)

If a zero padding were not applied to the FFT, then, for typical run values, the frequency resolution of

the FFT for the PFSS algorithm would be considerably lower than the maximum error for SS and PCPS

algorithms, 500 Hz (maximum error).

2.3 Carrier and Code Tracking

After the coarse value of L1 carrier frequency doppler shift and the C/A code phase are obtained in

acquisition, those values are then delivered to tracking. The main purpose of this phase is to keep

track of these values and through them, extract the navigation message and provide an estimate of the

pseudorange. The following subsections will explore how this is accomplished.

2.3.1 Second-Order Phase-Locked Loop

In order to create perfectly aligned local carrier wave and C/A code replicas that can be used to extract

the navigation message and can be kept updated through time, an inter-dependent phase-locked loop

(PLL) and delay-locked loop (DLL) is used. Both the PLL and the DLL can be modeled by the following

analytic linear phase-locked loop model that can be used to predict their performance

18

∑ Kd F (s)+

N (s)

_

𝜃o

𝜃i

Figure 2.9: Equivalent frequency domain model of a PLL.

The previous system has the following transfer function

H(s) =θoθi

=KdF (s)N(s)

1 +KdF (s)N(s)(2.14)

where, Kd is the loop gain, F (s) is the filter function and N(s) is the voltage controlled oscillator,

respectively represented by the following functions

F (s) =τ2s+ 1

τ1s(2.15)

N(s) =Ko

s(2.16)

Inserting equations 2.15 and 2.16 into equation 2.14 yields

H(s) =2ζωns+ ω2

n

s2 + 2ζωns+ ω2n

(2.17)

This result is further explained in detail in appendix A.1. This transfer function refers to the closed loop

of the linearized second-order PLL, the fact that the denominator of the transfer function has a s2 in it,

is what makes this loop a second order system. From the previous equation the following relationships

are formed

ωn =

√KoKd

τ1(2.18)

ζ =ωnτ2

2(2.19)

The behavior of the PLL model can be predicted with these parameters, although another parameter is

usually used instead of the natural frequency of the system ωn, which is the noise bandwidth Bn. The

noise bandwidth Bn controls the amount of noise allowed in the filter and is calculated as

Bn =

∫ ∞0

∣∣∣H(s)∣∣∣2 df =

ωn2

(ζ +

1

4ζ

)(2.20)

19

This result is further explained in appendix A.2.

Choosing the damping ratio ζ << 1, the noise bandwidth Bn and the tolerancefraction (percentage

of the final output value of H(s)), the settling time of a second order system can be approximated by the

following equation

Tset =ln (tolerancefraction)

ζ × ωn(2.21)

2.3.2 Carrier Tracking

Following the demodulation concept introduced in figure 2.5, a more real carrier tracking is usually

accomplished with a Costas loop.

Carrier generator

Incoming

signal

PRN code

90º

Lowpass filter

Lowpass filter

Carrier loop filter

Carrier loop discriminator

Q

I

Figure 2.10: Costas loop block diagram.

Assuming the local PRN code replica is perfectly aligned in time with the incoming PRN code and

thus after the multiplication, removed from the signal, the in-phase arm of the Costas loop becomes

Dk[n]sin[ωkdopplern]sin[ωkdopplern+ ϕ] =1

2Dk[n]cos[ϕ]− 1

2Dk[n]cos[2ωkdopplern+ ϕ] (2.22)

where ϕ is the phase difference between the phase of the incoming signal and the phase of the local

carrier replica. The quadrature arm of the Costas loop becomes

Dk[n]sin[ωkdopplern]cos[ωkdopplern+ ϕ] =1

2Dk[n]sin[ϕ] +

1

2Dk[n]cos[2ωkdopplern+ ϕ] (2.23)

After filtering the terms with double the doppler shift frequency, the signals fed to the discriminator are

Ik =1

2Dk[n]cos[ϕ] (2.24)

Qk =1

2Dk[n]sin[ϕ] (2.25)

20

Using these signals, the phase error ϕ can be discovered and fed to the carrier generator through

Qk

Ik=

12D

k[n]sin[ϕ]12D

k[n]cos[ϕ]= tan[ϕ]

(2.26)

ϕ = tan−1[Qk

Ik

]

In order to maintain the phase error ϕ = 0 (i.e. keep track of the incoming signal), the PLL will tend

to keep all the energy in the in-phase arm and minimize the energy in the quadrature arm. Several

types of PLL discriminators are shown in table 2.5. The following figure(s) represent the in-phase and

quadrature components in regard to the phase difference ϕ between the incoming signal and the local

carrier replica, where the subscript P present in IP and QP indicates these components are the output

of the prompt code correlator and hence the code can be assumed to have been perfectly removed.

This operation is further explained in the next subsection.

φφ

Q

I

A

IP

-IPQP

-QP

-A

Figure 2.11: I and Q phasor diagram showing the phase error between the incoming carrier wave and

the local carrier wave replica.

As shown in the previous figure, the two-quadrant arctangent discriminator along with the other

discriminators in table 2.5 are immune to bit changes in the navigation message and thus are referred

to as Costas discriminators. This ability to be indifferent to phase shifts of 180o in the incoming signal

is specially suitable for GPS C/A L1 signals, because it allows the receiver to continuously track the

incoming signal without loosing track of it whenever a bit change occurs in the navigation message. The

following table represent several types of Costas discriminators [25].

21

Discriminator Algorithm Characteristics

QP × IP

Classic Costas analog discriminator

Near optimal at low SNR

Slope proportional do signal amplitude squared

Moderate computational burden

QP × sign(IP )

Near optimal at high SNR

Decision directed Costas

Slope proportional to signal amplitude

Least computational burden

QP /IP

Slope not signal amplitude dependent

Suboptimal but good at high and low SNR

Higher computational burden

Divide by zero error at ± 90o

tan−1(QP /IP )

Optimal (maximum likelihood estimator) at high and low SNR

Two-quadrant arctangent

Highest computational burden

Usually table lookup implementation

Table 2.5: Various types of Costas phase lock loop discriminators.

Using figure 2.11 a crude approximation of QP and IP can be made using the incoming signal

amplitude A and the phase error ϕ

IP = A cos(ϕ) (2.27)

QP = A sin(ϕ) (2.28)

Using these approximations, the approximate behaviour of each discriminator can be derived as

QP × IP =A2

2sin 2ϕ (2.29)

QP × sign(IP ) = A sinϕ (2.30)

QP /IP = tanϕ (2.31)

tan−1(QP /IP ) = ϕ (2.32)

As proved in the previous set of equations and shown in the following figure, when the phase error

ϕ ≈ 0, all discriminators tend to output a closer value of the phase error ϕ. As the phase error ϕ differs

from 0, most discriminators lose accuracy in determining its correct value. The following figure depicts

22

how the previously presented discriminators respond to the phase error ϕ, using the derived equations

2.29 through 2.32

−150 −100 −50 0 50 100 150−100

−80

−60

−40

−20

0

20

40

60

80

100

Phase Error [°]

Nor

mal

ized

PLL

Dis

crim

inat

or O

utpu

t [°]

QP x I

P

QP x sign(I

P)

QP / I

P

tan−1(QP/I

P)

Figure 2.12: Comparison between various Costas phase locked loop discriminator responses.

2.3.3 Code Tracking

Just as in the previous subsection, the usual method of tracking the code will be explained. A typical

code tracking block diagram is shown as follows

Incoming

signal

Local

oscillator

PRN code

generator

Integrate

& dump

Integrate

& dump

Integrate

& dump

Code loop

discriminator

I E

P

L

IE

IP

IL

Figure 2.13: Typical code tracking loop block diagram.

23

Assuming the local carrier wave replica is perfectly aligned in phase with the incoming carrier wave,

after the first multiplication, the incoming carrier wave can be considered removed from the incoming

signal, thus bringing the C/A code and the navigation message to baseband. After removing the incom-

ing carrier wave from the signal, three local C/A code replicas are created (early, prompt and late) with a

defined chip spacing between them, having the prompt code replica aligned in phase using the obtained

code phase shift in acquisition. These three replicas are then multiplied with the baseband incoming

signal and integrated over a fixed period. The output values of these multiplications with integrations are

called the correlator output and are an indication of how much each local code replica correlates with

the incoming code.

Chips

Correlation

Late

Prompt

Early

Incoming signal

1

1/2

0-1 -1/2 0 1/2 1

P

E L

Figure 2.14: Example of a in lock code loop with the prompt replica having the highest normalized

correlation.

The correlator output values are then fed to the DLL discriminator which calculates how much the

code phase of the locally generated replicas (early, prompt and late) should to be adjusted. All DLL

discriminators function on a early minus late basis variant.

The following table and figure respectively represent several types of DLL discriminators and depict how

these discriminators respond to the chip offset between the incoming C/A code and the locally generated

C/A code replica.

24

Discriminator Algorithm Characteristics

E2−L2

E2+L2

where

E =√I2E +Q2

E

and

L =√I2L +Q2

L

Normalized noncoherent early minus late power

by E2 + L2 to remove amplitude sensitivity

High computational load

For 1 chip E − L correlator spacing, produces true tracking

error within ± 0.5 chip of input error (in the absence of noise)

Becomes unstable (divide by zero) at ± 1.5 chip input error, but this

is well beyond code tracking threshold in the presence of noise

(IE − IL) IP + (QE −QL)QP

(dot product)

IE−ILIP

+ QE−QLQP

(normalized with I2P and Q2P )

Quasi-coherent dot product

Uses all six correlators

Moderate computational load

For 1 chip E − L correlator spacing, it produces nearly true error

output within ± 0.5 chip of input error (in the absence of noise)

Normalized version shown second using I2P and Q2P , respectively

IE − IL

IE−ILIP

(normalized with IP )

Coherent

Can be used only when carrier loop is in phase lock

Low computational load

Most accurate code measurements

Normalized version shown second using IP

Table 2.6: Various types of delay lock loop discriminators.

−1.5 −1 −0.5 0 0.5 1 1.5

−1

−0.8

−0.6

−0.4

−0.2

0

0.2

0.4

0.6

0.8

1

Offset between the incoming code and the local prompt code replica [chips]

Nor

mal

ized

DLL

dis

crim

inat

or o

utpu

t

CoherentDot ProductNormalized Power

Figure 2.15: Comparison between various DLL discriminator responses when correlator spacing = 0.5.

25

26

Chapter 3

Software Implementation

This chapter begins with a description of how to implement a Parallel Code Phase Search algorithm with

a refined frequency search on detected satellites using the Parallel Frequency Space Search algorithm.

Afterwards an explanation of how the theoretical models in section 2.3 are converted to the digital domain

is given, followed by their implementation to form the tracking algorithm. The resulting DLL and PLL

tracking chain design is presented in detail. This was all done in post processing and the recorded

signals contained interleaved in-phase and quadrature samples.

27

3.1 Practical Concerns Regarding Complex Signal Processing

The developed program operates with quadrature sampled signals only (complex signals represented

by their in-phase and quadrature samples interleaved with each other with no metadata), meaning the

data type in some recorded files might be need to be treated before entering each signal processing

chain.

When using quadrature sampled signals, the in-phase and quadrature components can be complex

combined as x[n] = I[n]+jQ[n] to form the recorded signal, where I[n] and Q[n] represent the in-phase

and quadrature samples stored in the file and x[n] represents the resulting signal. These samples were

obtained by bringing the GPS C/A L1 signal signal between Fc−Fs/2 and Fc+Fs/2 to baseband centred

around 0 Hz, where Fc is the center frequency for L1 signals (1.57542 MHz) and Fs is the sampling fre-

quency used in the recording of the signal. While bringing the signal to baseband, the two carriers used,

are generated with the same L1 carrier frequency, but with a 90o offset between them, as to record the

I[n] and Q[n]. If the input signal contains real samples, then a quadrature sampling must be executed

over its intermediate frequency to obtain the in-phase and quadrature components, as described above.

After deinterleaving and complex combining the file samples, the input stream to the program x[n],

becomes a complex-baseband signal ready for signal processing.

3.2 Acquisition

As seen in subsection 2.2.3, the acquisition could be parallelized in the code phase dimension perform-

ing only M frequency steps using the Parallel Code Phase Search algorithm, compared to the N code

phase steps performed in Parallel Frequency Space Search or the O steps performed in Serial Search

algorithms. When using typical values of acquisition parameters, these steps become

M = 41

N = 4000

O = 164000

Based on these values, a PCPS acquisition was chosen to be implemented, followed by a PFSS fre-

quency refinement, using the acquired code phase from PCPS, so only one FFT operation is performed.

The before-mentioned advantage of the parallelized code phase search and parallelized frequency

space refinement are described as follows.

3.2.1 Frequency Translation

Before discovering the correct code phase alignment of the local code replica with the incoming signal,

for despreading and consequent detection purposes, firstly the center frequency of the incoming sig-

nal must be adjusted. As seen in 2.2, the frequency search band should be accounted for, hence a

28

frequency translation is required. The Fourier transform property of frequency translation states that

X (j(ω − ω0))⇔ x(t)ejω0t (3.1)

the frequency shift property expression can be obtained by simply combining the complex expo-

nentials in the Fourier transform integral and then noticing that the resulting expression is precisely the

definition of X(.) evaluated at the frequency ω − ω0

Fc{x(t)ejω0t

}=

∫ ∞−∞

(x(t)ejω0t

)e−jωtx(t) dt

=

∫ ∞−∞

x(t)e−j(ω−ω0)t dt

= X(j(ω − ω0)) (3.2)

where Fc {.} represents the continuous or analog Fourier transform

Fc {x(t)} =

∫ ∞−∞

x(t)e−jωt dt = X(jω) (3.3)

On the digital perspective, the above Fourier transform expressions are represented in another man-

ner, beginning with the Discrete Fourier Transform (DFT)

F {x[n]} =

N−1∑n=0

x[n]e−j2πkn/N = X[k] (3.4)

where N is the length of the signal being transformed. The frequency translation property of the DFT

is then explained as follows

F{x[n]ej2πmn/N

}=

N−1∑n=0

(x[n]ej2πmn/N

)e−j2πkn/N

=

N−1∑n=0

x[n]e−j2π(k−m)n/N

= X[k −m] (3.5)

proving that a digital signal can be shifted in the frequency domain by multiplying it with a complex dis-

crete exponential wave. This frequency translation manifests itself as a circular shift on X[k] represented

by X[k −m] where m is the amount of circularly shifted samples and each sample represent a digital

frequency step of value equal to the sampling frequency divided by the total number of samples N .

X[k −m]⇔ x[n]ej2πmn/N (3.6)

The implemented frequency translation algorithm is accomplished, firstly by multiplying the incoming

signal with a complex exponential wave of frequency settings.doppler min, so the signal gets shifted to

29

settings.doppler min, the beginning of the search band. Afterwards, a cycle of positive frequency trans-

lation of settings.doppler step, circular cross correlation and peak detection happens for every frequency

step up until settings.doppler max (see figure 3.3). The complex exponential wave is chosen instead of

the usual real sinus wave, because it removes the need for filtering the resulting signal to remove the

double frequency signal artifact, as it is usually not possible to do so with real signals.

3.2.2 Circular Cross-Correlation and Detection

The goal of the acquisition is to perform a correlation with the incoming signal and a PRN code. Instead

of multiplying the input signal with a PRN code with several different code phases as done in the serial

search acquisition method, it is more convenient to make a circular cross correlation between the input

and the PRN code. In the following, a method of performing circular correlation through Fourier trans-

forms will be described [26]

Using equation 3.4, the DFT of the finite length sequences x[n] and ca[n] both with length N are

computed as

X[k] =

N−1∑n=0

x[n]e−j2πkn/N (3.7a)

CA[k] =

N−1∑n=0

ca[n]e−j2πkn/N (3.7b)

The circular cross-correlation between two finite length sequences x[n] and ca[n] both with length N and

periodic repetition is computed as

z[n] =1

N

N−1∑m=0

x[m] ca[n+m] (3.8)

In the following, the scaling factor 1N will be omitted. The discrete N-point Fourier transform of z[n] can

be expressed as

Z[k] =

N−1∑n=0

N−1∑m=0

x[m] ca[n+m] e−j2πkn/N

=

N−1∑m=0

N−1∑n=0

x[m] ca[n+m] ej2πkm/N e−j2πk(n+m)/N

=

N−1∑m=0

x[m] ej2πkm/NN−1∑n=0

ca[n+m] e−j2πk(n+m)/N

= X∗[k] CA[k] (3.9)

30

Where X∗[k] is the complex conjugate of X[k]. The above equation can also be written as

Z[k] =

N−1∑n=0

N−1∑m=0

x[n+m] ca[m] e−j2πkn/N = X[k] CA∗[k] (3.10)

Finnaly, the magnitude of z[n] can be written as

∣∣∣z[n]∣∣∣2 =

∣∣∣F−1 {X∗[k] CA[k]}∣∣∣2 =

∣∣∣F−1 {X[k] CA∗[k]}∣∣∣2 (3.11)

Where F−1 represents the Inverse Discrete Fourier Transform (IDFT), described as follows

z[n] =1

N

N−1∑k=0

Z[k]ej2πkn/N (3.12)

Equation 3.11 can be used to find the correlation of the input signal and the locally generated signal,

it provides a periodic (or circular) correlation and this is the desired procedure [24].

Fourier

Transform

Incoming

signal

Complex

conjugate

Fourier

Transform

PRN code

generator

Inverse Fourier

transform| |

2Output

Figure 3.1: Block diagram of the parallel code phase search algorithm.

The result of the multiplication between the Fourier transform of the input signal and the complex

conjugate of the Fourier transform of the C/A code is transformed into the time domain by an inverse

Fourier transform. The absolute value of the output of the inverse Fourier transform represents the

correlation between the input and the PRN code. If a peak is present in the correlation, the index of this

peak marks the PRN code phase of the incoming signal.

3.2.3 Refined Acquisition

As mentioned before in section 2.3, the carrier and code tracking loops start tracking at the coarse val-

ues obtained from acquisition. PCPS acquisition with a typical value of 500 Hz as the search frequency

step, is sufficient for satellite detection but may not be precise enough for the tracking loops to begin

tracking. Hence, a refined search of the doppler frequency shifts is required to properly begin tracking.

For this purpose and having into account the code phase shift values obtained from PCPS acquisition

31

required to perfectly remove the C/A code sequence from the signal, a PFSS is then performed for the

detected satellites in PCPS.

After successfully removing the C/A code, the resulting FFT will have a peak present at the doppler

frequency shift.

−2 −1.5 −1 −0.5 0 0.5 1 1.5 2

x 106

0

1

2

3

4

5

6

7

8

9x 10

9

Frequency [Hz]

Mag

nitu

de

Figure 3.2: PSD of incoming signal after successful C/A code removal.

3.2.4 Final Acquisition Structure

The final acquisition structure implemented in this program consists of a PCPS acquisition on the se-

lected satellites, followed by a PFSS refinement on those satellites who are considered detected by the

acquisition metric. Between PCPS and PFSS phases, a normalization of the best correlation results

of all satellites is done, by dividing those results by the worst correlation in the satellite set, excluding

satellites not searched for.

The following figure represents this implementation of the acquisition algorithm.

32

Parallel Frequency Space Search

acquisition.m

Initializations

(pre-allocating

vectors, matrixes

and load file)

frequency shift

original signal to

doppler_min -

doppler_step

create complex

conjugate of the

FFT of the

appropriate C/A

code

frequency shift

copy of originaly

shifted signal to

doppler_step

circular cross

correlation for

this frequency

step

save

correlation

result for this

frequency step

all frequency

steps tested?

save frequency step

and corresponding

code phase based on

best correlation result

for this C/A code

plot acquisition

map?

plot aquisition map

(code phase and

frequency step)

searched for all

C/A codes?

refine

acquisition?

return acquisition

results

no

yes

are there detected

satellites according to

chosen metric yet to

be refined?

no

generate appropriate

C/A code and remove

it from the incoming

signal by multiplication

estimate

doppler shift

via DFT

update results

Parallel Code Phase Search

yes

yesyesno

no

yes

no

Figure 3.3: Flow diagram of the acquisition algorithm.

3.3 Tracking

In the previous sections, the discussion is based on continuous systems. In order to build a phase-

locked loop in software for digitized data, the continuous system from 2.3.1 must be changed into a

discrete system. The transformation from the continuous s-domain into the discrete z-domain is through

the bilinear transform, described as [26]

s =2

Ts

1− z−1

1 + z−1(3.13)

33

where Ts is the numerical integration step size of the trapezoidal rule used in the bilinear transform

derivation, or in other words, the sampling period (the inverse of the sampling frequency).

The following subsections explore how this implementation was done.

3.3.1 Correlators

As seen in figure 2.5, to extract the navigation data signal, the carrier and the code must be removed

from the incoming signal, this is accomplished, respectively, by multiplying the incoming signal by the

synthesized complex carrier and the early, prompt and late code replicas. After this, a summation of the

six signals is done, over the time interval of a C/A period (1 millisecond) and each of these values is

labeled IE , IP , IL, QE , QP , QL, accordingly. These values are proportional to the correlation between

the incoming carrier wave and the C/A code, hence the name correlators.

The summation period is fixed at 1 millisecond, because this allows for a proper tracking of the C/A code

as well as the doppler shift in the carrier wave, without being too much of a computational burden. This

value could be variable in future versions of the program.

3.3.2 Discriminators

The coding implementation of the discriminators is a straightforward one. Using the correlators output

(IE , IL, IP , QE , QL, QP ) and the chosen discriminators from tables 2.5 and 2.6, selected through the

program input commands settings.dll discriminator and settings.pll discriminator, the PLL discrimi-

nator acts as a phase detector and outputs the phase error ϕ (or an approximation of it, depending on

the chosen discriminator) between the incoming signal and the synthesized one which is then fed back

to the carrier NCO, whereas the DLL discriminator feeds back to the PRN code generators an indication

of how much the code phase (and consequently the code frequency) has to be adjusted. These outputs

are then delivered to the loop filters to be processed and afterwards used to control the carrier NCO and

PRN generation, for the next iteration of the loop cycle.

After implementing the PLL discriminators in table 2.5, it was verified that the first (QP × IP ) and second

(QP × sign(IP )) discriminators did not work. Their signal amplitude sensitivity prevented the proper

tracking of the system. To resolve this issue, a normalization of both the outputs was implemented using

the information from equations 2.30 and 2.31, thus allowing for a proper tracking of the incoming signal.

Regarding the DLL discriminators, only the normalized noncoherent early minus late power discrimina-

tor functioned properly upon first implementation. Both the other two DLL discriminators (quasi-coherent

dot product and coherent), much in the same way as the PLL discriminators, only successfully tracked

the incoming signal after their normalization by the in-phase prompt correlator output. After the nor-

malization, these discriminators essentially became identical, so only two discriminators were ultimately

implemented, the normalized noncoherent early minus late power (E2−L2

E2+L2 ) and the normalized coher-

ent/dot product ( IE−ILIP).

34

3.3.3 Calculating Filter Coefficients

After choosing the desired the noise bandwidth Bn, damping factor ζ, loop gain Kd and nco gain Ko

responsible for the behavior of the transfer function H(s) that describes the phase lock loop system, the

filter coefficients τ1 and τ2 must be calculated accordingly. As described in subsection 2.3.1, the DLL

can be modeled as a linear PLL and thus the performance of the loop can be predicted based on this

model. In other words the loop filter design is the same, just the parameter values are different.

Using equations 2.20, 2.18 and 2.19, τ1 and τ2 are derived as follows

τ1 =KoKd

ω2n

(3.14)

τ2 =2ζ

ωn(3.15)

where

ωn =8ζBn

4ζ2 + 1(3.16)

Using the values of τ1 and τ2 calculated this way, the correct behavior of the loop system is assured.

3.3.4 Digital Loop Filters

Having calculated the filter coefficients, the digital structure of the loop filter can be obtained, firstly, by

applying the bilinear transform to equation 2.15 resulting in

F (z) = C1 +C2

1− z−1(3.17)

where

C1 =2τ2 − Ts

2τ1and C2 =

Tsτ1

This result is explained in greater detail in appendix A.3.

∑C2 ∑

z-1

C1

OutputIncoming

signal

Figure 3.4: Second-order phase lock loop filter F (z).

35

lastly, by applying the inverse Z-transform to the previous equation and reordering the resulting equa-

tion to give a proper usable program command line, yields

y[n]F (z) = y[n− 1] + C1 (x[n]− x[n− 1]) + C2 x[n] (3.18)

3.3.5 Numerical Controlled Oscillators

Lastly in implementing the tracking structure, the NCOs are updated with the filters output command,

that control the the PLL carrier frequency and the DLL code frequency of the synthesized signals for the

next iteration of the tracking cycle.

In implementing a software defined VCO, the resulting system is usually called a numerical controlled

oscillator (NCO) in simple cases using lookup tables. As seen in subsection 3.3.4, usually a bilinear

transform is applied to achieve this result, but in the case of an integrator such as 2.16, typically, a direct

digital frequency synthesizer with the following transform function is used

N(z) =Koz

−1

1− z−1(3.19)

After applying the inverse z-transform and reordering, yields

y[n]NCO = y[n− 1] +Kox[n− 1] (3.20)

which is a correct implementation of an integrator with gain Ko, but in the particular design of this PLL

(also the DLL, but with one difference) loop, the inverse z-transform of the chosen filter (equation 3.18)

also depends on its previous outputs, meaning the cumulative characteristic of the integrator is already

present in the filter function. With this in mind, the final function of the integrator is modified, by removing

its output memory and fixing its center frequency on the acquired frequency discovered in the acquisition

phase of the program.

Thus, the final PLL integrator function becomes

y[n]NCOPLL= acquired freq +Kox[n− 1] (3.21)

While the PLL discriminators outputs a signal that, when positive in sign, represents that an increase

in the synthesized carrier frequency is required and when negative, represents that a decrease in the

synthesized carrier frequency is required, the DLL discriminators output the reverse, i.e. when the

discriminator output is positive, the synthesized code frequency should be reduced and when the dis-

criminator output is negative, the synthesized code frequency should be increased.

If the late code replica has a higher correlation with the incoming signal than the early code replica,

then, in all of the possible discriminators, the output sign will be negative, indicating the code frequency

should be increased.

36

Chips

Correlation

Late

Prompt

Early

Incoming signal

1

1/2

0-1 -1/2 0 1/2 1

P

E

L

Figure 3.5: Early, late and prompt correlation values. The late replica has the highest correlation so the

code phase must be increased

This is implemented as such

y[n]NCODLL= code freq −Kox[n− 1] (3.22)

where code freq = 1.023 MHz

37

3.3.6 Final Tracking Structure

Combining the previously designed DLL and PLL loop into a single common structure, the following

block diagram is obtained

Re

Im

Complex carriergenerator

Incomingsignal

PRN codegenerator

Integrate& dump

Integrate& dump

Integrate& dump

Integrate& dump

Integrate& dump

Integrate& dump

Code loopfilter

Code loopdiscriminator

Carrier loopfilter

Carrier loop discriminator

Q

I E

P

L

L

P

E

IE

IP

IL

QL

QP

QE

NavigationMessage

Figure 3.6: Block diagram of the combined DLL and PLL tracking loops.

When the PLL and the DLL both have a lock on the incoming signal, the navigation message signal

is extracted through the IP correlator output.

The described tracking algorithm in this section is represented by the following flowchart

tracking.minitializations

satellite specific

initializations

(acquired C/A code

phase and doppler

shift)

load 1 ms of

signal to process

generate complex

carrier and bring the

signal to baseband

generate early,

prompt and late

code period replicas

obtain IE, IP, IL, QE,

QP and QL through

correlators

DLL loop calculations

(discriminator, filter

and code frequency

for next iteration)

PLL loop calculations

(discriminator, filter

and code frequency

for next iteration)

save ms

iteration results

all ms

processed?

All channels

processed?

yes

no

return tracking

results

yes

no

Figure 3.7: Flow diagram of the tracking algorithm.

38

3.4 Final Model

The following depicted flow diagram demonstrates the final code implementation of the acquisition and

tracking algorithms presented thus far within the SDR4GPS framework. The program begins by search-

ing for the selected satellites, gathering the doppler shift and code phase of each C/A signal, then, upon

the chosen metric, channels are created to track the acquired satellites.

Signal Source(Recorded Samples)

Settings

Aquisition Results(Doppler Frequency Shift, C/A

Code Phase, etc...)

Tracking Results(Correlators, PLL and DLL Frequency,

Navigation Message, etc...)

Acquisition• Parallel Code Phase Search• Parallel Frequency Space Search

Tracking • PLL Loop • DLL Loop

SDR4GPSFramework

Signal Processing Chain

Figure 3.8: Flow diagram of the SDR4GPS program.

39

40

Chapter 4

Results

This chapter presents the performance results of the acquisition and tracking algorithms obtained by

evaluating several parameters of the ultimately implemented system. Firstly, a brief introduction of, under

which settings the results were obtained and which recorded signals were used is presented. Lastly, the

acquisition and tracking modules performance evaluation is shown, comparing the experimental results

with the expected theoretical models providing a succinct analysis of their meaning.

41

4.1 Scenarios Description

Due to the fact of not being able to record new GPS signals, throughout the implementation and testing

phases of this work, three signals previously recorded by different universities were used. Two signals

from the Danish GPS Center at Aalborg University (signals 1 and 2) and another from the Centre Tec-

nologic de Telecomunicacions de Catalunya (signal 3). Signal 1, 2 and 3 are named ’Multipath.bin’,

’GPS fs16 3676E6-if4 1304E6 8bit.bin’, ’2013 04 04 GNSS SIGNAL at CTTC SPAIN.dat’ respectively

and have the following characteristics

Recording Date Sampling Frequency Intermediate Frequency Data Type

Signal 1 11/09/2007 16.3676 MHz 4.1304 MHz int8 (real samples)

Signal 2 ? 16.3676 MHz 4.1304 MHz int8 (real samples)

Signal 3 04/04/2013 4 MHz 0 MHz int16 (I & Q samples)

Table 4.1: Recorded signal characteristics.

Signals 1 and 2 were downconverted to baseband using a complex exponential carrier with a fre-

quency corresponding to each signals IF frequency and saved as interleaved In Phase and Quadrature

(I/Q) samples, while signal 3 had already the desired characteristics. In all tests, except were noted, one

of these 3 signals was used. Further specification on the settings used is given in sections 4.3 and 4.4.

4.2 Acquisiton

This section contains the assessment of the acquisition module of the SDR4GPS program, starting

with the bytes to skip parameter, followed by an analysis of the search grid, then the evaluation of the

integration period parameter and finally the frequency refinement option.

4.2.1 Skipping Bytes

An option of the SDR4GPS program is the bytes to skip parameter. It allows the user to begin reading

the file after the specified number of bytes, so that it helps to avoid transient anomalies or other types of

signal glitches. This may improve the acquisition.

The next figures present a signal recording with a transient glitch and the corresponding acquisition bar

output, followed by a normal signal recording and its acquisition bar output.

42

0 20 40 60 80 100 120 140 160 180 200−1

−0.5

0

0.5

1x 104

valu

e

In−phase samples

0 20 40 60 80 100 120 140 160 180 200−4000

−2000

0

2000

4000

6000

Quadrature samples

valu

e

Figure 4.1: Transient anomaly present in the signal.

0 5 10 15 20 25 300

1

2

3

4

5

Acquisition results

PRN number (no bar − satellite is not in the acquisition list)

Acq

uisi

tion

Met

ric

Figure 4.2: Damaged acquisition bar output.

after skipping 1 millisecond of signal

0 20 40 60 80 100 120 140 160 180 200−400

−200

0

200

400

valu

e

In−phase samples

0 20 40 60 80 100 120 140 160 180 200−400

−200

0

200

400

Quadrature samples

valu

e

Figure 4.3: Normal signal recording.

0 5 10 15 20 25 300

1

2

3

4

5

6

7

Acquisition results

PRN number (no bar − satellite is not in the acquisition list)

Acq

uisi

tion

Met

ric

Figure 4.4: Normal acquisition bar output.

In this case, all satellites showed an improved correlation. This is specially true with SV20, SV23 and

SV30.

4.2.2 Search Grid

Using PCPS acquisition, a search grid of doppler shifts x code phases is obtained, with the correlation

with the local C/A code being represented by the height of each point in the grid. The resolution of fre-

43

quency axis can be adjusted by altering the doppler step parameter, whereas the code phase resolution

depends only on the sampling frequency of the recorded file. The larger the sampling frequency, the

better the resolution of the code phase, as explained by the equation

∆chip =sampling frequency

code frequency=sampling frequency

1.023× 106samples/chip (4.1)

The following figures represent a normal PCPS acquisition map plot for a recorded signal, where

PRN 1 was visible at the time of recording and PRN 2 was not.

Figure 4.5: PRN 1 is present. Figure 4.6: PRN 2 is not present.

PCPS acquisition successfully detected PRN 1, as shown by the correlation peak at doppler shift

7000 Hz and code phase 3987 samples. On the other hand, PRN 2 was not found, as indicated by the

lack of a noticeable correlation peak.

4.2.3 Integration Period

In order to demonstrate the effect of the integration period parameter on the PCPS aquisition results,

using the bytes to skip parameter, the algorithm is run for several typical values of integration period

and a plot is produced, showing the acquisition correlation result of the PCPS algorithm regarding the

starting point in time of the file recording.

44

−10 −8 −6 −4 −2 0 2

x 10−3

0

2

4

6

8

10

12

14

16

18x 10

9A

cqui

sitio

n C

orre

latio

n R

esul

t

Time with origin located at bit transition [s]

Integration Period = 1 ms

Figure 4.7: PCPS acquisition correlation PI = 1ms.

−10 −8 −6 −4 −2 0 2

x 10−3

0

1

2

3

4

5

6x 10

10

Acq

uisi

tion

Cor

rela

tion

Res

ult




−10 −8 −6 −4 −2 0 2

x 10−3

0

5

10

15x 10

10

Acq

uisi

tion

Cor

rela

tion

Res

ult




−10 −8 −6 −4 −2 0 2

x 10−3

0

0.5

1

1.5

2

2.5

x 1011

Acq

uisi

tion

Cor

rela

tion

Res

ult




In the previous figures, the time axis origin is located at a bit transition in the navigation message,

thus allowing the correlation operation over the integration period to become intentionally corrupted, so

as to exemplify the effect of the integration period parameter in the PCPS acquisition algorithm.

45

Figure 4.11: Acquisition map where the integra-

tion period does not include a bit transition.

Figure 4.12: Acquisition map where the integra-

tion period does include a bit transition.

Visible in the previous figures is the effect of a corrupted correlation over the integration period,

caused by the presence of a bit transition. Figures 4.7 through 4.10 represent the correlation result

of the PCPS acquisition algorithm, which is the maximum value of the acquisition map represented in

figures 4.11 and 4.12. In figure 4.12 the corrupting effect of the bit transition is visible in between the

two correlation peaks, on the correct doppler frequency shift, levelling the correlation value output of the

correct code phase shift to somewhere below the correlation floor. This value is not presented in figures

4.7 through 4.10 (it would be expected that all figures would present a decline to somewhere around 0),

because as explained earlier, the algorithm outputs the maximum value of the the calculated acquisition

map.

4.2.4 Frequency Refinement

The implemented frequency refinement structure defined in 3.2.3 is shown here. Continuing the PCPS

acquisition from 4.2.1 the following results were obtained

PRN Doppler [Hz] Code [sample]

1 7000 3987

11 5500 354

17 10000 402

20 8500 1251

23 11000 1587

32 6500 3691

Table 4.2: Acquisition text output of SDR4GPS without PFSS.

Attempting to begin tracking PRN 20 yields the following results

46

−1 −0.5 0 0.5 1

x 105

−5

0

5

x 104 Discrete−Time Scatter Plot

I prompt

Q p

rom

pt

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

−5

0

5

x 104 Bits of the navigation message

Time (s)

0.1 0.2 0.3 0.4 0.5

−1

−0.5

0

0.5

1

1.5

Time (s)

Am

plitu

de

Raw PLL discriminator

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

2

4

6

8

10x 104 Correlation results

Time (s)

0.1 0.2 0.3 0.4 0.5

−100

0

100

200

Time (s)

Am

plitu

de

Filtered PLL discriminator

0.1 0.2 0.3 0.4 0.5−0.4

−0.2

0

0.2

Time (s)

Am

plitu

de

Raw DLL discriminator

0.1 0.2 0.3 0.4 0.5

−10

−5

0

Time (s)

Am

plitu

de

Filtered DLL discriminator

√

I2E+ Q2

E√

I2P+ Q2

P√

I2L+ Q2

L

Figure 4.13: Unsuccessful tracking of PRN 20 with doppler shift value from PCPS acquisition.

Tracking of PRN 20 was unsuccessful, so the whole process is retried, this time with PFSS acquisition

on the detected satellites in PCPS. The following table represents the values updated with PFSS, using

fft length power = 8

PRN Doppler [Hz] Code [sample]

1 7032 3987

11 5529 354

17 9905 402

20 8307 1251

23 10809 1587

32 6464 3691

Table 4.3: Acquisition text output of SDR4GPS with PFSS.

Attempting to track PRN 20 with the updated doppler shift, yelds.

47

−10 −5 0 5

x 104

−5

0

5

x 104 Discrete−Time Scatter Plot

I prompt

Q p

rom

pt

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5−10

−5

0

5

x 104 Bits of the navigation message

Time (s)

0.1 0.2 0.3 0.4 0.5−0.5

0

0.5

1

Time (s)

Am

plitu

de

Raw PLL discriminator

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

2

4

6

8

10

x 104 Correlation results

Time (s)

0.1 0.2 0.3 0.4 0.5

0

50

100

Time (s)

Am

plitu

de

Filtered PLL discriminator

0.1 0.2 0.3 0.4 0.5−0.4

−0.3

−0.2

−0.1

0

0.1

0.2

Time (s)

Am

plitu

de

Raw DLL discriminator

0.1 0.2 0.3 0.4 0.5−12

−10

−8

−6

−4

−2

0

Time (s)

Am

plitu

de

Filtered DLL discriminator

√

I2E+ Q2

E√

I2P+ Q2

P√

I2L+ Q2

L

Figure 4.14: Successful tracking of PRN 20 with doppler shift value from PFSS acquisition.

After the PCPS acquisition returned the values of doppler frequency shift and code phase shift of

8500 Hz (500 Hz step used) and 1251 chips respectively for PRN 20, the acquired value of code phase

shift is applied on the local code replica to properly remove the C/A code from the incoming signal (by

multiplication).

−2 −1.5 −1 −0.5 0 0.5 1 1.5 2

x 106

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5x 109

X: 8307Y: 4.749e+09

Frequency [Hz]

Mag

nitu

de

Figure 4.15: FFT of incoming signal after C/A code removal.

Thus allowing the FFT to reveal the despreaded L1 signal at 8307 Hz. This value is then passed on

to the next phase of the SDR4GPS program, to properly begin tracking the signal.

48

4.3 PLL Tracking Loop

To assess the performance of the PLL tracking loop, all parameters are evaluated individually, to be able

to observe their particular influence on the loop. Although the proof is not shown here, the tests are

performed with knowledge that the DLL tracking loop is locked onto the C/A code and is stable, so there

is little or no influence from the DLL loop and also there is little or no influence from varying these param-

eters in the PLL loop on the DLL loop. All tests in this section were performed with pll noise bandwidth

Bn = 30 Hz, pll damping ratio ζ = 0.7, pll loop gain Kd = 1 and the tan−1 (QP /IP ) PLL discrimina-

tor, except in each specific subsection were these parameters are individually evaluated. A value of

pll loop gain Kd = 1 means that the filtered PLL discriminator output is equal to the frequency offset

from the acquired frequency in the acquisition phase of the program, i.e. the current tracked frequency

offset from the coarse value where the PLL started tracking.

4.3.1 Loop Noise Bandwidth

0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05−20

0

20

Time (s)

Am

plitu

de

Filtered PLL discriminator − Bn = 5 Hz

0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05−40−20

02040

Time (s)

Am

plitu

de


0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05−100

−500

50

Time (s)

Am

plitu

de


0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05−200−100

0100

Time (s)

Am

plitu

de


0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05

−400

−200

0

Time (s)

Am

plitu

de


Figure 4.16: Filtered PLL discriminator output for several values of PLL noise bandwidth Bn.

49

Varying the noise bandwidth Bn of the PLL loop, the previous graphics were obtained for the behavior of

the filtered phase detector (PLL discriminator) output, the Numerically Controlled Oscillator (NCO) input.

As predicted by equation 2.21 it is clear that with an increase in noise bandwidth, comes a faster

lock on the carrier wave and with a decrease in noise bandwidth, it takes longer to achieve a lock on the

carrier wave. But since the noise bandwidth controls the amount of noise allowed in the loop, it is also

clear that a quicker lock comes at a price. The faster the lock is achieved, the more jitter will be present

in the NCO command and the longer the loop takes to lock onto the carrier, the more closely the carrier

is followed with less jitter. So there is a trade off between setting time and jitter in the NCO command.

In the extreme cases, there is the too low noise bandwidth (Bn = 5 Hz) that cannot follow the incoming

signal properly because it is not fast enough, on the other hand there is the too high bandwidth (Bn = 70

Hz) that does not allow the NCO to properly converge to the correct incoming frequency, because it over

corrects the frequency at every step.

Although it is not shown here in this set of graphics, the test with Bn = 5 Hz does eventually converge

to the correct frequency of the carrier at around 500 ms, whereas the test with Bn = 70 Hz does not.

0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1−1

−0.5

0

0.5

1x 105

Time (s)

Am

plitu

de

Bits of the navigation message − Bn = 10 Hz

0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

−1

−0.5

0

0.5

1x 105

Time (s)

Am

plitu

de

Bits of the navigation message − Bn = 20 Hz

Figure 4.17: Bits of the navigation message for several values of PLL noise bandwidth Bn.

Once lock is achieved, a similar tracking occurs for all tested values of noise bandwidth Bn.

4.3.2 Loop Damping Ratio

As seen in figure 4.18 and equation 2.21, the settling time of the loop varies in accordance to the

damping ratio ζ much in the same way as it does to the noise bandwidth Bn, except that no matter how

close to 1 the damping ratio is, the loop still converges to the correct frequency.

50

0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

0204060

Time (s)A

mpl

itude

Filtered PLL discriminator − damping ratio = 0.15

0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1−20

0204060

Time (s)

Am

plitu

deFiltered PLL discriminator − damping ratio = 0.2

0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

−50

0

50

Time (s)

Am

plitu

de


0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1−150−100

−500

50

Time (s)

Am

plitu

de


0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

−1000

100

Time (s)

Am

plitu

de


Figure 4.18: Filtered PLL discriminator output for several values of PLL damping ratio ζ.

For ζ > 1/√

2, the behavior of the loop remains practically unchanged.

Also, observing more closely the filtered PLL discriminator output between 0.05 and 0.1 seconds for

ζ = 0.2 and 0.35 reveals

0.05 0.055 0.06 0.065 0.07 0.075 0.08 0.085 0.09 0.095 0.140

42

44

46

48

50

Time (s)

Am

plitu

de


0.05 0.055 0.06 0.065 0.07 0.075 0.08 0.085 0.09 0.095 0.130

35

40

45

50

55

60

Time (s)

Am

plitu

de


Figure 4.19: Zoomed in filtered PLL discriminator output for several values of PLL damping ratio ζ.

51

Although both graphics have a very similar result, there is a different scaling sensitivity. Again, as

with the noise bandwidth, a smaller value of the damping ratio ζ allows the loop to follow more closely

the incoming carrier wave, but this trait is not so prevalent with the noise bandwidth, hence it was not

shown.

4.3.3 Loop Gain

As predicted by equations 3.14, 3.15 and 3.17, the loop gain Kd should have the inverse effect on the

loop as the noise bandwidth Bn, as proved by the following figure

0.02 0.04 0.06 0.08 0.1 0.12 0.14

−5000

500

Time (s)

Am

plitu

de

Filtered PLL discriminator − loop gain Kd = 0.2

0.02 0.04 0.06 0.08 0.1 0.12 0.14−200

0

200

Time (s)

Am

plitu

de


0.02 0.04 0.06 0.08 0.1 0.12 0.14−150−100−50

050

Time (s)

Am

plitu

de


0.02 0.04 0.06 0.08 0.1 0.12 0.14−50

0

50

Time (s)

Am

plitu

de

Filtered PLL discriminator − loop gain Kd = 2

0.02 0.04 0.06 0.08 0.1 0.12 0.14−20

02040

Time (s)

Am

plitu

de

Filtered PLL discriminator − loop gain Kd = 5

Figure 4.20: Filtered PLL discriminator output for several values of PLL loop gain Kd.

With Kd = 0.2, no lock was attained.

4.3.4 NCO Gain

It was only after implementing the NCO gain Ko, when testing, that it was discovered that even though

the filtered PLL discriminator output became smaller by a scaling factor although retaining the same

52

shape, the final frequency used in bringing the incoming signal to baseband, remained exactly the

same. This happens due to the fact that the inverse z-transform of F (z) is proportional to C1 and C2,

which in turn are inversely proportional to τ1, which is proportional to the loop gain Ko. So by multiplying

the filtered PLL discriminator output by the NCO gain Ko (thus becoming the NCO input), its influence

in the loop is removed, rendering its value arbitrary.


After the normalization of the first (QP × IP ) and second (QP × sign(IP )) discriminators, almost all of

the implemented and tested discriminators behaved the same way, except for the first discriminator that

showed a bit more of a noisy raw discriminator output, even though this didn’t have a noticeable effect

on the demodulation of the navigation message.

0.1 0.2 0.3 0.4 0.5

20

40

60

80

Time (s)

Am

plitu

de (

Hz)

Filtered PLL discriminator 1 output

0.1 0.2 0.3 0.4 0.5

20

40

60

80

Time (s)

Am

plitu

de (

Hz)


0.1 0.2 0.3 0.4 0.5

20

40

60

80

Time (s)

Am

plitu

de (

Hz)


0.1 0.2 0.3 0.4 0.5

20

40

60

80

Time (s)

Am

plitu

de (

Hz)


Figure 4.21: Filtered PLL discriminator output when using different discriminators.

In the previous figure, discriminators 1 through 4 represent discriminators QP × IP , QP × sign(IP ),

QP /IP and tan−1(QP /IP ) respectively.

4.4 DLL Tracking Loop

Similarly to 4.3, to assess the performance of the DLL tracking loop, all parameters are evaluated in-

dividually, to be able to observe their particular influence on the loop. Although the proof is not shown

here, the tests are performed with knowledge that the PLL tracking loop is locked onto the carrier wave

and is stable, so there is little or no influence from the PLL loop and also there is little or no influence

from varying these parameters in the DLL loop on the PLL loop. All tests in this section were performed

with dll correlator spacing = 0.5 chips, pll noise bandwidth Bn = 30 Hz, dll damping ratio = 0.7,

53

dll nco gain = 1 and the normalized early minus late power DLL discriminator, except in each specific

subsection were these parameters are individually evaluated. A value of dll loop gain = 1 means that

the filtered DLL discriminator output is equal to the frequency offset from the nominal frequency of the

C/A code (1.023 MHz), of the incoming C/A signal.

4.4.1 Correlator Spacing

The following graphics show the influence of the correlator spacing on the DLL discriminator output.

0.1 0.2 0.3 0.4 0.5

2468

1012


Time (s)

0.1 0.2 0.3 0.4 0.5−0.4

−0.20

0.2

0.4

Time (s)

Am

plitu

de

DLL discriminator output − correlator spacing = 0.01 chips

0.1 0.2 0.3 0.4 0.5

2468

1012


Time (s)

0.1 0.2 0.3 0.4 0.5−0.4

−0.20

0.2

0.4

Time (s)

Am

plitu

de


0.1 0.2 0.3 0.4 0.5

2468

1012


Time (s)

0.1 0.2 0.3 0.4 0.5−0.4

−0.20

0.2

0.4

Time (s)

Am

plitu

de


0.1 0.2 0.3 0.4 0.5

2468

1012


Time (s)

0.1 0.2 0.3 0.4 0.5−0.4

−0.20

0.2

0.4

Time (s)

Am

plitu

de


0.1 0.2 0.3 0.4 0.5

2468

1012


Time (s)

√

I2E+ Q2

E√

I2P+ Q2

P√

I2L+ Q2

L

0.1 0.2 0.3 0.4 0.5−0.4

−0.20

0.2

0.4

Time (s)

Am

plitu

de


Figure 4.22: Correlation results and DLL discriminator output for several values of correlator spacing.

54

When the prompt code is not perfectly aligned with the incoming C/A signal, a larger value of cor-

relator spacing will make the correlation values of the early and late codes more distinct, allowing the

discriminator to better correct the difference. But this advantage come with a cost, the larger the corre-

lator spacing, the less smoother the DLL discriminator output will be, because the correlators value for

early and late replicas are too low, to allow a proper distinction.

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5−1

0

1x 105

Time (s)

Am

plitu

de

Bits of the navigation message − correlator spacing = 0.01 chips

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5−1

0

1x 105

Time (s)

Am

plitu

de


0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

−1

0

1x 105

Time (s)

Am

plitu

de


Figure 4.23: Bits of the navigation message for several values of correlator spacing.

Under noisy conditions, with a small signal SNR, a low value of correlator spacing (all correlators

output a similar value, because all three codes are almost equally spaced) will not allow the discriminator

to properly correct the code phase offset and eventually loose the lock on the incoming C/A signal.

4.4.2 Loop Noise Bandwidth

Much like in the PLL loop, here in the DLL loop, the increase of the noise bandwidth Bn allows for a

faster lock on the incoming C/A signal, but too much of an increase and the filtered DLL discriminator

output will have a noisy and irregular characteristic, over correcting the code frequency.

55

0.2 0.4 0.6 0.8 1 1.2 1.4−10

−5

0

Time (s)

Am

plitu

deFiltered DLL discriminator − noise bandwidth B

n = 1 Hz

0.2 0.4 0.6 0.8 1 1.2 1.4−1

0

1x 105

Time (s)

Am

plitu

de

Bits of the navigation message

0.2 0.4 0.6 0.8 1 1.2 1.4−10

−5

0

Time (s)

Am

plitu

de

Filtered DLL discriminator − noise bandwidth Bn = 1.5 Hz

0.2 0.4 0.6 0.8 1 1.2 1.4

−1

0

1

x 105

Time (s)

Am

plitu

de


0.2 0.4 0.6 0.8 1 1.2 1.4−10

−5

0

Time (s)

Am

plitu

de

Filtered DLL discriminator − noise bandwidth Bn = 2 Hz

0.2 0.4 0.6 0.8 1 1.2 1.4

−1

0

1

x 105

Time (s)

Am

plitu

de


0.2 0.4 0.6 0.8 1 1.2 1.4−10

−5

0

Time (s)

Am

plitu

de


0.2 0.4 0.6 0.8 1 1.2 1.4

−1

0

1

x 105

Time (s)

Am

plitu

de


0.2 0.4 0.6 0.8 1 1.2 1.4−10

−5

0

Time (s)

Am

plitu

de


0.2 0.4 0.6 0.8 1 1.2 1.4

−1

0

1

x 105

Time (s)

Am

plitu

de


Figure 4.24: Filtered DLL discriminator and Bits of the navigation message for several values of DLL

noise bandwidth Bn.

With the noise bandwidth Bn = 1.5 Hz, an inversion in the signal of the incoming navigation message

bits is observed around second 0.6. This is due to the fact that when the DLL loop is near loosing track

of the incoming C/A signal, this affects the PLL loop, in this case, when updating the carrier frequency

to use in bringing the incoming signal to baseband, a multiple of a half period is added to the correction,

causing the inversion in the signal of the signal brought to baseband.

56

4.4.3 Loop Damping Ratio

Although increasing the damping factor ζ decreases the lock time, it also increases the jitter present in

the signal. The effect of the damping ratio ζ on the DLL loop, differs a bit from its effect on the PLL loop.

There is a oscillatory behavior to the filtered DLL discriminator output for low values of the damping

factor ζ, but on the other hand, the jitter presence is hampered.

0.5 1 1.5 2 2.5 3 3.5 4

−8−6−4−2

0

Time (s)

Am

plitu

de

Filtered DLL discriminator − damping ratio = 0.05

0.5 1 1.5 2 2.5 3 3.5 4−1

0

1x 105

Time (s)

Am

plitu

de


0.5 1 1.5 2 2.5 3 3.5 4

−8−6−4−2

0

Time (s)

Am

plitu

de


0.5 1 1.5 2 2.5 3 3.5 4

−1

0

1x 105

Time (s)

Am

plitu

de


0.5 1 1.5 2 2.5 3 3.5 4

−8−6−4−2

0

Time (s)

Am

plitu

de


0.5 1 1.5 2 2.5 3 3.5 4

−1

0

1

x 105

Time (s)

Am

plitu

de


0.5 1 1.5 2 2.5 3 3.5 4

−8−6−4−2

0

Time (s)

Am

plitu

de


0.5 1 1.5 2 2.5 3 3.5 4

−1

0

1

x 105

Time (s)

Am

plitu

de


0.5 1 1.5 2 2.5 3 3.5 4

−8−6−4−2

0

Time (s)

Am

plitu

de


0.5 1 1.5 2 2.5 3 3.5 4

−1

0

1

x 105

Time (s)

Am

plitu

de


Figure 4.25: Filtered DLL discriminator and Bits of navigation message for several values of DLL damp-

ing ratio ζ.

For ζ > 1/√

2, the behaviour of the loop remains practically unchanged and no lock was obtained for

ζ = 0.05.

4.4.4 Loop Gain

For Kd > 7, no visible change in the bits of the navigation message is observed and the filtered DLL

discriminator output remains its shape, but its scaling is smaller.

For extreme values of the loop gain Kd (bigger than 7 and smaller than 0.003), the loop cannot attain

57

0.5 1 1.5 2

−2000

0

2000

Time (s)

Am

plitu

deFiltered DLL discriminator − loop gain K

d = 0.003

0.5 1 1.5 2

−5

0

5

x 104

Time (s)

Am

plitu

de


0.5 1 1.5 2

−1000

0

1000

Time (s)

Am

plitu

de

Filtered DLL discriminator − loop gain Kd = 0.005

0.5 1 1.5 2−1

0

1x 105

Time (s)

Am

plitu

de


0.5 1 1.5 2

−6

−4

−2

Time (s)

Am

plitu

de

Filtered DLL discriminator − loop gain Kd = 1

0.5 1 1.5 2

−1

0

1

x 105

Time (s)

Am

plitu

de


0.5 1 1.5 2

−6

−4

−2

Time (s)

Am

plitu

de


0.5 1 1.5 2

−1

0

1

x 105

Time (s)

Am

plitu

de


0.5 1 1.5 2−5−4−3−2−1

Time (s)

Am

plitu

de


0.5 1 1.5 2−1

0

1x 105

Time (s)

Am

plitu

de


Figure 4.26: Filtered DLL discriminator and Bits of navigation message for several values of DLL loopgain Kd.

lock on the incoming C/A signal, due to the fact that the output of the filter controls equals to the NCO

command and in these cases, either it over corrects the code frequency or it cannot follow the acquired

code phase. For values of the loop gain Kd between those extremes, the higher its value, the closer the

loop tracks the code phase of the incoming C/A signal, while on the other hand, the lower the value, the

more jitter exists and the bigger its influence is on the filtered DLL discriminator output. Also, for higher

values of the loop gain Kd, some oscillatory characteristic is present in the filtered DLL discriminator

output.

58

4.4.5 NCO Gain

As explained in 4.3.4 the effect of the NCO gain Ko in the DLL loop is also non existent, so no tests were

performed.


As mentioned in subsection 3.3.2, ultimately only two DLL discriminators were implemented, the nor-

malized noncoherent early minus late power (E2−L2

E2+L2 ) and the normalized coherent/dot product ( IE−ILIP).

The following figure presents the output of the filtered DLL discriminator when using both these discrim-

inators.

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

−10

−5

0

Time (s)

Am

plitu

de (

Hz)

Filtered normalized power DLL discriminator output

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

−10

−5

0

Time (s)

Am

plitu

de (

Hz)

Filtered normalized dot product / coherent DLL discriminator output

Figure 4.27: Filtered DLL discriminator output when using different discriminators.

The previous figure shows the normalized dot product / coherent discriminator tracking the code

more closely than the normalized power discriminator. According to figure 2.15, this result is expected.

While the normalized power discriminator over corrects the current code phase offset, both the coherent

and the dot product discriminators always present a lower code phase offset output than the normal-

ized power discriminator. Also, no difference was noticeable between both discriminators demodulated

navigation message.

59

60

Chapter 5

Conclusions

This last chapter finalizes this work, summarizing conclusions from several chapters, presenting the

main results, which techniques and models proved useful and also analyzing the limitations of the work

itself. Continuing by pointing out aspects and directions to be developed in future work.

61

5.1 Achievements

The work presented thus far, allowed the development of a successful software-defined GPS receiver for

C/A L1 signals using a MATLAB R© coded framework for analysis and post-processing of said recorded

signals and a system performance testbed of the acquisition and tracking module algorithms that com-

pose it. Regarding acquisition, a PCPS algorithm with a PFSS frequency refinement algorithm aid was

implemented allowing for a proper acquisition of doppler shift in the incoming L1 signal and the code

phase shift in the incoming C/A signal, to be delivered to the tracking algorithm of the program for further

processing. In implementing the tracking module of the program, a combined PLL and DLL digitally

modelled loop was chosen which proved successful in tracking both the L1 and C/A signals, thus, suc-

cessfully extracting the navigation message signal, but not converting it yet to a bitstream.

5.1.1 Acquisition

The implementation of the PCPS algorithm was a straightforward one, although, not being successful in

recording satellite signals to experiment with, prompted the investigation to focus on searching for freely

available signal records on the internet, even asking companies of the space sector for them. Eventually

4 signal records were obtained, with sampling frequencies ranging from 4 MHz to 16.3676 MHz and

with 8 and 16 signed integer bits of data types with quadrature sampled signals, with quadrature and

in-phase samples interleaved allowing implementation to proceed using those signals.

Testing the implemented acquisition algorithm on the stored signals, proved successful using the suffi-

cient 500 Hz step in frequency search, in detecting visible satellites, but in some cases a PFSS frequency

refinement was required to allow a proper tracking of the incoming carrier. All code phase shifts acquired

in PCPS were already the best estimate possible, with a code phase step of ≈ 3.91 samples per chip for

a sampling frequency of 4 MHz.

5.1.2 Tracking

Implementing the tracking algorithms was a bit more problematic, because the used linear model ap-

proximation of the PLL and DLL loops weren’t as direct to implement in the system, as it happened in

acquisition. The two parts of the tracking algorithm most altered from their expected design, were the

mixing, in which a complex sinus wave was used, instead of a regular real signal sinus wave because

of the advantage of already having available the in-phase and quadrature components of the incoming

signal and the other significant change was NCO command, whose original N(s) function was replaced

by a direct digital frequency synthesizer and then it was altered to remove its cumulative properties that

conflicted with the loop filter.

One limitation of the developed tracking algorithm is the fact that the integration period for the correlators

is fixed at 1 millisecond, it does not follow the same philosophy of a software-defined system that the

rest of the implemented program does. If a larger value of integration period of the correlators were

62

to be used, a finer resolution of all tracking signals would be obtained, consequently there would be a

more accurate tracking of all signals. Of course this would come with a greater computational cost, not

advised while the platform is a MATLAB R© written program.

Regarding the performance of the implemented tracking loop, overall, the linear model approximation

of a PLL and DLL tracking loop is verified as a valid and feasible approach, that correctly predicts the

behaviour of the system, as confirmed by the variation of the loop parameters in chapter 4. As expected

the noise bandwidth Bn and the damping ratio ζ were the prime conductors of the loop characteristic

and could be used to control it, while the loop gain Kd could be set to 1 so as to reduce the complexity

of managing the program. Both in the PLL and DLL loop, the increase in either the damping ratio ζ or

the noise bandwidth Bn achieved a faster lock on the incoming signal, but added a noisy characteristic

to the system signals, without affecting the extracted navigation message signal, only the lock time.

Judging by the expected behavior of the system by varying the damping ratio ζ, it is clear that the DLL

loop is better modeled with the implemented second order loop system, than the PLL loop. The oscilla-

tory characteristic of the filtered DLL discriminator output is more prevalent in the DLL loop than in the

PLL loop. Also, the same signal behaviours take more time to manifest themselves in the DLL loop than

in the PLL loop, i.e. the both loops behave somewhat similarly with a different time scale. On a more

practical note, both the DLL and PLL discriminators only functioned properly with normalized outputs,

even thought some discriminators are designed to work without that normalization since all discrimina-

tors tend to obtain a close value of the phase error between the incoming signal and the generated one,

when this error is a small one. This may be attributed to the 1 ms integration period of the correlators,

not allowing the loop to more closely track the incoming signals.

5.2 Future Work

The developed software allows future work to be developed in completing the current platform, continu-

ing the SDR4GNSS project, even expanding it beyond its original designation and other possible ideas.

Thus, some topics are presented:

• Completing the current platform:

– add navigation message decoding,

– add pseudoranges estimation,

– add position solving;

• Continuing the SDR4GNSS project:

– add GALILEU support for multi-constellation global navigation,

– also add GLONASS support;

• Expanding SDR4GNSS functionality:

– implementation of different algorithms in all phases of data processing (acquisition, tracking,

decoding...)

• Adding additional functionalities to SDR4GNSS:

63

– add a Graphical User Interface,

– add IF real signals support,

– add real-time support for SDR ready peripherals, such as USB dongles (RTL-SDR), Universal

Software Radio Peripheral (USRP) and other types of devices,

– transform SDR4GNSS source code to other programming languages, such as C++, Python

or Java.

The following diagram represents a possible future SDR4GPS program.

Signal Source(Recorded Samples)

Settings

Aquisition Results(Doppler Frequency Shift, C/A

Code Phase, etc...)

Acquisition• Parallel Code Phase Search• Parallel Frequency Space Search

Tracking • PLL Loop • DLL Loop

SDR4GPS FutureFramework

Signal Processing Chain

Navigation Message Decoding

Position Solving• NMEA• RINEX

Orbital Parameters

Observables (Pseudoranges)

Tracking Results(Correlators, PLL and DLL

Frequency, Navigation Message, etc...)

Position, Velocity, etc...

Data Processing

Figure 5.1: Flow diagram of a possible future SDR4GPS program.

64

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67

68

Appendix A

Extended Mathematical Analysis

This appendix deals with the solving of several mathematical expressions throughout this thesis. Expres-

sions that were too lengthy to be present in their complete form, but in this appendix, they are explained

in detail.

A.1 Second Order PLL System H(s)

The extended calculation to obtain of the transfer function of the frequency domain model of the PLL

H(s) in order of the system parameters ωn (natural frequency) and ζ (damping ratio) mentioned in

equation 2.17 is explained as

F (s) =τ2s+ 1

τ1s

N(s) =Ko

s

H(s) =KdF (s)N(s)

1 +KdF (s)N(s)

H(s) =

KdKo(τ2s+1)s2τ1

1 + KdKo(τ2s+1)s2τ1

=KdKo(τ2s+ 1)

s2τ1 +KdKo(τ2s+ 1)=

KdKoτ2s+KdKo

s2τ1 +KdKoτ2s+KdKo=

=

KdKoτ2τ1

s+ KdKo

τ1

s2 + KdKoτ2τ1

s+ KdKo

τ1

=2ζωns+ ω2

n

s2 + 2ζωns+ ω2n

(A.1)

where

ωn =

√KoKd

τ1and ζ =

ωnτ22

69

A.2 Noise Bandwidth Bn of H(s)

Following from 2.20, the final expression of the noise bandwidth Bn calculated as

Bn =

∫ ∞0

∣∣∣H(s)∣∣∣2 df

(A.2)

where H(s) is the transfer function of the frequency domain model of the PLL described in equation

2.17, is explained as follows

Bn =

∫ ∞0

∣∣∣H(s)∣∣∣2 df =

ωn2π

∫ ∞0

1 +(

2ζ ωωn

)2[1−

(ωωn

)2]2+(

2ζ ωωn

)2 dω =

=ωn2π

∫ ∞0

1 + 4ζ2(ωωn

)2(ωωn

)4+ 2(2ζ2 − 1)

(ωωn

)2+ 1

dω =ωn2

(ζ +

1

4ζ

)(A.3)

A.3 Bilinear Transform of F (s)

Applying the bilinear transform

s =2

Ts

1− z−1

1 + z−1(A.4)

to the analog PLL loop filter transform function described in equation 2.15

F (s) =τ2s+ 1

τ1s

yields the following digital frequency domain pll loop filter

F (z) =2τ2Ts

1−z−1

1+z−1 + 12τ1Ts

1−z−1

1+z−1

=2τ2(1− z−1) + (1 + z−1)Ts

2τ1(1− z−1)=

2τ22τ1

+Ts2τ1

1 + z−1

1− z−1=

=2τ22τ1

+Ts2τ1

(2

1− z−1− 1

)=

2τ2 − Ts2τ1

+Tsτ1

(1

1− z−1

)= C1 +

C2

1− z−1(A.5)

where

C1 =2τ2 − Ts

2τ1and C2 =

Tsτ1

70

A.4 Inverse Z-Transform of F (z)

The calculation of the Inverse Z-Transform of the digital PLL Filter function F (z) shown in equation 3.3.4

is explained in detail as follows

F (z) = C1 +C2

1− z−1

F (z) =Y (z)

X(z)⇔ Y (z) = F (z)X(z)⇔ Y (z) =

(C1 +

C2

1− z−1

)X(z) =

= C1X(z) +C2X(z)

1− z−1⇔ Y (z)(1− z−1) = C1(1− z−1)X(z) + C2X(z)⇔

⇔ Y (z)− z−1Y (z) = C1X(z)− C1z−1X(z) + C2X(z) (A.6)

after applying the inverse Z-Transform to the previous equation, the results is a usable program com-

mand

y[n]N(z) − y[n− 1] = C1x[n]− C1x[−1] + C2x[n]⇔

⇔ y[n]N(z) = y[n− 1] + C1(x[n]− x[n− 1]) + C2x[n] (A.7)

71

72

Appendix B

C/A Code Generation

The C/A code generation is obtained from the Interface Specification IS-GPS-200 which defines the

requirements related to the interface between the GPS space and user segments for the L1 and L2

carriers. As mentioned in subsection 2.1.2, the two maximum-length sequences used to create the C/A

code referred to as G1 and G2i (the G2i sequence is formed by delaying the G2 sequence by an integer

number of chips), are driven by a 1.023 MHz clock and generated by a 10-stage shift register, having the

following polynomials as referred to in the shift register input

G1 = 1 +X3 +X10 (B.1)

G2 = 1 +X2 +X3 +X6 +X8 +X9 +X10 (B.2)

the initialization vector for the G1 and G2 sequences is 1111111111. The following structures repre-

sent the shift register generator configuration of G1 and G2.

Figure 3-8. G1 Shift Register Generator Configuration

1 1

2 1

3 1

4 1

5 1

6 1

7 1

8 1

9 1

10 1

STAGE NUMBERS

INITIAL CONDITIONS

SHIFT DIRECTION

0 1 2 3 4 5 6 7 8 9 10

OUTPUT

TAP NUMBERS

POLYNOMIAL G1: 1 + X 3 + X 10

INPUT

32 IS-GPS-200H 24 Sep 2013

Figure B.1: G1 shift register generator configuration.

73

Figure 3-9. G2 Shift Register Generator Configuration

1 1

2 1

3 1

4 1

5 1

6 1

7 1

8 1

9 1

10 1

STAGE NUMBERS

INITIAL CONDITIONS

SHIFT DIRECTION

0 1 2 3 4 5 6 7 8 9 10

OUTPUT

TAP NUMBERS

POLYNOMIAL G2: 1 + X 2 + X 3 +X 6 + X 8 + X 9 + X 10

INPUT

33 IS-GPS-200H 24 Sep 2013

Figure B.2: G2 shift register generator configuration.

The effective delay of the G2 sequence to form the G2i sequence may be accomplished by combin-

ing the output of two stages of the G2 shift register by modulo-2 addition. The following table presents

the code phase assignment to generate the appropriate C/A code

Satellite ID Code Phase Code Delaycontinuation...

GPS PRN Number Selection Chips

1 2 ⊕ 6 5 17 1 ⊕ 4 469

2 3 ⊕ 7 6 18 2 ⊕ 5 470

3 4 ⊕ 8 7 19 3 ⊕ 6 471

4 5 ⊕ 9 8 20 4 ⊕ 7 472

5 1 ⊕ 9 17 21 5 ⊕ 8 473

6 2 ⊕ 10 18 22 6 ⊕ 9 474

7 1 ⊕ 8 139 23 1 ⊕ 3 509

8 2 ⊕ 9 140 24 4 ⊕ 6 512

9 3 ⊕ 10 141 25 5 ⊕ 7 513

10 2 ⊕ 3 251 26 6 ⊕ 8 514

11 3 ⊕ 4 252 27 7 ⊕ 9 515

12 5 ⊕ 6 254 28 8 ⊕ 10 516

13 6 ⊕ 7 255 29 1 ⊕ 6 859

14 7 ⊕ 8 256 30 2 ⊕ 7 860

15 8 ⊕ 9 257 31 3 ⊕ 8 861

16 9 ⊕ 10 258 32 4 ⊕ 9 862

Table B.1: Code Phase assignments for C/A code generation.

74

Combining the G1 and G2 code generators as suggested in the IS-GPS-200, a C/A code generator

can be assembled such as

Figure 3-10: Example C/A-Code Generation

Valid for C/A PRNs 1-37. For PRNs 38-63, the G1 Register should be XOR-ed directly to the G2 Register in order

to make Gi. These PRNs do not use the Phase Select Logic box for G2i generation.

10

S C

I

C S

I

G1 REGISTER

2 3 6 8 9 10

G2

3

10

10.23 MHz

SYNCH

X1 EPOCH

20

SYNCH

G EPOCH 1 Kbps

1023 DECODE

50 bps TO DATA ENCODER

PHASE SELECT LOGIC

G2 i

G1

REGISTER INPUTS

C - CLOCK I - INPUT S - SET ALL ONES

G i

34 IS-GPS-200H 24 Sep 2013

Figure B.3: Example of a C/A code generation structure.

75

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Documents

Post-Processed Acquisition & Tracking of GPS C/A L1 Signals · In this thesis, two GPS C/A L1 signal acquisition algorithms are implemented and evaluated, the Parallel Frequency Space