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Presenter: Matt Reynolds / Suresh Chandran

PLZT (lead-lanthanum-zirconium-titanate) Capacitors

for High Frequency Operation

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New demands on DC-link capacitors

Requirements for a DC link

capacitor

High capacitance density

High current density

Low parasitic values (ESR / ESL) for fast

switching

Low losses in operation

High operating and peak temperatures

High cooling efficiency due to high thermal

conductivity

Support of distributed DC link capacitor

topologies with low inductance components

(modular design)

Improvements in power density and efficiency

were mainly driven by semiconductor

technology in the last decade.

Example: principle block picture and size comparison of a

motor inverter

“Today the package of a motor inverter is

mainly driven by the size of the capacitor, the

bus bars, the terminal box and the filter

components.”

from:Plikat, Mertens, Koch, Volkswagen AG, Corporate Research,

2013

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How does PLZT Capacitor meet these requirements?

TDK PLZT Capacitor is meeting the demands on three levels:

Innovative

MaterialCeramic chip

features

Optimized

Packaging

High capacitcance

density

High current densityLow parasitic values

Low losses

High operating and

peak temperatures

High cooling efficiency

Modular design

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PLZT – comparison to other materials

Nature of electrical

polarizationelectronic, ionic

permanent dipoles form

ferroelectric domains

permanent dipoles form

antiparallel zones

Material class (Ba,Nd)TiO, typ. NP0, C0G BaTiO3 (BTO), typ. X7R (Pb,La)(Zr,Ti)O3 (PLZT)

Advantagesε constant over electric field

and temperatureε up to 10,000 is possible

ε increases with field

Disadvantages ε < 100ε decreases strongly with

electrical fieldε low at zero bias

P Dielectric polarization

E Electrical field strength

ε Dielectric constant.

P

E

E

ε

P

E

E

ε

P

E

E

ε

FerroelectricLinear Antiferroelectric

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High capacitance density under electrical field

• Due to antiferroelectic behaviour,

CeraLink‘s features are strongly non-linear

and optimized for conditions under

operation in power electronics

• Film capacitors and class 1 ceramics have

a dielectric constant (nearly) independent

on the electrical field.

(ε < 100)

• The permittivity of ferroelectric (BTO)

MLCC capacitors is decreasing with

electrical field

• CeraLink™ features an increasing

dielecric constant up to the operating

voltage

• At higher AC voltage (peaks), the material

is able to provide even higher permittivies

DC bias characteristics

at room temperature4000

3000

2000

1,000

0

Die

ele

ctr

icc

on

sta

nt

Electric field [V/µm]

0 2 4 6 8 10 12

MKP film

capacitor

BTO Class

2 MLCC

CeraLink

™

Nominal / rated capacitance 100 % 100 % 100 %

No bias voltage 0.5 VRMS 100% 100 % 35 %

DC link voltage 0.5 VRMS 100 % 35 % 60 %

DC link voltage 20 VRMS 100 % 35 % 100 %

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High current density – low self heating

• Due to low losses at high

temperaure and high

frequency, CeraLink™ can

carry more current under these

conditions

Measurement conditionMKP film

capacitor

BTO Class

2 MLCC

CeraLink

™

Typical capacitance density

@ DC link voltage, 20 VRMS, 25°C0.7 µF/cm³ 2.5 µF/cm³ 4.9 µF/cm³

Typical current rating

per capacitance @ 100 kHz, 105°C< 1 A/µF < 4.5 A/µF 12 A/µF

Measurements were carried out without active cooling (no forced air flow, no heat sink)

Comparison @ 400 VDC, 105 °C, 200 kHz Comparison @ 400 VDC, 85 °C, 5 Arms

5

0 0

Te

mp

era

ture

incre

ase

[°C

]

Te

mp

era

ture

incre

ase

[°C

]

Frequency [kHz]Current [Arms]

0 1 2 3 4 5 6 20 40 60 80 120100

10

15

20

25

30

10

20

30

40

50

60

70

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Comparison @ 400 VDC

Low leakage current at high temperatures

1µF

1µF

CeraLink shows stable and outstanding high isolation properties compared to all

existing capacitor technologies

low leakage current at elevated temperatures even above 150°C

No thermal runaway observed for CeraLink ceramic material

Temperature [°C]

ρ[Ω

m]

1013

1012

1011

1010

20 40 60 80 120100 140 160

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Exceptional lifetime at high temperatures

Lifetime @ 200 °C more than one order of magnitude higher than that of

conventional ceramic capacitors.

100,00010,0001,000100101

99

90807060504030

20

10

5

3

2

1

TTF [min]

Pe

rc

en

t

BTO X7T

BTO X7R / X7T

CeraLink

Highly accelerated life test (HALT) 200°C / 600 VDC

Weibull - 95% CI

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Characteristic lifetime at 200 °C and 600 V

CeraLink offers highest lifetime and highest capacitance density

compared to conventional ceramic capacitors.

Lifetime at high temperatures - comparison of

ceramic capacitors

100,000

10,000

1,000

100

10

1

0 1 2 3 4 5 6

Capacitance density [µF/cm3]

Ch

ara

cte

ris

tic

life

tim

e[m

in]

CeraLinkTM

Class 2 MLCCs (BTO ceramic)

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Low parasitic values

Device characteristics lead to a low inductive

commutation loop

Low self-inductance (ESL) of 2.5 to 4 nH

High capacitance density of 2 to 5 µF/cm³

High thermal robustness allows PLZT to be placed

very close to the semi-conductor with operation up

to 150 °C permissible

System-enabled benefits lead to miniaturization

Lower voltage overshoot during semiconductor

switching

Faster switching with higher di/dt and dv/dt

values decrease the switching losses

Higher switching frequencies achievable

<<ESL

<<Lσ

0

10

20

30

40

50

60

70

80

90

100

0

100

200

300

400

500

600

Time [ns]

PLZT

Se

mic

on

du

cto

r s

wit

ch

ing

vo

lta

ge

[V

]

Se

mic

on

co

llec

tor

cu

rren

t[A

]

0 1600 3200 4800 6400 8000 9600

Semiconductor overshoot principle

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21

35

6

7

4

Typical Ceramic based

PLZT Capacitor Constructionnr. name material

1 Dielectric ceramic

PLZT

2 electrode Cu

3 sputterlayer

Cr Ni Ag

4 sinter silver Ag

5 lead frame Cu Fe Ni

6 coating Ag

7 adhesive epoxy resin

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Key benefits of PLZT

Effective capacitance increases with rising

voltage and leads to high capacitance density

Low ESL and low inductive connection

Low ESR especially at high frequencies

and high temperatures

High current density

High operating and peak temperatures

with temperature excursions up to 150°C

High robustness against high temperatures

Supports fast-switching semiconductors

and high switching frequencies

Supports further miniaturization of power

electronics at the system level

Summary

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Nominal capacitance / rated

voltage

Designed for 650V

semiconductors

Designed for 900V

semiconductors

Designed for 1300V

semiconductors

Low Profile series

LP (L leads)

1µF / 500V

Released

0.5µF / 700V

Released

0.25µF / 900V

Released

Low profile series

LP (J leads)

1µF / 500V

Released

0.5µF / 700V

Released

0.25µF / 900V

Released

Flex Assembly

FA1010µF / 500V

Samples available

5µF / 700V

Samples available

2.5µF / 900V

Samples available

Flex Assembly

FA2 / FA32/3µF / 500V

Samples available

1/1.5µF / 700V

Samples available

0.5/0.75µF / 900V

Samples available

Solder Pin series

SP

20µF / 500V

Released

10µF / 700V

Released

5µF / 900V

Released

Device portfolio

All products shown share the same ceramic material. Different voltage performance is adjusted by internal layer thickness.

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Typical Impedance and ESR vs Frequency

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Typical permissible current vs frequency