“Placement for Hierarchical Interconnect basedFPGA Devices”

A final project report submittedby

Kesava R. Talupuruktalupur@ecs.umass.edu

ID: 998-10-3850

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Why FPGAs Came in to Existence:

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Some of the benefits of programmable logic versus mask-programmed gate arrays are:

• Faster Design and Verification FPGA can be designed and verified quickly while the sameprocess requires several weeks with gate arrays. There are no non-recurring engineering costs, notest vectors to generate, and no delay while waiting for prototypes to be manufactured.

• Design Changes without Penalty Because the devices are software-configured and user-programmed, modifications are much less risky and can be made anytime - in a manner ofminutes or hours, as opposed to the weeks it would take with a gate array. This results insignificant cost savings in design and production.

• Shortest Time-to-Market many component products are available in common packages withcommon footprints, designs often can be migrated to higher or lower density devices, or evenacross some product families, without any printed circuit board changes. Design ideas,represented in text or schematic format, are converted into a configuration data file for an FPGAor CPLD device using step development software running on a PC or workstation.

The below are the pictures of some commercial FPGAs available in the market:

The above architecture represents the Island style architecture. The Xilinx Company produces thesetypes of devices. Each Configurable logic block contains four look up tables. The interconnectsbetween the blocks are programmable. The input/output blocks can be used for both input and output.The wire length cost is a linear function of the distance between the blocks.

The below is the picture of the Hierarchical Style architecture FPGA:

The Altera Company produces these kinds of FPGAs. Each LAB consists of minimum 100 Look uptables and a maximum of 160 look up tables. These labs are connected to each other with the help ofGlobal Interconnects. The placement cost is not proportional to the distance between the two blocks.The cost is calculated with different techniques , which are discussed later in this document.

All the above information provided a brief introduction to FPGAs. Now we will see the objective ofthe project :

Objective: To generate a legal placement for hierarchical interconnect based FPGAs such that

1. Design performance is maximized : Design performance means the maximum pin to pin delay in the FPGA is minimized and also total area of the circuit is reduced 2. Routing congestion is minimized: This takes of even distribution of routing wires all over the circuit.

The below is the diagram which shows the flow in the Quartus software for placement androuting developed by Altera Company:

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At the initial stage an Hardware Description Language (Verilog or VHDL) is fed to the quartussoftware. The quartus software then does the synthesis (redundant logic is removed). After synthesisplacement is done using the mincut based recursive partitioning. After the placement routing is doneand finally the programming bit generation is done which is fed to the FPGA.

We basically modify the placement procedure used by the Quartus software. Instead of the min cutbased recursive partitioning, we use Bottom up clustering.

Min cut based recursive partitioning is described below:

It generates design partitions such that

1. Cut size between partitions are minimized: Each edge between the clusters is assigned a weight based on the criticality of the edge. If the edge has more weight then it is said to be more critical.So while making cuts, the tool makes sure that edges which have more weight will not be cut.

2. Cluster size constraints are satisfied: Each LAB can hold a maximum of 160 Look up tables. Sowhile making clusters, the tool makes sure that the cluster size is not violated.

3. Timing driven partitioning minimizes the crossing of critical nets: As mentioned earlier, in orderto meet the timing constraints, the critical nets are not cut.

Now we will see the problems associated with the above procedure:

1. Minimizing cut size does not directly minimize design delay. This can be explained as follows:

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Suppose consider the above two cases, where the tool needs to make a choice. In case (1), the weightof a single edge is 10. So, the edge is considered to be very critical. In case (2), the sum of the weightsof all the edges is 11. As the sum of weights of the edges in second case is more, the tool doesn’t cutthose clusters. It cuts the clusters in the first case. But, we know that the criticality of the edge is more.So, we are losing the timing information here. So, the min cut based partitioning is doing bad here.

2.Routing Congestion: The main idea in min cut based partitioning is that it tries to reduce as much aspossible the number of wires crossing between two partitions. But this actually worsens the routing. Itincreases the routing congestion a lot. This can be shown below:

Case (1)

Case (2)

During the initial stages of partition (case 1), we can see that the number of edges crossing betweenthe clusters is less. So, the routing congestion is very less in those areas. But, once the cluster sizebecomes smaller (case 2), the number of edges crossing between the clusters is very high. As a resultof that the routing congestion is very high in those areas. As a result of the uneven distribution of theedges, the routing is high at some areas and low at some areas. This can be overcome by evenlydistributing the wires.

Motivation:

1. Bottom-up clustering groups closely connected components. As a result of this routing congestionis improved

2.Placement with wire length based cost function. As a result of this design delay is reduced.

The proposed flow:

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Initially HDL design is taken, its synthesized and then it’s clustered. After clustering, simulatedannealing placement is done. After that routing is done and finally programming bits generated.

Framework: VPR (Versatile Place and Route): VPR is a placement and routing tool for array-based FPGAs, and T-VPack is a logic block packing (clustering) program. VPR was written to allow circuits to be placed androuted on a wide variety of FPGAs to facilitate comparisons of different architectures. It takes two inputfiles, a net list describing the circuit to be placed and routed, and a description of the FPGA architecture.Optionally, one can also input a placement file to VPR if one desires that an existing placement be routedonly.

VPR targets island style devices. So, we need to take care of appropriate things such that we can use thatfor Hierarchical devices. The main parameters to be changed are:

1. Each LAB in Hierarchical device contains a maximum of 160LUTs where as island style containsonly 4LUTs. So, while we are clustering, we need to see that the cluster can hold as much aspossible for Hierarchical device

2. The cost function needs to be changed. The cost calculation method in Island style follows thebounded box approximation method. The cost is linearly proportional to the distance between thetwo blocks.

Formula for calculating the cost in Island style is :Cost = Σn=1 to nets q(n) [ (bbx(n)/Cavg) + (bby(n)/Cavg) ]

bbx, bby are horizontal and vertical distances respectively.

Cavg is the average channel capacity.

q(n) is the error factor.

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Cost Calculation for Hierarchical Devices:

Its consists of two types of routing:

1. Intra Cluster Routing ( the cost is zero for this)

2. Inter Cluster Routing : These are of different types-

The chip can be divided in to four quadrants and the cost is calculated based on the location of thetwo nets.

Quadrant: If the two nets are with in the quadrant, then a single wire is used.

Half of the chip: If the two nets are in with in the half of the chip, then a double wire is used.

Same Row: If the two nets are in same row but in different quadrants, then a double is used

Same Column: If the two nets are in same column but in different quadrants, then a double is used

Neither: If the nets lies in cross quadrants, then two double wires are needed.

All the above cases are considered while calculating the cost.

Results:All the above cases are considered and these are implemented in the VPR source code , to obtain theco-ordinates of the cluster.

The below are the tables which shows that we outperform the Alteras Quartus tool in every aspect.

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In the above table, the first column represents the test benches we considered to compare the results.The second column, shows the number of look up tables used by the quartus. Third and fourth columnshows the results we obtained by the bottom up clustering method. We can clearly see that, weoutperform the quartus tool in every test case with a huge difference. This shows that area wise we aresaving a lot.

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The above table shows the maximum pin to pin delay in the circuit. The second column represents thequartus output. The third and fourth column represents results with our technique. We can see that, weout perform the quartus in design maximum dealy also.

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Here also we can see that we outperform Quartus in the time it takes for synthesis and fitting.

We can conclude that the bottom up clustering groups closely connected components together and thismakes the placement of the connected components nearby and as a result routing becomes easy. Theresults also show that placing the closely related nets together will reduce the design delay and thearea.

First take a hdl code and give directly to quartus and see the number of lookup tables and thetiming information.

Second, take an hdl code and convert it in to blif format, and then cluster them and then dosimulated annealing placement and then convert back the clustered blif in to hdl code and thenfeed into quartus

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Acknowledgements: Thanks to Srini Krishnamoorthy for project related discussions

References:

1. “Performance-Driven Multi-Level Clustering with application to Hierarchical FPGA Mapping”,Jason Cong

2. “Placement Algorithms for Datapath-Oriented FPGAs”, Poplavko

3. “Timing-Driven Placement for Hierarchical Programmable-Logic Devices”, Michael Hutton

4. “FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs”, Jason Cong