Defect ToleranceDefect Tolerancefor for Yield EnhancementYield Enhancementof of FPGA InterconnectFPGA InterconnectUsing Fine-grain and Using Fine-grain and

Coarse-grain RedundancyCoarse-grain RedundancyAnthony J. YuAnthony J. Yu

August 15, 2005August 15, 2005

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OutlineOutline

Introduction and motivationIntroduction and motivation Previous worksPrevious works New architecturesNew architectures

Coarse-grain redundancy (CGR)Coarse-grain redundancy (CGR) Fine-grain redundancy (FGR)Fine-grain redundancy (FGR)

ComparisonsComparisons ConclusionsConclusions

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Introduction and Introduction and MotivationMotivation

Scaling introduces Scaling introduces new types of defectsnew types of defects

Number of defects Number of defects expected to increase expected to increase as chip density as chip density increasesincreases As a result, chip yield is As a result, chip yield is

on the declineon the decline FPGAs are mostly FPGAs are mostly

interconnectinterconnect

To improve yield (and To improve yield (and revenue), we must revenue), we must tolerate multiple tolerate multiple interconnect defectsinterconnect defects

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General Defect Tolerant General Defect Tolerant TechniquesTechniques

Defect-tolerant techniques minimize Defect-tolerant techniques minimize impact (cost) of manufacturing defectsimpact (cost) of manufacturing defects

FPGA defect-tolerance can be loosely FPGA defect-tolerance can be loosely categorized into three classes:categorized into three classes: Software Redundancy – use CAD tools to map Software Redundancy – use CAD tools to map

around the defectsaround the defects Hardware Redundancy – incorporate spare Hardware Redundancy – incorporate spare

resources to assist in defect correction (eg. resources to assist in defect correction (eg. Spare row/column)Spare row/column)

Run-time Redundancy – protection against Run-time Redundancy – protection against transient faults such as SEUs (eg. TMR)transient faults such as SEUs (eg. TMR)

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Previous work – 1 – XilinxPrevious work – 1 – Xilinx Xilinx’s Defect-Tolerant ApproachXilinx’s Defect-Tolerant Approach

Customer (knowingly) purchases “less that perfect” Customer (knowingly) purchases “less that perfect” partsparts

Customer gives Xilinx configuration bitstreamCustomer gives Xilinx configuration bitstream Xilinx tests FPGA devices against bitstreamXilinx tests FPGA devices against bitstream

Sells FPGA parts that “appear” perfectSells FPGA parts that “appear” perfect Defects avoid the bitstreamDefects avoid the bitstream

Limitation:Limitation: Chips work only with given bitstream – no changes!Chips work only with given bitstream – no changes!

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Previous work – 2 – Previous work – 2 – AlteraAltera

Altera’s Defect-Tolerant ApproachAltera’s Defect-Tolerant Approach Customer purchases “seemingly perfect” partsCustomer purchases “seemingly perfect” parts

Make defective resources inaccessible to Make defective resources inaccessible to useruser

Coarse-grain architectureCoarse-grain architecture Spare row and column in array (like memories)Spare row and column in array (like memories)

Defective row/column must be bypassedDefective row/column must be bypassed Use the spare row/column insteadUse the spare row/column instead

Limitation:Limitation: Does not scale well (multiple defects)Does not scale well (multiple defects)

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ObjectivesObjectives

ProblemProblem FPGA yield is on decline because of FPGA yield is on decline because of

aggressive technology scalingaggressive technology scaling Important objectives to improve yield:Important objectives to improve yield:

Tolerate interconnect defects (dominates Tolerate interconnect defects (dominates area)area)

Tolerate multiple defects (future trend)Tolerate multiple defects (future trend) Preserve timing (no timing re-verification)Preserve timing (no timing re-verification) Fast correction time (production use)Fast correction time (production use)

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ContributionsContributions New New fine-grainfine-grain redundancy architecture redundancy architecture Coarse-grain architecture with Coarse-grain architecture with multiplemultiple spare rows spare rows

and columnsand columns

Detailed evaluation of fine-grain and coarse-grain Detailed evaluation of fine-grain and coarse-grain redundancyredundancy Area, delay, yield estimatesArea, delay, yield estimates

Publications:Publications: Non-redundant architecture paperNon-redundant architecture paper,, at FPT’04 at FPT’04 Fine-grain architecture paper, Fine-grain architecture paper, to appear in FPL’05to appear in FPL’05 Yield comparison paper, Yield comparison paper, to appear in FPT’05to appear in FPT’05

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Non-redundant Non-redundant Interconnect SwitchInterconnect Switch

a) TraditionalConnection Point

b) Single-driverConnection Point

c) High-level Single-driverConnection Point

OLDOLD(bidirectional)(bidirectional)

MODERNMODERN(directional)(directional)

HIGH-LEVELHIGH-LEVELMODELMODEL

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Coarse-grain Redundancy Coarse-grain Redundancy (CGR)(CGR)

Row

Dec

oder

Fault Free

Spare Row

Wire Extensions

Faulty

Defect

Row

Dec

oder

BypassedRow

F. Hatori et al., “Introducing Redundancy in Field Programmable GateArrays,” presented at Custom Integrated Circuits Conference, 1993.

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So…what’s wrong with it?So…what’s wrong with it?

Spare Row and Column

0

0.2

0.4

0.6

0.8

1

1.2

1 10

Number of Defects

Yie

ld

32x32

64x64

128x128

256x256

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Improving yield for CGR –Improving yield for CGR –Adding Adding Multiple GlobalMultiple Global

SparesSpares Add multiple Add multiple

globalglobal spare to spare to traditional CGRtraditional CGR

Global spares can Global spares can be used to repair be used to repair any defective any defective row/column in the row/column in the arrayarray

Wire extensions Wire extensions are now longerare now longer

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Yield Impact of Multiple Yield Impact of Multiple Global SparesGlobal Spares

Global Spare Rows+Columns (32x32)

0

0.2

0.4

0.6

0.8

1

1.2

1 10Number of Defects

Yield

Baseline2 Global4 Global

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Increasing Area+Delay Increasing Area+Delay OverheadOverhead

1 GLOBAL SPARE

2 GLOBAL SPARES

4 GLOBAL SPARES MAY BE IMPRACTICAL

!!!

NO SPARES

MORE SPARES MORE MUX OVERHEAD IN EVERY SWITCH

ELEMENT

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Fine-grain Redundancy Fine-grain Redundancy (FGR) – (FGR) –

Avoidance by ShiftingAvoidance by Shifting

DefectSpare

a) Original b) Corrected

+1

+1 -1-1

-1+1

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Implementation Implementation OverviewOverview

-1 0-2

+1 0+2

-10

-2

+10

+2

-1 0-2

+1 0+2

-10

-2

+10

+2

omux

imux

a) Original b) Defect-tolerant

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FGR Switch Element FGR Switch Element DetailsDetails

Upstream Switch BlockUpstream Switch BlockDownstream Switch BlockDownstream Switch Block

DefectDefect

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FGR Implementation FGR Implementation ComparisonComparison

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FGR Architectural FGR Architectural SummarySummary

Several implementations of FGR evaluated:Several implementations of FGR evaluated: Implementation with Implementation with bestbest yield improvement (EM22) yield improvement (EM22)

Area +50%, delay + 20%Area +50%, delay + 20% Implementation with Implementation with lowestlowest yield improvement (EN11) yield improvement (EN11)

Area +35%, delay +25%Area +35%, delay +25%

Perfect chips can be sold as interconnect-Perfect chips can be sold as interconnect-enhanced FPGAsenhanced FPGAs Allow router to use spare routing resources (muxes, Allow router to use spare routing resources (muxes,

tracks)tracks) Gives more routing flexibilityGives more routing flexibility TrueTrue area and delay overhead are 10-20% and 5-25% area and delay overhead are 10-20% and 5-25%

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Comparison between FGR Comparison between FGR and CGR – FGR Tolerates and CGR – FGR Tolerates

Tens of DefectsTens of DefectsFine-grain Redundancy(Best Yield Architecture)

0

0.2

0.4

0.6

0.8

1

1.2

1 10 100Number of Defects

Yield

CGR

32x32

64x64

128x128

256x256

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Estimated Area overhead at Estimated Area overhead at equal yield (80%)equal yield (80%)

* CGR-G1 can only tolerate 1-2 defects

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Limitations of Study & Limitations of Study & ArchitecturesArchitectures

FGRFGR Does not tolerate defects in the logicDoes not tolerate defects in the logic Cannot tolerate clustered defectsCannot tolerate clustered defects Requires a detailed fault mapRequires a detailed fault map

CGRCGR Assumes that all defects can be Assumes that all defects can be

corrected with a single row/columncorrected with a single row/column Bypass circuitry is approximatedBypass circuitry is approximated

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ConclusionsConclusions CGR is effective for 1 or 2 defectsCGR is effective for 1 or 2 defects FGR meets desired objectives:FGR meets desired objectives:

Tolerates Tolerates multiplemultiple randomly distributed randomly distributed defectsdefects

Defect correction Defect correction does not perturb timingdoes not perturb timing Tolerates an Tolerates an increasing numberincreasing number of defects of defects

as array size increasesas array size increases Correction can be applied Correction can be applied quicklyquickly

FGR potentially capable of FGR potentially capable of correcting correcting crosstalkcrosstalk faults, but is not explored in faults, but is not explored in thesisthesis

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ContributionsContributions New New fine-grainfine-grain redundancy architecture redundancy architecture Coarse-grain architecture with Coarse-grain architecture with multiplemultiple spare rows spare rows

and columnsand columns

Detailed evaluation of fine-grain and coarse-grain Detailed evaluation of fine-grain and coarse-grain redundancyredundancy Detailed circuit-level design Detailed circuit-level design improved area, delay improved area, delay

estimatesestimates Yield comparisonYield comparison

Publications:Publications: Non-redundant architecture paperNon-redundant architecture paper,, at FPT’04 at FPT’04 Fine-grain architecture paper, Fine-grain architecture paper, to appear in FPL’05to appear in FPL’05 Yield comparison paper, Yield comparison paper, to appear in FPT’05to appear in FPT’05

Thank you!Thank you!

anthonyy@ece.ubc.caanthonyy@ece.ubc.ca

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Improving yield for CGR –Improving yield for CGR –Adding Adding Multiple LocalMultiple Local

SparesSpares Divide FPGA into Divide FPGA into

subdivisionssubdivisions

Each subdivision has Each subdivision has locallocal spare(s)spare(s)

DistributesDistributes spares across spares across chipchip Reduces mux area overheadReduces mux area overhead

(of Global scheme)(of Global scheme)

Limitation:Limitation: Spare(s) can only repair defect Spare(s) can only repair defect

withinwithin the subdivision the subdivision

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Yield Impact of Multiple Local Yield Impact of Multiple Local SparesSpares

(not as good as Global with same # (not as good as Global with same # spares)spares)

Local Spare Rows+Columns (32x32)

0

0.2

0.4

0.6

0.8

1

1.2

1 10Number of Defects

Yield

Baseline2 Global4 Global2 Sub, 1 Spare4 Sub, 1 Spare

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SummarySummary As the density of FPGAs increase, they become As the density of FPGAs increase, they become

increasingly susceptible to manufacturing defectsincreasingly susceptible to manufacturing defects Defect-tolerant techniques alleviate this growing Defect-tolerant techniques alleviate this growing

problemproblem Depending on the desired level of protection, we can Depending on the desired level of protection, we can

apply different techniquesapply different techniques

At low defect rates, the coarse-grain spare row and At low defect rates, the coarse-grain spare row and column approach has lower overhead than the fine-column approach has lower overhead than the fine-grain approachgrain approach

At the same area overhead, the fine-grain approach At the same area overhead, the fine-grain approach can tolerate more defects than the spare row and can tolerate more defects than the spare row and column approachcolumn approach