-
8/12/2019 Pipelined Processor Documentation
1/10
=============================================================
CMPE 140Fall 2013
Final Project
Enhanced and Pipelined MIPS Processor
Submitted by: Thanh Huynh 007610265
Christopher Harris 006088043
Date Performed: 12-8-2013
Checked by: Thanh Huynh
Christopher Harris
San Jose State UniversityDepartment of Computer Engineering
-
8/12/2019 Pipelined Processor Documentation
2/10
1
CMPE 140 Final Project
Thanh Huynh, Christopher HarrisComputer Engineering Department,
College of Engineering
San Jose State University, San Jose, CA 95192
E-mail:[email protected]@gmail.com
AbstractThe objective of this project is to utilized the skills
obtained in previous lab assignment to
create and enhanced and pipelined MIPS processor.
Introduction
With the knowledge and skills we obtained in classroom and
previous lab assignments,and based on the initial design of the
single-cycle MIPS processor, we are now ready to extend theinitial
design to a more capable version of the MIPS processor.
Specifically, we will create andenhanced single-cycle MIPS
processors functionality and then pipeline that single-cycle
design.
Design Description
Task 1
Create an enhanced single-cycle MIPS processors functionality by
extending itsinstruction support from the initial sub set (ADD,
SUB, AND, OR, SLT, LW, SW, BEQ, J,ADDI) to cover the following
additional instructions: MULTU, MFHI, MFLO, JR, and JAL.
FigureInitial Single Cycle Processor
mailto:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]
-
8/12/2019 Pipelined Processor Documentation
3/10
2
Table1 - Control Unit for Main Decoder (Single Cycle Design)
Table1Control Unit for R Type Functions
FigureEnhanced Single Cycle Processor
-
8/12/2019 Pipelined Processor Documentation
4/10
3
Task 2
Pipeline the enhanced single-cycle MIPS processor based on the
reference design shown below.
FigureInitial Pipelined Design
FigureRevised Pipeline Design
-
8/12/2019 Pipelined Processor Documentation
5/10
4
FigureRevised Pipeline Design (larger)
-
8/12/2019 Pipelined Processor Documentation
6/10
5
For each task of our design, it will be tested via both Verilog
simulation and FPGAvalidation. Two sample test programs (from
previous lab assignments) are attached below.
Test Program 1: C++ Pseudo Code.
a = 0x51;b = 0x13;Save a to memory address 0x20;Save b to memory
address 0x24;x = a - b;a = a + b; // a = 0x64if(a < 0x25){
Read the word at address 0x20 into $a0; //so a=0x51a = a +
0x89;
}else{
Read the word at address 0x20 into $a0; //so a=0x51a = a -
0x10;
}Store the value of a to memory address 0x30;
Test Program 1: Machine Code:
#$a0 = a $a1 = b $s0 = x# Variables initialization
li $a0, 0x51 #a = 0x51li $a1, 0x13 #b = 0x13sw $a0, 0x20($0)
#save a to memory address 0x20sw $a1, 0x24($0) #save b to memory
address 0x24
# Arithmetic computationssub $s0, $a0, $a1 # x = a - badd $a0,
$a0, $a1 # a = a + b;
#IF structureaddi $t1, $0, 0x25 # temp1 = 0 + 0x25slt $t2, $a0,
$t1 # set temp2 = 1 if a < 2500lw $a0, 0x20($0)
beq $t2, $0, else # if temp2 = 0, go to elseaddi $a0, $a0, 137 #
a = a + 0x89j endif
#else structureelse:addi $a0, $a0, -16 # a = a + 0x9
#endif structureendif:
-
8/12/2019 Pipelined Processor Documentation
7/10
6
sw $a0, 0x30($0)
FigureGenerated Machine Code from Test Program 1.
FigureRegister / Memory Content from Test Program 1 after
execution.
Test Program 2: Assembly Code for extended design
.data
.globl main
.text
-
8/12/2019 Pipelined Processor Documentation
8/10
7
main:# addi $sp, $0, 48 not for SPIMaddi $a0, $0, 12 # set
argjal factorial # compute the factorialadd $s0, $v0, $0 # move
result into $s0j end
factorial:addi $sp, $sp, -8 # make room on stacksw $a0, 4($sp) #
store $a0sw $ra, 0($sp) # store $raaddi $t0, $0, 2 # $t0 = 2slt
$t0, $a0, $t0 # a
-
8/12/2019 Pipelined Processor Documentation
9/10
8
FigureRegister / Memory content from test program 2 after
execution.
Verification And Test
FigureISIM (single cycle using test program 1)
The figure above shows simulation of our single cycle. This
simulation yields correctresults. When executing on MIPS, the last
instruction (ac40030) stores value 41 of register ainto memory
address 0x30. As shown from ISIM figure above, wave length
din[31:0] andaddr[31:0] of DMEM shows value 30 and 41.
-
8/12/2019 Pipelined Processor Documentation
10/10
9
Table : settings for FPGA board.
Conclusion andDiscussion
References
1. Handouts from SJSU Canvas.
