Pipeline Data Hazards

Warning, warning, warning!

Read 4.8

Peer Instruction Lecture Materials for Computer Architecture by Dr. Leo Porter is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License.

Pipelining Key Points

• Pipeline processors aim at improving instruction throughput.

• Control signals are generated by combinational logic and passed with the instruction

• ET=IC*CPI*CT

Dealing With Data Hazards

• In Software

–

• In Hardware

–

–

Data Hazards are caused by instruction dependences. For example, the add is data-dependent on the subtract:

subi $5, $4, #45add $8, $5, $2

Data Hazards are caused by instruction dependences. For example, the add is data-dependent on the subtract:

subi $5, $4, #45add $8, $5, $2

nops/independent insts

Pipeline stalls

Forwarding

Pipeline Stalls

• To insure proper pipeline execution in light of register dependences, we must:– detect the hazard

– stall the pipeline

Detecting the Hazard

IM Reg

AL

U DM Reg

IM Reg

AL

U DM

IM Reg

AL

U DM Reg

IM Reg A

LU DM Reg

IM Reg

AL

U DM Reg

CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8

• 6 types of data hazards– two reg reads * 3 reg writes

Draw arrows from 3 previous instructions

Jump ahead two slides

To show the comparison logic

Once you detect the hazard in ID – what must you do to insert the nop and “stall”?

1. Flush all instructions in the pipeline (set control signals to 0).2. Set all control signals going to ID/EX register to zero.3. Set PCWrite to zero.

4. Set IF/ID register write to zero.

Stalling the pipeline

Selection Changes

A 1, 3, 4

B 1, 2, 3

C 2, 3, 4

D 1

E None of the above

The PipelineShow comparison logic, go back 1 slide, then show how to stall

What else can we do other than just stalling?

Registers

ID/EX

AL

U

EX/MEM MEM/WB

DataMemory

0

1

IM Reg

AL

U DM Reg

IM Reg

AL

U DM Reg

add $2, $3, $4

add $5, $3, $2

Show how the value is already available

Reducing Data Hazards Through Forwarding

EX Hazard:if (EX/MEM.RegWriteand (EX/MEM.RegisterRd != 0)and (EX/MEM.RegisterRd = ID/EX.RegisterRs)) ForwardA = 10

if (EX/MEM.RegWriteand (EX/MEM.RegisterRd != 0)and (EX/MEM.RegisterRd = ID/EX.RegisterRt)) ForwardB = 10

(similar for the MEM stage)

Point out source registers being pass along

Show how the logic applies.

Data Forwarding

• The Previous Data Path handles two types of data hazards– EX hazard

– MEM hazard

• We assume the register file handles the third (WB hazard)– “Register File forwarding”

– If the register file is asked to read and write the same register in the same cycle, we assume that the reg file allows the write data to be forwarded to the output

– We’re still going to call that forwarding.Point out that although the book talks about writing on the neg edge and always reading, this isn’t accurate for today. Today – forwarding in the regfile is explicit.

Eliminating Data Hazards via Forwarding

IM Reg

AL

U DM Reg

IM Reg

AL

U DM

IM Reg

AL

U DM Reg

IM Reg A

LU DM Reg

IM Reg

AL

U DM Reg

CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8

sub $2, $1, $3

and $6, $2, $5

or $13, $6, $2

add $14, $2, $2

sw $15, 100($2)

Draw the arrows for the add, or, and add instructions.

Forwarding in Actionadd $1, $12, $3 sub $12, $3, $4 add $3, $10, $11 Memory Access Write Back

Forwarding in ActionInstruction Fetch add $1, $12, $3 sub $12, $3, $4 add $3, $10, $11 Write Back

Eliminating Data Hazards via Forwarding??

CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8

lw $2, 10($1)

and $12, $2, $5

or $13, $6, $2

add $14, $2, $2

sw $15, 100($2)

Do this on our own

How many stalls occur and how many values require hardware forwarding support to avoid stalling for our MIPS 5-stage pipeline.

add $3, $2, $1

lw $4, 100($3)

and $6, $4, $3

sub $7, $6, $2

add $9, $3, $6

Selection Stalls Forwarded values

A 1 3

B 2 4

C 2 3

D 1 5

E None of the above

Datapath CombinedPoint out this logic now just checks to see if the next instruction reads from mem

Seque – we know MIPS – but can we apply these principles to other pipelines

Suppose EX is the longest (in time) pipeline stage. To reduce CT, we split it in half. Given the following pipeline:IF ID EX1 EX2 M WB

Assume the input data must be available at the start of EX1 and the output is available after EX2.How many hardware stalls would be required in the following code (assuming hardware forwarding wherever possible)?

lw r1, 0(r3)add r2, r1, r3

Selection Number of stalls

A 0

B 1

C 2

D 3

E 4

Suppose EX is the longest (in time) pipeline stage. To reduce CT, we split it in half. Given the following pipeline: IF ID EX1 EX2 M WB

Assume the input data must be available at the start of EX1 and the output is available after EX2. How How many hardware stalls would be required in the following code (assuming hardware forwarding wherever possible)?

add r1, r2, r3add r4, r1, r3

Selection Number of stalls

A 0

B 1

C 2

D 3

E 4

Suppose IF and M are the longest stages. To reduce CT, we split each in half. Given the following pipeline:IF1 IF2 ID EX M1 M2 WB

Assume the input data must be available at the start of F1/M11 and the output is available after F2/M2. How many hardware stalls would be required in the following code (assuming hardware forwarding wherever possible)?

lw r1, r2, r3sw r1, 0 (r3)

Selection Number of stalls

A 0

B 1

C 2

D 3

E 4

As an ISA designer - you have a choice between dealing with these hazards in software or hardware. Which might you choose and why?

Selection HW or SW Why? (Best answer)

A Software Compilers have a large window of instructions available to do reordering to eliminate hazards

B Software Detecting data hazards in hardware can be difficult and expensive

C Hardware Hardware knows at runtime the actual dependencies and can exploit that knowledge for better reordering

D Hardware Exposing the number of required stalls violates the abstraction between hardware and software

E Software For different reasons than above

Dealing with Data Hazards

All these are reasonable – but reason D is the driving factor for hardware dealing with hazards (be sure to highlight no single right answer). Highlight a full discussion of this is in graduate architecture, but we’ll touch on it some later

Data Hazard Key Points

• Pipelining provides high throughput, but does not handle data dependences easily.

• Data dependences cause data hazards.

• Data hazards can be solved by:– software (nops)

– hardware stalling

– hardware forwarding

• Our processor, and indeed all modern processors, use a combination of forwarding and stalling.

• ET = IC * CPI * CT