PICMG 3.1 R3.0® 3.1 Revision 3.0 Specification Ethernet/Fibre Channel for AdvancedTCA® Systems Revision 3.0 - May 5, 2016Com Express · CompactPCI · Open Standards · Adlink Technology

PICMG® 3.1 Revision 3.0 Specification

Ethernet/Fibre Channel for AdvancedTCA® SystemsRevision 3.0 - May 5, 2016

© Copyright 2016, PCI Industrial Computer Manufacturers Group. The attention of adopters is directed to the possibility that compliance with or adoption of PICMG® specifications may require use of an invention covered by patent rights. PICMG® shall not be responsible for identifying patents for which a license may be required by any PICMG® specification or for conducting legal inquiries into the legal validity or scope of those patents that are brought to its attention. PICMG® specifications are prospective and advisory only. Prospective users are responsible for protecting themselves against liability for infringement of patents.

NOTICE:

The information contained in this document is subject to change without notice. The material in this document details a PICMG® specification in accordance with the license and notices set forth on this page. This document does not represent a commitment to implement any portion of this specification in any company's products.

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In no event shall PICMG® be liable for errors contained herein or for indirect, incidental, special, consequential, reliance or cover damages, including loss of profits, revenue, data or use, incurred by any user or any third party. Compliance with this specification does not absolve manufacturers of equipment from the requirements of safety and regulatory agencies (UL, CSA, FCC, IEC, etc.).

IMPORTANT NOTICE:

This document includes references to specifications, standards or other material not created by PICMG. Such referenced materials will typically have been created by organizations that operate under IPR policies with terms that vary widely, and under process controls with varying degrees of strictness and efficacy. PICMG has not made any enquiry into the nature or effectiveness of any such policies, processes or controls, and therefore ANY USE OF REFERENCED MATERIALS IS ENTIRELY AT THE RISK OF THE USER. Users should therefore make such investigations regarding referenced materials, and the organizations that have created them, as they deem appropriate.

PICMG®, CompactPCI®, AdvancedTCA®, AdvancedTCA® 300,ATCA®, ATCA® 300, AdvancedMC®, CompactPCI® Express, COM Express®, MicroTCA®, SHB Express®, and the PICMG, CompactPCI, AdvancedTCA, µTCA and ATCA logos are registered trademarks, and xTCA™, IRTM™ and the IRTM logo are trademarks of the PCI Industrial Computer Manufacturers Group. All other brand or product names may be trademarks or registered trademarks of their respective holders.

ii PICMG 3.1 R3.0, May 5, 2016

iContents

Contents

1 Introduction and objectives..........................................................................................................1

1.1 Objectives ............................................................................................................................11.2 Reference documents...........................................................................................................2

1.2.1 Reference specifications..........................................................................................21.2.2 Environment and regulatory documents .................................................................3

1.3 Special word usage .............................................................................................................31.4 Statement of compliance ......................................................................................................31.5 Name and logo usage...........................................................................................................41.6 Signal naming conventions ..................................................................................................51.7 Intellectual property ..............................................................................................................5

1.7.1 Necessary claims.....................................................................................................61.7.2 Unnecessary claims.................................................................................................61.7.3 Third party disclosures.............................................................................................6

1.8 Acronyms and definitions......................................................................................................6

2 PICMG 3.0 compliance ..................................................................................................................9

2.1 Mechanical............................................................................................................................92.2 Power distribution .................................................................................................................92.3 Thermal.................................................................................................................................9

3 Hardware platform management................................................................................................11

3.1 Introduction .........................................................................................................................113.2 PICMG 3.1 implementation requirements...........................................................................11

3.2.1 Implementation independent requirements ..........................................................113.3 Messaging algorithm ..........................................................................................................113.4 E-Keying extensions ..........................................................................................................12

3.4.1 Link Descriptor ......................................................................................................123.4.2 LDES: Link Designator .........................................................................................133.4.3 LTYPE: Link Type .................................................................................................133.4.4 LCLASS: Link Class .............................................................................................133.4.5 LEXT: Link Type Extension ..................................................................................133.4.6 LGID: Link Grouping ID ........................................................................................14

3.5 Link and Link Descriptor options.........................................................................................153.6 Channel E-keying extensions .............................................................................................47

3.6.1 Backplane Channel capabilities .............................................................................473.6.2 Board Channel capabilities ....................................................................................503.6.3 E-Keying process...................................................................................................533.6.4 Updated Set and Get Port State Commands.........................................................54

4 Data transport .............................................................................................................................57

4.1 Introduction ........................................................................................................................574.2 Pin assignments ................................................................................................................59

5 Backplane physical layer interfaces..........................................................................................63

5.1 Gigabit Backplane interface, 1000BASE-BX/FC-PI............................................................645.1.1 1000BASE-BX/FC-PI transmitter electrical specifications .....................................65

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5.1.1.1 Transmitted electrical specifications at TP1...........................................655.1.1.2 Transmitted electrical specifications at TPT ..........................................655.1.1.3 Transmitted eye mask at TPT................................................................66

5.1.2 1000BASE-BX/FC-PI receiver electrical specifications .........................................685.1.2.1 Receiver electrical specifications at TPR...............................................685.1.2.2 Received eye mask at TPR ...................................................................695.1.2.3 Receiver electrical specifications at TP4 ...............................................71

5.1.3 1000BASE-BX/FC-PI jitter specifications ..............................................................715.2 10 Gigabit Backplane interface, 10GBASE-BX4 ................................................................72

5.2.1 10GBASE-BX4 transmitter electrical specifications...............................................735.2.1.1 Transmitted electrical specifications at TP1...........................................735.2.1.2 Transmitted electrical specifications at TPT ..........................................745.2.1.3 Compliance interconnect definition ........................................................74

5.2.2 10GBASE-BX4 receiver electrical specifications..................................................755.2.2.1 Receiver electrical specifications at TPR...............................................765.2.2.2 Receiver electrical specifications at TP4 ...............................................76

5.2.3 10GBASE-BX4 TPT and TPR eye mask ...............................................................765.3 1000BASE-KX and 10GBASE-KX4 specifications .............................................................775.4 10GBASE-KR and 40GBASE-KR4 Channel characteristics ..............................................77

5.4.1 Definitions of measurements and calculations (informative) .................................795.4.1.1 Fitted attenuation ...................................................................................795.4.1.2 Insertion loss deviation (ILD) .................................................................795.4.1.3 Power sum differential near-end crosstalk (PSNEXT) ...........................805.4.1.4 Power sum differential far-end crosstalk (PSFEXT) ..............................805.4.1.5 Power sum differential crosstalk (PEXT) ...............................................805.4.1.6 Insertion loss to crosstalk ratio (ICR) and fitted ICR..............................81

5.4.2 Backplane test assembly characteristics ...............................................................815.4.2.1 Backplane test assembly common requirements ..................................835.4.2.2 Short Backplane test assembly requirements........................................845.4.2.3 Long Backplane test assembly requirements ........................................88

5.4.3 Front Board test card requirements .......................................................................915.4.3.1 Fitted attenuation ...................................................................................94

5.4.4 Backplane test paddle card requirements .............................................................995.4.4.1 Fitted attenuation .................................................................................1025.4.4.2 Insertion loss deviation ........................................................................1045.4.4.3 Return loss...........................................................................................1055.4.4.4 Common mode return loss...................................................................1055.4.4.5 Common mode conversion loss...........................................................1065.4.4.6 Insertion loss to crosstalk ratio.............................................................107

5.4.5 Front Board Channel requirements .....................................................................1085.4.5.1 Fitted attenuation .................................................................................1095.4.5.2 S-Parameter and jitter testing and requirements .................................1105.4.5.3 Return loss...........................................................................................1115.4.5.4 Common mode return loss...................................................................1125.4.5.5 Crosstalk and error rate testing and requirements...............................114

5.4.6 Backplane Channel requirements........................................................................1165.4.6.1 Fitted attenuation .................................................................................1175.4.6.2 Insertion loss deviation ........................................................................1185.4.6.3 Insertion loss to crosstalk ratio.............................................................119

5.4.7 Channel fitted attenuation (informative)...............................................................1205.5 Auto-Negotiation (informative) ..........................................................................................122

5.5.1 1000BASE-BX to 10GBASE-BX4 Auto-Negotiation ............................................122

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Contents

5.5.2 1000BASE-KX/10GBASE-KX4/10GBASE-KR/40GBASE-KR4 Auto-Negotiation ..................................................................................................................................122

5.6 100GBASE-KR4 Channel characteristics.........................................................................1225.6.1 Definitions of measurements and calculations (informative)................................123

5.6.1.1 Channel Operating Margin...................................................................1245.6.2 100GBASE-KR4 Backplane test assembly characteristics..................................124

5.6.2.1 100GBASE-KR4 Backplane test assembly common requirements.....1255.6.2.2 Short 100GBASE-KR4 Backplane test assembly requirements ..........1265.6.2.3 Long 100GBASE-KR4 Backplane test assembly requirements...........130

5.6.3 100GBASE-KR4 Front Board test card requirements..........................................1345.6.3.1 Fitted attenuation .................................................................................1365.6.3.2 Insertion loss deviation ........................................................................1375.6.3.3 Return loss at TP A..............................................................................1385.6.3.4 Return loss at TP 2/TP 3......................................................................1395.6.3.5 Common mode return loss at TP A......................................................1405.6.3.6 Common mode return loss at TP 2/TP 3 .............................................1415.6.3.7 Common mode conversion loss TP 2/TP 3 to TP A ............................1425.6.3.8 Common mode conversion loss TP A to TP 2/TP 3 ............................1435.6.3.9 Insertion loss to crosstalk ratio.............................................................144

5.6.4 100GBASE-KR4 Backplane test paddle card requirements ................................1465.6.4.1 Fitted attenuation .................................................................................1495.6.4.2 Insertion loss deviation ........................................................................1505.6.4.3 Return loss at TP B..............................................................................1515.6.4.4 Return loss at TP 1/TP 4......................................................................1525.6.4.5 Common mode return loss at TP B......................................................1535.6.4.6 Common mode return loss at TP 1/TP 4 .............................................1545.6.4.7 Common mode conversion loss at TP 1/TP 4 to TP B ........................1555.6.4.8 Common mode conversion loss TP B to TP 1/TP4 .............................1565.6.4.9 Insertion loss to crosstalk ratio.............................................................157

5.6.5 Front Board Channel requirements .....................................................................1595.6.5.1 Fitted attenuation ................................................................................1605.6.5.2 S-Parameter and jitter testing and requirements .................................1615.6.5.3 Return loss...........................................................................................1625.6.5.4 Common mode return loss...................................................................1635.6.5.5 Crosstalk and error rate testing and requirements...............................1645.6.5.6 Front Board Channel Operating Margin...............................................166

5.6.6 Backplane Channel requirements........................................................................1675.6.6.1 Backplane Channel Operating Margin .................................................168

A Advanced Differential Fabric connector generation 2 Definition - ADFplus (normative) ...171

A.1 General data .....................................................................................................................171A.1.1 Objective of this Appendix ...................................................................................171A.1.2 Scope...................................................................................................................171A.1.3 Intended method of mounting ..............................................................................172A.1.4 Ratings and characteristics..................................................................................172A.1.5 Normative references ..........................................................................................172A.1.6 Markings ..............................................................................................................172

A.2 Technical information........................................................................................................172A.2.1 Definitions ............................................................................................................172

A.2.1.1 Contacts and terminations ...................................................................172A.2.1.2 Complete connectors (pairs) ................................................................172

A.3 Dimensional information ...................................................................................................173

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A.3.1 General isometric view and common features.....................................................173A.3.2 Engagement information......................................................................................173A.3.3 Backplane connectors .........................................................................................173A.3.4 Front Board connectors .......................................................................................174

A.3.4.1 Dimensions ..........................................................................................174A.3.4.2 Terminations ........................................................................................176

A.3.5 Mounting information for Backplane connectors..................................................176A.3.6 Mounting information for ADFplus Front Board connectors.................................177

A.4 Characteristics ..................................................................................................................177A.4.1 Climatic category .................................................................................................177A.4.2 Electrical characteristics ......................................................................................178

A.4.2.1 Impedance ...........................................................................................178A.4.2.2 Crosstalk ..............................................................................................179A.4.2.3 Insertion loss........................................................................................179A.4.2.4 Intra-pair skew (differential skew) ........................................................180

B Advanced Differential Fabric connector generation 3 Definition - ADF++ (normative) ......181

B.1 General data .....................................................................................................................181B.1.1 Objective of this Appendix ...................................................................................181B.1.2 Scope...................................................................................................................181B.1.3 Intended method of mounting ..............................................................................182B.1.4 Ratings and characteristics..................................................................................182B.1.5 Normative references ..........................................................................................182B.1.6 Markings ..............................................................................................................182

B.2 Technical information........................................................................................................183B.2.1 Definitions ............................................................................................................183

B.2.1.1 Contacts and terminations ...................................................................183B.2.1.2 Complete connectors (pairs)................................................................183

B.3 Dimensional information ...................................................................................................183B.3.1 General isometric view and common features.....................................................183B.3.2 Engagement information......................................................................................183

B.3.2.1 Electrical engagement length...............................................................183B.3.2.2 First contact point.................................................................................183B.3.2.3 Perpendicular to engagement direction ...............................................184B.3.2.4 Inclination.............................................................................................184

B.3.3 Backplane connectors .........................................................................................184B.3.3.1 Dimensions ..........................................................................................184B.3.3.2 Contacts...............................................................................................184B.3.3.3 Contact tip geometry............................................................................184B.3.3.4 Terminations ........................................................................................184

B.3.4 Front Board connectors .......................................................................................184B.3.4.1 Dimensions ..........................................................................................184B.3.4.2 Terminations ........................................................................................185

B.3.5 Mounting information for ADF++ Backplane connectors .....................................185B.3.6 Mounting information for ADF++ Front Board connectors ...................................185

B.4 Characteristics ..................................................................................................................185B.4.1 Climatic category .................................................................................................185B.4.2 Electrical characteristics ......................................................................................186

B.4.2.1 General Remarks.................................................................................186B.4.2.2 Impedance ...........................................................................................186B.4.2.3 Crosstalk ..............................................................................................187

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B.4.2.4 Insertion loss........................................................................................188B.4.2.5 Intra-pair skew (differential skew) ........................................................189B.4.2.6 Return loss...........................................................................................190

C Revision History .......................................................................................................................193

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Contents

viii May 5, 2016

Figures

Figures

1 Introduction and objectives .............................................................................................................1

2 PICMG 3.0 compliance......................................................................................................................9

3 Hardware platform management ...................................................................................................11

3-1 Backplane Point-to-Point Connectivity Record structure ........................................................483-2 Board Point-to-Point Connectivity Record structure ...............................................................50

4 Data transport .................................................................................................................................57

5 Backplane physical layer interfaces .............................................................................................63

5-1 SerDes 1000BASE-BX Ethernet/FC-PI Channel electrical environment ................................645-2 1000BASE-BX/FC-PI test points ............................................................................................655-3 1000BASE-BX/FC-PI transmit test point TPT.........................................................................665-4 1000BASE-BX/FC-PI absolute eye diagram mask at TPT .....................................................675-5 1000BASE-BX/FC-PI receive test point TPR .........................................................................685-6 1000BASE-BX/FC-PI received eye mask at TPR...................................................................705-7 10GBASE-BX4 electrical environment ..................................................................................735-8 10GBASE-BX4 compliant interconnect magnitude response and ISI loss .............................755-9 10GBASE-BX4 TPT and TPR eye mask ................................................................................775-10 Test point locations for LCLASS 0011b Channels..................................................................785-11 Examples of long and short Backplane test assemblies.........................................................825-12 Test point locations for validation of the Backplane test assembly.........................................835-13 Fitted attenuation limits for short Backplane test assembly....................................................855-14 Insertion loss deviation limits for short Backplane test assembly ...........................................865-15 Insertion loss to crosstalk ratio limits for short Backplane test assembly ...............................885-16 Fitted attenuation limits for long Backplane test assembly .....................................................895-17 Insertion loss deviation limits for long Backplane test assembly ............................................905-18 Insertion loss to crosstalk ratio for long Backplane test assembly..........................................915-19 Example Front Board test assembly .......................................................................................925-20 Test point locations for Front Board test card.........................................................................935-21 Fitted attenuation limits for the Front Board test card.............................................................945-22 Insertion loss deviation limits for Front Board test card ..........................................................955-23 Return loss limit for Front Board test card ..............................................................................965-24 Common mode return loss limit for the Front Board test card ................................................975-25 Common mode conversion loss limit for Front Board test card ..............................................985-26 Insertion loss to crosstalk ratio limits for the Front Board test card ........................................995-27 Example Backplane test paddle card ...................................................................................1005-28 Test Point locations for the Backplane test paddle card ......................................................1015-29 Possible loopback measurement configuration for the Backplane test paddle card.............1025-30 Fitted attenuation limits for the Backplane test paddle card .................................................1035-31 Insertion loss deviation limits for the Backplane test paddle card.........................................1045-32 Return loss limits for the Backplane test paddle card...........................................................1055-33 Common mode return loss limit for the Backplane test paddle card.....................................1065-34 Common mode conversion loss limit for the Backplane test paddle card.............................1075-35 Insertion loss to crosstalk ratio limits for the Backplane test paddle card.............................1085-36 Fitted attenuation limit for LCLASS 0011b signal paths in Front Board................................110

May 5, 2016 ix

Figures

5-37 Front Board Inserted into Front Board test card ...................................................................1115-38 Recommended test setup for Front Board S-parameter and jitter tests ...............................1115-39 Return loss limits for LCLASS 0011b signal paths in Front Board .......................................1125-40 Common mode return loss limits for LCLASS 0011b signal paths in a Front Board ............1135-41 Front Board transmit/receive setup with the short Backplane test assembly .......................1145-42 Recommended test setup for Front Board bit error rate testing ...........................................1155-43 Test point locations for Backplane testing ............................................................................1165-44 Backplane test setup with two Backplane test paddle cards ................................................1175-45 Fitted attenuation limits for LCLASS 0011b Backplane signal paths....................................1185-46 Insertion loss deviation limits for LCLASS 0011b Backplane signal paths ...........................1195-47 Insertion loss to crosstalk ratio limits for LCLASS 0011b Backplane signal paths ...............1205-48 Example Channel fitted attenuation loss at 5.15625 GHz ....................................................1215-49 Test point locations for LCLASS 0100b Channels................................................................1235-50 Examples of long and short 100GBASE-KR4 Backplane test assemblies ...........................1245-51 Test point locations for validation of the 100GBASE-KR4 Backplane test assembly ...........1255-52 Fitted attenuation limits for short 100GBASE-KR4 Backplane test assembly ......................1275-53 Insertion loss deviation limits for the short 100GBASE-KR4 Backplane test assembly .......1285-54 Insertion loss to crosstalk ratio limits for the short 100GBASE-KR4 Backplane test assembly..

1295-55 Fitted attenuation limits for the long 100GBASE-KR4 Backplane test assembly .................1315-56 Insertion loss deviation limits for the long Backplane test assembly ....................................1325-57 Insertion loss to crosstalk ratio for the long 100GBASE-KR4 Backplane test assembly ......1335-58 Example 100GBASE-KR4 Front Board test assembly .........................................................1345-59 Test point locations for the 100GBASE-KR4 Front Board test card .....................................1355-60 Fitted attenuation limits for the 100GBASE-KR4 Front Board test card ...............................1375-61 Insertion loss deviation limits for the 100GBASE-KR4 Front Board test card ......................1385-62 Return loss limit for the 100GBASE-KR4 Front Board test card at TP A..............................1395-63 Return loss limit for 100GBASE-KR4 Front Board test card at TP 2/TP 3 ...........................1405-64 Common mode return loss limit for 100GBASE-KR4 Front Board test card at TP A ...........1415-65 Common mode return loss limit for 100GBASE-KR4 Front Board test card at TP 2/TP 3 ...1425-66 Common mode conversion loss limit for the 100GBASE-KR4 Front Board test card (TP 2/TP 3

to TP A).................................................................................................................................1435-67 Common mode conversion loss limit for 100GBASE-KR4 Front Board test card (TP A to TP 2/

TP 3) .....................................................................................................................................1445-68 Insertion loss to crosstalk ratio limits for 100GBASE-KR4 Front Board test card.................1455-69 Example 100GBASE-KR4 Backplane test paddle card........................................................1465-70 Test Point locations for the 100GBASE-KR4 Backplane test paddle card ..........................1475-71 Possible loopback measurement configuration for 100GBASE-KR4 Backplane test paddle card

..............................................................................................................................................1485-72 Fitted attenuation limits for the 100GBASE-KR4 Backplane test paddle card......................1505-73 Insertion loss deviation limits for 100GBASE-KR4 Backplane test paddle card...................1515-74 Return loss limits for the 100GBASE-KR4 Backplane test paddle card at TP B ..................1525-75 Return loss limits for 100GBASE-KR4 Backplane test paddle card at TP 1/TP 4 ................1535-76 Common mode return loss limit for 100GBASE-KR4 Backplane test paddle card at TP B..1545-77 Common mode return loss limit for 100GBASE-KR4 Backplane test paddle card at TP 1/TP 4

..............................................................................................................................................1555-78 Common mode conversion loss limit for the 100GBASE-KR4 Backplane test paddle card from

TP 1/TP 4 to TP B.................................................................................................................1565-79 Common mode conversion loss limit for 100GBASE-KR4 Backplane test paddle card from TPB

to TP 1/TP 4..........................................................................................................................1575-80 Insertion loss to crosstalk ratio limits for the 100GBASE-KR4 Backplane test paddle card .158

x May 5, 2016

Figures

5-81 Fitted attenuation limit for LCLASS 0100b signal paths in Front Board................................1605-82 Front Board Inserted into the 100GBASE-KR4 Front Board test card..................................1615-83 Recommended test setup for Front Board S-parameter and jitter tests ...............................1625-84 Return loss limits for LCLASS 0100b signal paths in Front Board........................................1635-85 Common mode return loss limits for LCLASS 0100b signal paths in a Front Board ............1645-86 Front Board transmit/receive setup with short 100GBASE-KR4 Backplane test assembly ..1655-87 Recommended test setup for Front Board bit error rate testing............................................1665-88 Test point locations for Backplane testing ............................................................................1675-89 Backplane test setup with two 100GBASE-KR4 Backplane test paddle cards.....................168

A Advanced Differential Fabric connector generation 2 Definition - ADFplus (normative).......171

A-1 View of Zone 2 Connectors with common features ..............................................................173A-2 Dimensional drawing for ADFplus connectors......................................................................175A-3 Dimensional drawing of ADFplus Front Board connectors ...................................................176A-4 Front Board connector mounting ..........................................................................................177A-5 Pair under test (shaded light yellow) with 8 neighboring pairs..............................................178A-6 Victim pair (shaded light yellow) with surrounding aggressors ............................................179A-7 Pair under test (shaded light yellow) with 8 neighboring pairs..............................................180

B Advanced Differential Fabric connector generation 3 Definition - ADF++ (normative)..........181

B-1 Pair under test (shaded light yellow and surrounded) with 8 neighboring pairs....................187B-2 Power sum near-end crosstalk .............................................................................................188B-3 Victim pair (shaded light yellow and surrounded) with surrounding aggressors ...................188B-4 Measured insertion loss limits...............................................................................................189B-5 Pair under test (shaded light yellow and surrounded) with 8 neighboring pairs....................190B-6 Measured return loss limits ...................................................................................................191B-7 Pair under test (shaded light yellow and surrounded) with 8 neighboring pairs....................191

C Revision History ...........................................................................................................................193

May 5, 2016 xi

Figures

xii May 5, 2016

TABLES

Tables

1 Introduction and objectives .............................................................................................................1

1-1 Reference specifications...........................................................................................................21-2 Special word usage ..................................................................................................................31-3 Acronyms and special terms.....................................................................................................7

2 PICMG 3.0 compliance......................................................................................................................9

3 Hardware platform management ...................................................................................................11

3-1 LCLASS values.......................................................................................................................133-2 LEXT and LCLASS combinations...........................................................................................143-3 Link options.............................................................................................................................153-4 Example Link Descriptors: option 1 ........................................................................................163-5 Example Link Descriptors: option 1-K (also supports option 1) ..............................................173-6 Example Link Descriptors: option 1-KR (also supports options 1-K and 1) ............................183-7 Example Link Descriptors: option 1-K25 (also supports options 1-KR, 1-K and 1).................193-8 Example Link Descriptors: option 2 (also supports option 1)..................................................203-9 Example Link Descriptors: option 2-K (also supports options 2, 1-K, or 1).............................213-10 Example Link Descriptors: option 2-KR (also supports options 1-KR, 2-K, 2, 1-K and 1) ......223-11 Example Link Descriptors: option 2-K25 (also supports options 2-KR, 2-K, 2, 1-K25, 1-KR, 1-K

and 1)......................................................................................................................................243-12 Example Link Descriptors: option 3 (also supports options 2 or 1).........................................263-13 Example Link Descriptors: option 3-K (also supports options 3, 2-K, 2, 1-K, or 1) .................273-14 Example Link Descriptors: option 3-KR (also supports options 3-K, 3, 2-KR, 2-K, 2, 1-KR, 1-K,

or 1) ........................................................................................................................................293-15 Example Link Descriptors: option 3-K25 (also supports options 3-KR, 3-K, 3, 2-KR, 2-K, 2, 1-

KR, 1-K, or 1) ..........................................................................................................................313-16 Example Link Descriptors: option 4 (also supports options 1-K25, 1-KR, 1-K, 1, or 7) ..........343-17 Example Link Descriptors: option 5 (also supports options 2-K25, 2-KR, 2-K, 2, 1-K25, 1-KR,

1-K, 1, 4, or 7) .........................................................................................................................353-18 Example Link Descriptors: option 6 (also supports options 2-K25, 2-KR, 2-K, 2, 1-K25, 1-KR,

1-K, 1, 5, 4, 8, or 7) .................................................................................................................373-19 Example Link Descriptors: option 7 ........................................................................................393-20 Example Link Descriptors: option 8 (also supports option 7)..................................................393-21 Example Link Descriptor: option 9 ..........................................................................................393-22 Example Link Descriptor: option 9-K (also supports option 9) ................................................403-23 Example Link Descriptors: option 9-KR (also supports options 9-K, 9, 3-KR, 3-K, 3, 2-KR, 2-K,

2, 1-KR, 1-K, or 1)...................................................................................................................413-24 Example Link Descriptors: option 9-K25 (also supports options 9-KR, 9-K, 9, 3-K25, 3-KR, 3-

K, 3, 2-K25, 2-KR, 2-K, 2, 1-K25, 1-KR, 1-K, or 1) .................................................................433-25 Backplane Point-to-Point Connectivity Record .......................................................................483-26 Point-to-Point Slot Descriptor .................................................................................................493-27 Backplane Point-to-Point Connectivity Record Channel Descriptor .......................................493-28 Board Point-to-Point Connectivity Record ..............................................................................513-29 Link Descriptor ........................................................................................................................523-30 Link Class ...............................................................................................................................523-31 Link Type ................................................................................................................................523-32 Set Port State command.........................................................................................................55

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Tables

3-33 Get Port State command ........................................................................................................56

4 Data transport .................................................................................................................................57

4-1 AdvancedTCA Fabric Interface generic pin mappings ...........................................................574-2 PICMG 3.1 Channel options ...................................................................................................584-3 Channel Interface pin assignments for 1G, 1000BASE-KX, 10GBASE-KR, and 25GBASE-KR

Ethernet Ports.........................................................................................................................594-4 Ethernet with Fibre Channel pin assignments ........................................................................604-5 Channel Interface pin mappings for ..... 10GBASE-BX4, 10GBASE-KX4, 40GBASE-KR4, and

100GBASE-KR4 .....................................................................................................................60

5 Backplane physical layer interfaces .............................................................................................63

5-1 1000BASE-BX/FC-PI transmitter specifications at TPT .........................................................665-2 1000BASE-BX/FC-PI transmitter specifications at TPT .........................................................675-3 1000BASE-BX/FC-PI receiver specifications at TPR .............................................................695-4 1000BASE-BX/FC-PI jitter budget ..........................................................................................725-5 10GBASE-BX4 transmit specifications at TPT .......................................................................745-6 10GBASE-BX4 receiver specifications at TPR.......................................................................765-7 Description of LCLASS 0011b Channel test points ................................................................785-8 Description of the Backplane test assembly test points..........................................................835-9 Description of Front Board test card test points......................................................................935-10 Description of the Backplane test paddle card test points ....................................................1015-11 Description of LCLASS 0100b Channel test points ..............................................................1235-12 Description of the 100GBASE-KR4 Backplane test assembly test points ............................1255-13 Short Backplane Test Assembly Fitted Attenuation Parameters ..........................................1275-14 Insertion loss deviation limits for short 100GBASE-KR4 Backplane test assembly .............1285-15 Parameters for Short Backplane test assembly Insertion Loss to Crosstalk Ratio...............1295-16 Long Backplane test assembly Fitted Attenuation parameters.............................................1305-17 Insertion loss deviation limits for long 100GBASE-KR4 Backplane test assembly...............1325-18 Parameters for long Backplane test assembly Insertion Loss to Crosstalk Ratio.................1335-19 Description of the Front Board test card test points..............................................................1355-20 Parameters for 100GBASE-KR4 Front Board test card fitted attenuation ............................1365-21 Parameters for 100GBASE-KR4 Front Board test card insertion loss deviation ..................1385-22 Parameters for 100GBASE-KR4 Front Board test card return loss at TP A.........................1395-23 Parameters for 100GBASE-KR4 Front Board test card return loss at TP 2/TP 3.................1405-24 Parameters for 100GBASE-KR4 Front Board test card common mode return loss at TP A 1415-25 Parameters for 100GBASE-KR4 Front Board test card common mode return loss at TP 2/TP 3

..............................................................................................................................................1425-26 Parameters for 100GBASE-KR4 Front Board test card common mode conversion loss from TP

2/TP3 to TP A .......................................................................................................................1435-27 Parameters for 100GBASE-KR4 Front Board test card common mode conversion loss from TP

A to TP 2/TP 3 ......................................................................................................................1445-28 Parameters for 100GBASE-KR4 Front Board test card insertion loss to crosstalk ratio ......1455-29 Description of the 100GBASE-KR4 Backplane test paddle card test points ........................1475-30 Parameters for 100GBASE-KR4 Backplane test paddle card fitted attenuation ..................1495-31 Parameters for 100GBASE-KR4 Backplane test paddle card insertion loss deviation.........1515-32 Parameters for 100GBASE-KR4 Backplane test paddle card return loss at TP B ...............1525-33 Parameters for 100GBASE-KR4 Backplane test paddle card return loss at TP 1/TP 4 .......1535-34 Parameters for 100GBASE-KR4 Backplane test paddle card common mode return loss at TP B

..............................................................................................................................................1545-35 Parameters for 100GBASE-KR4 Backplane test paddle card common mode return loss at TP

xiv May 5, 2016

TABLES

1/TP 4 ...................................................................................................................................1555-36 Parameters for 100GBASE-KR4 Backplane test paddle card common mode conversion loss

from TP 1/TP4 to TP B .........................................................................................................1565-37 Parameters for 100GBASE-KR4 Backplane test paddle card common mode conversion loss

from TP B to TP 1/TP4 .........................................................................................................1575-38 Parameters for 100GBASE-KR4 Backplane test paddle card insertion loss to crosstalk ratio ...

..............................................................................................................................................1585-39 Parameters for 100GBASE-KR4 Front Board fitted attenuation...........................................1605-40 Parameters for 100GBASE-KR4 Front Board return loss.....................................................1625-41 Parameters for 100GBASE-KR4 Front Board common mode return loss ............................163

A Advanced Differential Fabric connector generation 2 Definition - ADFplus (normative).......171

A-1 Electrical characteristics ........................................................................................................178A-2 Intra-pair skew.......................................................................................................................180

B Advanced Differential Fabric connector generation 3 Definition - ADF++ (normative)..........181

B-1 Electrical characteristics ........................................................................................................186B-2 Intra-pair skew.......................................................................................................................189

C Revision History ...........................................................................................................................193

May 5, 2016 xv

Tables

xvi May 5, 2016

Introduction and objectives

Introduction and objectives 1

¶ 1 The PICMG® 3.1 specification is a member of the PICMG 3 AdvancedTCA series of specifications. The base specification in the family, PICMG 3.0, is required to understand this specification. The PICMG 3.0 base specification implements a Board and Shelf architecture where the Boards all have point-to-point differential pair serial-data links to communicate with each other. The base design is sufficiently generic that it can accommodate many different link-level standards. PICMG 3.1 establishes the usage of Ethernet (IEEE 802.3) and Fibre Channel (NCITS T11) communication within the AdvancedTCA Shelf.

¶ 2 Ethernet is a highly successful LAN (Local Area Network) standard with support from a wide array of silicon, board, and software vendors. Originally developed by a consortium consisting of Digital Equipment Corporation, Intel, and Xerox (“DIX”) it was eventually standardized in 1983. Higher speeds of operation and other new capabilities have been defined and incorporated into the standard over the years. IEEE 802.3 and its amendments are approved as national standards by ANSI, and international standards by ISO, although these approvals will lag from IEEE Standards Association approval. The international standards are published as ISO/IEC 8802-3. The Ethernet standards referred to by PICMG 3.1 are listed in Section 1.2.1, “Reference specifications.”

¶ 3 Fibre Channel has become a very popular standard for the connection of disk media storage systems with processors to form SANs (Storage Area Networks). It has been incorporated into PICMG 3.1 to allow the development of Shelf units with mass storage in addition to processing and switching. PICMG 3.1 supports a Fibre Channel Port as FC-PI. The default for a FC-PI Port is 1 Gbps, however if both ends have Auto-Negotiation implemented, a data rate of 2 Gbps can be achieved. In general, the use of Fibre Channel is expected to be used in parallel with Ethernet, although PICMG 3.1 does not preclude the use of Fibre Channel only.

¶ 4 PICMG 3.1 supports 10 Gigabit Ethernet via AdvancedTCA® Channels using EEE 25GBASE-KR, IEEE 10GBASE-KX4, IEEE 10GBASE-KR, I and XAUI signaling, 100 Gigabit Ethernet using IEEE 100GBASE-KR4 signaling, 40 Gigabit Ethernet using IEEE 40GBASE-KR4 signaling, and 100 Gigabit Ethernet using IEEE 100GBASE-KR4 signaling.

1.1 Objectives

¶ 5 The specification in this document is derived from and is dependent upon, the PICMG 3.0 base specification. It is not intended to stand-alone or to be used separately from the base specification.

¶ 6 PICMG 3.1 builds upon the PICMG 3.0 base specification, the IEEE 802.3-2008, IEEE 802.3ba-2010, and EEE 802.3by specifications as well as the Fibre Channel FC-PI specifications, to meet the following objectives:

• Define the signals to be used over the data Link Channels provided by PICMG 3.0 based on Ethernet/Fibre Channel-compatible devices.

• Support over each PICMG 3.0 Channel the option of

— One Port of Gigabit or 10-Gigabit Ethernet or 25-Gigabit Ethernet

PICMG 3.1 R3.0, May 5, 2016 1


— Two Ports (Link-aggregated optional) of Gigabit or 10-Gigabit Ethernet or 25-Gigabit Ethernet

— Four Ports (Link-aggregated optional) of Gigabit or 10-Gigabit Ethernet or 25-Gigabit Ethernet

— Optionally one or two Ports of Fibre Channel

— One Channel of 10-Gigabit or 40-Gigabit Ethernet or 100-Gigabit Ethernet (utilizes all four Ports)

• Establish the rules for compatibility between PICMG 3.1 devices.

• Define design rules such that devices compatible with some standard other than PICMG 3.1 in the PICMG 3.x family can be safely inserted in the same system, even if they do not function.

1.2 Reference documents

¶ 7 The publications cited in this section are relevant to this specification. Most of the specifications referred to are subject to periodic and independent updates, and are the responsibility of their respective organizations. The reader is advised to check carefully the version or revision of the referenced specification that is to be used in conjunction with this document.

¶ 8 Unless specifically stated, nothing in the PICMG 3.1 specification is intended to override or supersede a referenced specification.

1.2.1 Reference specifications

¶ 9 All documents can be obtained from their respective organizations.

Table 1-1 Reference specifications

Document Organization Contact info

PICMG Policies and Procedures for Specification Development

PCI Industrial Computer Manufacturers Group®

http://www.picmg.org

PICMG 3.0 Release 3.0 Specification PCI Industrial Computer Manufacturers Group®


INCITS-352 Fibre Channel Physical Interfaces (FC-PI) Information technology - Fibre Channel 1998 Physical Interface (FC-PI'98)

INCITS T11 http://www.t11.org

IEEE 802.3-2008 IEEE Standard for Information technology-Specific requirements - Part 3: Carrier Sense Multiple Access with Collision Detection (CMSA/CD) Access Method and Physical Layer Specifications

IEEE 802 http://standards.ieee.org/getieee802/802.3.html

IEEE 802.3ba-2010 IEEE 802http://grouper.ieee.org/groups/802/3/ba/index.html

IEEE 802.3by IEEE 802http://grouper.ieee.org/groups/802/3/by/index.html

2 PICMG 3.1 R3.0, May 5, 2016

http://grouper.ieee.org/groups/802/3/ba/index.html


http://www.picmg.or

http://www.t11.org

http://standards.ieee.org/getieee802/802.3.html

http://grouper.ieee.org/groups/802/3/ba/index.html


1.2.2 Environment and regulatory documents

¶ 10 All environment and regulatory requirements that pertain to the PICMG 3.1 specification are cited within the PICMG 3.0 base specification.

1.3 Special word usage

¶ 11 In this specification, the following key words (in bold text) will be used:

Table 1-2 Special word usage

Note: When not in bold text, the words “may,” “should,” and “shall” are being used in the traditional sense; that is, they do not adhere to the strict meanings described above.

¶ 12 This document uses requirements numbering as a way to find and reference requirements. Each requirement is numbered using the format “REQ X.YYz” where X is the original section where the requirement was located, YY denotes the requirement number and is a running sequence for each section, z denotes the revision of the requirement. Requirement revisions note changes made to a requirement from the originally published requirement.

1.4 Statement of compliance

¶ 13 Statements of compliance with this specification take the form specified in the PICMG® Policies and Procedures for Specification Development:

¶ 14 “This product complies with PICMG® 3.1 Revision 3.0.”

¶ 15 Products making this simple claim of compliance must provide, at a minimum, all features defined in numbered requirements (REQ X.YYz) listed in this specification as being mandatory by use of the keyword “shall” in the body of the requirement. Such products must not include any feature prohibited by the use of the keyword “shall not” in the numbered requirements contained in the specification. Such products may also provide recommended features associated with the keyword “should” and permitted features associated with the key word “may” contained within the numbered requirements.

¶ 16 A simple claim of compliance with a subsidiary specification indicates the presence of all features defined as being mandatory by the use of the keyword “shall” in the body of that specification and must not include any feature prohibited by the use of the keyword “shall

may Indicates flexibility of choice with no implied preference.

shouldIndicates flexibility of choice with a strongly preferred implementation. The use of should not (in bold text) indicates flexibility of choice with a strong preference that the choice or implementation be avoided.

shall

Indicates a mandatory requirement. Designers shall implement such mandatory requirements to ensure interchangeability and to claim conformance with this specification. The use of shall not (in bold text) indicates an action or implementation that is prohibited.

PICMG 3.1 R3.0, May 5, 2016 3


not.” Because subsidiary specifications may also provide for recommended and permitted features beyond the mandatory minimum set and a range of performance capabilities, more complete descriptions of product compliance are encouraged.

1.5 Name and logo usage

¶ 17 The PCI Industrial Computer Manufacturers Group’s policies regarding the use of its logos and trademarks are as follows:

¶ 18 Permission to use the PICMG organization logo is automatically granted to designated members only as stipulated on the most recent Membership Privileges document (available at www.picmg.org) during the period of time for which their membership dues are paid. Non-members must not use the PICMG organization logo.

¶ 19 The PICMG organization logo must be printed in black or color as shown in the files available for download from the member’s side of the Web site. Logos with or without the “Open Modular Computing Specifications” banner can be used. Nothing may be added or deleted from the PICMG logo.

¶ 20 Manufacturers’ distributors and sales representatives may use the AdvancedTCA® logo (but not the PICMG organization logo) in promoting products sold under the name of the manufacturer. The use of the AdvancedTCA logo is a privilege granted by the PICMG organization to companies who have purchased the relevant specifications (or acquired them as a member benefit), and who believe their products comply with these specifications. Use of the logos by either members or non-members implies such compliance. PICMG may revoke permission to use logos if they are misused. The AdvancedTCA logo can be found on the PICMG web site, www.picmg.org.

¶ 21 Color information for the red parts of the AdvancedTCA® logos is as follows:

– Pantone 032 CVC is the closest match.

– CMYK colors are C:0, M:100, Y:100, K:0.

– RGB is R:237, G:28, B:36.

• The PICMG® name and logo, the AdvancedTCA® name and logos, and the AdvancedMC® name and logo are registered trademarks of PICMG®. Registered trademarks must be followed by the ® symbol, and the following statement must appear in all published literature and advertising material in which the logo appears:

PICMG, the AdvancedTCA name and logos, the AdvancedMC name and logo, and the PICMG logo are registered trademarks of the PCI Industrial Computers Manufacturers Group.

• The AdvancedMC™ name and logo are trademarks of PICMG®. Trademarks must be followed by the ™ symbol, and the following statement must appear in all published literature and advertising material in which the logo appears:

The AdvancedMC name and logo are trademarks of the PCI Industrial Computers Manufacturers Group.

¶ 22 The term “AMC” is an abbreviation and may not be used as a logo or in logo form due to the possible infringement of an existing trademark outside of PICMG for the term “AMC.

4 PICMG 3.1 R3.0, May 5, 2016



1.6 Signal naming conventions

¶ 23 All signals are active high unless denoted by a trailing # symbol. Differential signals are denoted by a trailing + (positive) or – (negative) symbol.

1.7 Intellectual property

¶ 24 The Consortium draws attention to the fact that it is claimed that compliance with this specification might involve the use of a patent claim(s) (Intellectual Property - “IPR”). The Consortium takes no position concerning the evidence, validity, or scope of this IPR.

¶ 25 Under the PICMG Intellectual Property Rights Policy adopted by the Executive Membership September 14, 2004, the license grants of Necessary Claims made in connection with this specification apply only to the Compliant Portion of an implementation. As a result they apply only to the required (as designated by the keyword “shall”) or recommended (as designated by the keyword “should”) elements of a specification that are within the bounds of the Statement of Work under which the Specification was developed.

¶ 26 The holder of this IPR has assured the Consortium that it is willing to license or sublicense all such IPR to those licensees (Members and non-Members alike) desiring to implement this specification. The statement of the holder of this IPR to such effect has been filed with the Consortium.

¶ 27 Attention is also drawn to the possibility that some of the elements of this specification might be the subject of IPR other than those identified below. The Consortium is not responsible for identifying any or all such IPR.

¶ 28 No representation is made as to the availability of any license rights for use of any IPR inherent in this specification for any purpose other than to implement this specification.

¶ 29 Refer to PICMG IPR Policies and Procedures and the company owner of the patent for terms and conditions of usage.

¶ 30 PICMG makes no judgment as to the validity of these claims or the licensing terms offered by the claimants.

¶ 31 THIS SPECIFICATION IS BEING OFFERED WITHOUT ANY WARRANTY WHATSOEVER, AND IN PARTICULAR, ANY WARRANTY OF NON-INFRINGEMENT IS EXPRESSLY DISCLAIMED. ANY USE OF THIS SPECIFICATION IS MADE ENTIRELY AT THE IMPLEMENTER'S OWN RISK, AND NEITHER THE CONSORTIUM, NOR ANY OF ITS MEMBERS OR SUBMITTERS, HAVE ANY LIABILITY WHATSOEVER TO ANY IMPLEMENTER OR THIRD PARTY FOR ANY DAMAGES OF ANY NATURE WHATSOEVER, DIRECTLY OR INDIRECTLY, ARISING FROM THE USE OF THIS SPECIFICATION.

¶ 32 Compliance with this specification does not absolve manufacturers of equipment from the requirements of safety and regulatory agencies (UL, CSA, FCC, IEC, etc.).

¶ 33 This specification conforms to the current PICMG® Intellectual Property Rights Policy and the Policies and Procedures for Specification Development and does not contain any known intellectual property that is not available for licensing under Reasonable and Non-discriminatory terms. In the course of Membership Review the following disclosures were made:

PICMG 3.1 R3.0, May 5, 2016 5


1.7.1 Necessary claims

¶ 34 This specification requires implementations of the Intelligent Platform Management Interface and Intelligent Platform Management Bus specifications. The IPMI Promoters (Dell, HP, Intel Corporation and NEC Corporation) require that implementers of either of these specifications sign the IPMI Adopters Agreement. Please refer to www.intel.com/design/servers/ipmi for details.

¶ 35 ERNI Electronics GmbH, "Plug Connector and Multilayer Board", US Patent 7,901,248

¶ 36 ERNI Electronics GmbH, "Connector and Multilayer Circuit Board", European Patent 2207244

¶ 37 Intel Corporation, "Apparatus and Method for Improving Printed Circuit Board Signal Layer Transitions", US Application# 20060090933

¶ 38 Intel Corporation, "Modular Server Architecture", US Patent 6,950,895

¶ 39 Intel Corporation, "Printed circuit board trace routing method", US Patent 7,022,919

¶ 40 Intel Corporation, "Conductor Trace Design to Reduce Common Mode Cross-talk and Timing Skew", US Patent 7,343,576

¶ 41 Intel Corporation, "Modular Server Architecture with Ethernet Routed Across a Backplane Utilizing an Integrated Ethernet Switch Module", US Patent 7,339,786

1.7.2 Unnecessary claims

¶ 42 (Referring to optional features or non-normative elements)

¶ 43 No disclosures in this category have been made.

1.7.3 Third party disclosures

¶ 44 (Note that third party IPR submissions do not contain any claim of willingness to license the IPR.)

¶ 45 Siemens Aktiengesellschaft, "Device for Transmitting High-Frequency Signals", US Patent 6,304,700, European Patent 0 983 617, International PCT/DE1998/001262

¶ 46 Teradyne, Inc., "Printed Circuit Board for Differential Signal Electrical connectors", US Patent 6,607,402

1.8 Acronyms and definitions

¶ 47 The following terms and acronyms are used in specific ways throughout this document. The PICMG 3.0 base specification also provides an extensive glossary of terms that are used in this document.

6 PICMG 3.1 R3.0, May 5, 2016

http://www.intel.com/design/servers/ipmi

http://www.intel.com/design/servers/ipmi


Table 1-3 Acronyms and special terms

ADFplus A higher-fidelity version of the ADF (Advanced Differential Fabric) connector defined in PICMG 3.0.

Auto-Negotiation A method of automatically determining features to use, as defined by IEEE 802.3 specifications.

CAT5 CATegory 5

FC-PI Fibre Channel-Physical Interface

Gbd Giga-Baud

GHz Gigahertz

GND Ground

Hz Hertz

IEEE Institute of Electrical and Electronics Engineers

ISO International Standards Organization

kHz Kilohertz

LCLASS 0011bThis refers to Boards or Backplanes capable of 10GBASE-KR and 40GBASE-KR4 signaling.

NC No Connect

MHz Megahertz

mil Unit of measure equal to 0.001 inches

mV milliVolts

mVp-p milliVolts peak to peak

PMD Physical Medium Dependent

RPSMA Reverse Polarity SubMiniature version A

SerDes Serializer/Deserializer

SMA SubMiniature version A

XAUI 10 Gigabit Attachment Unit Interface

PICMG 3.1 R3.0, May 5, 2016 7


8 PICMG 3.1 R3.0, May 5, 2016

PICMG 3.0 compliance

PICMG 3.0 compliance 2

¶ 48 The PICMG 3.1 specification is derived from the PICMG 3.0 specification, which fully addresses all issues regarding mechanical form, power distribution, and thermal characteristics. The notes provided in this section are provided for continuity. Where exceptions exist, requirements in this document take precedence over PICMG 3.0.

2.1 Mechanical

Requirements

REQ 2.1 A PICMG 3.1 Board shall conform to all the mechanical specifications set forth in PICMG 3.0 as detailed by Section 2 of the PICMG 3.0 specification.

REQ 2.2 The Zone 2 Connector shall conform to one of the connector specifications in PICMG 3.0, the connector specification in Appendix A, “Advanced Differential Fabric connector generation 2 Definition - ADFplus (normative),” or Appendix B, “Advanced Differential Fabric connector generation 3 Definition - ADF++ (normative).”

REQ 2.3 Boards supporting 10GBASE-KR or 40GBASE-KR4 technology across Zone 2 shall use ADFplus or ADF++ connectors for Zone 2 connections.

REQ 2.4 Boards supporting 25GBASE-KR or 100GBASE-KR4 technology across Zone 2 shall use ADF++ connectors for Zone 2 connections.

2.2 Power distribution

Requirements

REQ 2.5 A PICMG 3.1 Board shall conform to all the power specifications set forth in PICMG 3.0 as detailed by Section 4 and other sections of the PICMG 3.0 specification.

2.3 Thermal

Requirements

REQ 2.6 A PICMG 3.1 Board shall conform to all the thermal specifications set forth in PICMG 3.0 as detailed by Section 5 and other sections of the PICMG 3.0 specification.

PICMG 3.1 R3.0, May 5, 2016 9

PICMG 3.0 compliance

10 PICMG 3.1 R3.0, May 5, 2016

Hardware platform management

Hardware platform management 3

3.1 Introduction

¶ 49 The PICMG 3.1 hardware platform management requirements are derived from and based upon the features provisioned in Section 3, Hardware platform management, of the PICMG 3.0 base specification. Hardware platform management is applicable to Ethernet/Fibre Channel over the Fabric interface.

¶ 50 Two states where hardware platform management is most evident in its interaction with the Ethernet/Fibre Channel signaling are:

• At system power on

• During insertion or extraction of a Hub or Node Board.

¶ 51 The architecture of the control interface between hardware platform management and the Ethernet/Fibre Channel implementation is based on event messaging. Event messaging is used to facilitate both Electronic-Keying (E-Keying) and Operational State (M3, M4, ...) transitions. Ultimately, the actions taken by the Node and Hub Boards, in order to comply with the E-Keying, are implementation dependent. Please refer to Section 3 of PICMG 3.0 for further details on E-Keying and operational states.

3.2 PICMG 3.1 implementation requirements

3.2.1 Implementation independent requirements

¶ 52 The most noteworthy requirements pertain to E-Keying, Operational State transitions, and the existence of an IPM Controller on the Node and Hub Boards.

Requirements

REQ 3.1 PICMG 3.1-compliant connections shall support E-Keying between the Shelf Manager and the IPM Controller.

REQ 3.2 PICMG 3.1-compliant designs shall adhere to the requirements of the PICMG 3.0 base specification, Section 3.

3.3 Messaging algorithm

¶ 53 Upon detection of a Hub or Node Board during the power-on state or Board insertion, the Link Designator, Link Class, Link Type, Link Type Extension, and Link Grouping ID are read by the Shelf Manager from FRU information. The Shelf Manager determines if the Port partners are compatible, and notifies the IPM Controller on the respective Hub or Node Board via the IPMB-0 management bus. The Shelf Manager determination of matching Ports is based on a comparison of each of the Link Descriptor fields. Upon identifying a match, the

PICMG 3.1 R3.0, May 5, 2016 11


Shelf Manager sends a “Set Port State” command to the IPM Controller, indicating the Link to be enabled or disabled, augmented with a description of the Channel capabilities required. This process is detailed in Section 3 of the PICMG 3.0 base specification.

3.4 E-Keying extensions

¶ 54 The Link Type and Link Designator (Ports and Channels) are defined within the PICMG 3.0 hardware platform management section. One of the main underlying assumptions of E-Keying is that a capabilities description (a.k.a. Link description contained in the FRU) is read by the Shelf Manager for every Port present in the Channel. The Link Descriptors are listed in order of preference. The Shelf Manager proceeds with its comparison of the Port partner’s capabilities, and the actual Links enabled are determined by application dependent policies implemented in the Shelf Manager.

Note: The preference order is adjusted in this specification to maximize backwards compatibility.

3.4.1 Link Descriptor

¶ 55 Each Node and Hub Board must provide information about each Link to the Shelf Manager upon insertion and initialization. For the Board FRU information, the capabilities of all Fabric Channels and Ports are recorded via the Link Descriptor, which has five fields:

Link Designator (12 bits), comprised of Channel Number (6 bits)Interface (2 bits)

00b = Base Interface01b = Fabric Interface 10b = Update Channel Interface 11b = Reserved

Port 0-3 Flags (4 bits)

Link Type (4 bits) 0000b = Reserved0001b = PICMG 3.0 Base Interface 10/100/1000 BASE-T0010b = PICMG 3.1 Ethernet/Fibre Channel Interface0011b = PICMG 3.2 InfiniBand Fabric Interface0100b = PICMG 3.3 StarFabric Fabric Interface0101b = PICMG 3.4 PCI Express Fabric Interface0110b - 1110b = Reserved1111b = OEM/Reserved

Link Class = (4 bits)

Link Type Extension = (4 bits)

Link Group ID (8 bits)

12 PICMG 3.1 R3.0, May 5, 2016


3.4.2 LDES: Link Designator

¶ 56 The Link Designator uniquely identifies the Channel, Interface, and Port being described. For PICMG 3.1, only SerDes Ethernet and Fibre Channel technologies are permitted to be used on the Fabric Interface. The Link Designator fields are defined in Table 3-51 of PICMG 3.0.

3.4.3 LTYPE: Link Type

¶ 57 The Link Type values are assigned one per subsidiary specification. For PICMG 3.1, the value 0010b has been assigned.

3.4.4 LCLASS: Link Class

¶ 58 The Link Class field is newly defined in PICMG 3.1. In PICMG 3.0, these bits are defined as the upper 4 bits within the Link Type field and were defined as zero or Fh. The PICMG 3.1 specification redefines the Link Type field and splits it into an upper 4 bit Link Class field and a lower 4 bit Link Type. For this specification, the following Link Class values are used.

3.4.5 LEXT: Link Type Extension

¶ 59 The Link Type Extension bits are governed by the subsidiary specification and have no meaning outside of the context of the specification. They are used by hardware platform management as a comparison flag, and cannot be assumed to convey information to hardware platform management other than match or mismatch. Link Type Extension values are unique within a given Link Type and Link Class.

¶ 60 Table 3-2, “LEXT and LCLASS combinations”specifies the values for LTYPE 0010b.

Table 3-1 LCLASS values

LCLASS values Description

0000b Basic signaling Link Class for all 1000BASE-BX, 10GBASE-BX4 (XAUI), FC-PI, 1000BASE-KX and 10GBASE-KX4 Link Type Extensions

0001b - 0010b Reserved

0011b 10.3125 Gbd signaling Link Class for 10GBASE-KR and 40GBASE-KR4 Link Type Extensions

0100b 25.78125 Gbd signaling Link Class for 25GBASE-KR and 100GBase-KR4 Link Type Extensions


1111b OEM/Reserved

PICMG 3.1 R3.0, May 5, 2016 13


NOTE: All unspecified LEXT & LCLASS combinations for Link Type 0010b are reserved by PICMG 3.1.

3.4.6 LGID: Link Grouping ID

¶ 61 The Link Grouping ID flag is used to indicate multiple Channels which are operated as a group on a Board. All Channels which are operated as a group on a Board are assigned the same, non-zero value. A LGID value of 00h always indicates an independent Port.

¶ 62 Note that hardware platform management does not compare LGID values between Boards, only between the Channels on a single Board.

Table 3-2 LEXT and LCLASS combinations

LEXT values LCLASS values Description

0000b 0000b Fixed 1000BASE-BX

0001b 0000b Fixed 10GBASE-BX4 (XAUI)

0010b 0000b FC-PI

0011b 0000b Fixed 1000BASE-KX

0100b 0000b Fixed 10GBASE-KX4

0101b - 1010b 0000b Reserved by PICMG 3.1

0000b 0011b Fixed 10GBASE-KR

0001b 0011b Fixed 40GBASE-KR4


0000b 0100b Fixed 25GBASE-KR

0001b 0100b Fixed 100GBASE-KR4


1011b - 1110b 1111b OEM

1111b 1111b Reserved by PICMG 3.0

14 PICMG 3.1 R3.0, May 5, 2016


3.5 Link and Link Descriptor options

¶ 63 Thirteen Port configurations, or options, are defined in this specification for implementing Ethernet and Fibre Channel within the Channel, as called out in Table 3-3, “Link options”. Options not listed in the table are not defined or supported within the PICMG 3.1 specification.

¶ 64 There are two different types of options described in Table 3-3, “Link options”: complex, and simple. Complex options include both Ethernet and Fibre Channel Ports. Simple options include Ethernet or Fibre Channel Ports but not both. Boards can support more than one option. By virtue of how options are coded in the Board FRU Information, Boards that support a simple option for Fibre Channel and a simple option for Ethernet will also support a complex option that combines the two. For instance, a Board that supports option 1 (Ethernet on Port 0) and option 7 (Fibre Channel on Port 3) will also support option 4

Table 3-3 Link options

Option Port 0 Port 1 Port 2 Port 3 DescriptionLink Type Extension

Link ClassLink

Descriptor Priority

1 X One 1000BASE-BX 0000b 0000b 8

1-K X One 1000BASE-KX 0011b 0000b 7

1-KR X One 10GBASE-KR 0000b 0011b 18

1-K25 X One 25GBASE-KR 0000b 0100b 14

2 X X Two 1000BASE-BX 0000b 0000b 6

2-K X X Two 1000BASE-KX 0011b 0000b 5

2-KR X X Two 10GBASE-KR 0000b 0011b 17

2-K25 X X Two 25GBASE-KR 0000b 0100b 13

3 X X X X Four 1000BASE-BX 0000b 0000b 4

3-K X X X X Four 1000BASE-KX 0011b 0000b 3

3-KR X X X X Four 10GBASE-KR 0000b 0011b 16

3-K25 X X X X Four 25GBASE-KR 0000b 0100b 12

4 (4-K, 4-KR, 4-K25)

X Uses descriptor for option 1, option 1-K, or option 1-KR, or option 1-K25

X Uses descriptor for option 7

5 (5-K, 5-KR, 5-K25)

X X Uses descriptor for option 2, option 2-K, or option 2-KR, or option 2-K25

X Uses descriptor for option 7

6 (6-K, 6-KR, 6-K25)

X X Uses descriptor for option 2, option 2-K, or option 2-KR, or option 2-K25

X X Uses descriptor for option 8

7 X One FC-PI 0010b 0000b 10

8 X X Two FC-PI 0010b 0000b 9

9 X X X X 10GBASE-BX4 0001b 0000b 2

9-K X X X X 10GBASE-KX4 0100b 0000b 1

9-KR X X X X 40GBASE-KR4 0001b 0011b 15

9-K25 X X X X 100GBASE-KR4 0001b 0100b 11

PICMG 3.1 R3.0, May 5, 2016 15


(Ethernet on Port1 and Fibre Channel on Port 4). Options supported by a Board are described by Link Descriptors inside the Board FRU Information Board Point-to-Point Connectivity Record.

¶ 65 The Link Descriptor Priority is assigned such that all Link Descriptors with a Link Class of 0000b are prioritized ahead of Link Descriptors with a Link Class greater than 0000b. This ensures interoperability and backwards compatibility with existing Backplanes and Shelf Managers as the Link Class = 0000b Link Descriptors will match first. A PICMG 3.1-compliant Shelf Manager understands this backward compatibility ordering priority and re-orders the Link Descriptors to move the Link Class 0000b descriptors to the end of the prioritized list when the Backplane is capable of supporting links with a Link Class greater than 0000b (See REQ 3.19).

¶ 66 Link Descriptors consist of Link Designator, Link Class, Link Type, Link Extension, and Link Grouping ID fields. Simple options will have corresponding single Link Descriptor in the Board FRU Information Board Point-to-Point Connectivity Record. Complex options require no additional Link Descriptors other than what is present for the simple options from which they are composed.

¶ 67 The PICMG 3.0 specification allows Link Descriptors within a Board FRU Information Board Point-to-Point Connectivity record to be listed in the order of preference for associated protocols. If not consistently implemented, however, this flexibility can lead to compatibility issues. The Link Descriptor Priority in Table 3-3, “Link options” recommends an order that Link Descriptors are listed in to ensure the desired option is enabled.

¶ 68 PICMG 3.1 requires that a single Link Descriptor be used for each simple option in Table 3-3, “Link options”. The Link Descriptor must include all Ports that share the same Link Type Extension. For example, option 3 must be described in one Link Descriptor with all four Ports in its Link Designator having 1000BASE-BX connectivity.

¶ 69 In order to support backward compatibility, it is desirable for Boards that support *-K options found in Table 3-3, “Link options” to also support equivalent options for 1000BASE-BX. It is also desirable for Boards that support option 9-K also support option 9 and for Boards that support any of the *-KR options to also support the corresponding *-K option.

¶ 70 Table 3-4, “Example Link Descriptors: option 1” through Table 3-24, “Example Link Descriptors: option 9-K25 (also supports options 9-KR, 9-K, 9, 3-K25, 3-KR, 3-K, 3, 2-K25, 2-KR, 2-K, 2, 1-K25, 1-KR, 1-K, or 1)” show example Link Descriptors that might be found in the Board FRU Information Board Point-to-Point connectivity record to support various options. Most of these tables show Link Descriptors for more than one option. Link Descriptors are placed in order of priority found in Table 3-3, “Link options”. The nnnnn values in these tables refer to the Channel Number.

Table 3-4 Example Link Descriptors: option 1

Link Descriptor #

Option Field Value Description

1 1

Link Designator 0001010nnnnnbPort 0 Enabled; Fabric Interface; Channel Number

Link Type 0010b Ethernet/Fibre Channel Fabric Interface

Link Class 0000b Basic signaling Link Class

Link Type Extension 0000b 1000BASE-BX

Link Grouping ID 00h Independent Channel

16 PICMG 3.1 R3.0, May 5, 2016


Table 3-5 Example Link Descriptors: option 1-K (also supports option 1)

Link Descriptor #


1 1-K

Link Designator 0001010nnnnnb Port 0 Enabled; Fabric Interface; Channel Number



Link Type Extension 0011b 1000BASE-KX


2 1






PICMG 3.1 R3.0, May 5, 2016 17


Table 3-6 Example Link Descriptors: option 1-KR (also supports options 1-K and 1)

Link Descriptor #


1 1-K






2 1






3 1-KR



Link Class 0011b 10.3125 Gbd signaling Link Class

Link Type Extension 0000b 10GBASE-KR


18 PICMG 3.1 R3.0, May 5, 2016


Table 3-7 Example Link Descriptors: option 1-K25 (also supports options 1-KR, 1-K and 1)

Link Descriptor #


1 1-K






2 1






3 1-K25






4 1-KR






PICMG 3.1 R3.0, May 5, 2016 19


Table 3-8 Example Link Descriptors: option 2 (also supports option 1)

Link Descriptor #


1 2

Link Designator 0011010nnnnnb Port 1,0 Enabled; Fabric Interface; Channel Number





2 1






20 PICMG 3.1 R3.0, May 5, 2016


Table 3-9 Example Link Descriptors: option 2-K (also supports options 2, 1-K, or 1)

Link Descriptor #


1 2-K






2 2






3 1-K






4 1






PICMG 3.1 R3.0, May 5, 2016 21


Table 3-10 Example Link Descriptors: option 2-KR (also supports options 1-KR, 2-K, 2, 1-K and 1)

Link Descriptor #


1 2-K






2 2






3 1-K






4 1






5 2-KR






22 PICMG 3.1 R3.0, May 5, 2016


6 1-KR






Table 3-10 Example Link Descriptors: option 2-KR (also supports options 1-KR, 2-K, 2, 1-K and 1) (Continued)

Link Descriptor #


PICMG 3.1 R3.0, May 5, 2016 23


Table 3-11 Example Link Descriptors: option 2-K25 (also supports options 2-KR, 2-K, 2, 1-K25, 1-KR, 1-K and 1)

Link Descriptor #


1 2-K






2 2






3 1-K






4 1






5 2-K25






24 PICMG 3.1 R3.0, May 5, 2016


6 1-K25






7 2-KR






8 1-KR






Table 3-11 Example Link Descriptors: option 2-K25 (also supports options 2-KR, 2-K, 2, 1-K25, 1-KR, 1-K and 1) (Continued)

Link Descriptor #


PICMG 3.1 R3.0, May 5, 2016 25


Table 3-12 Example Link Descriptors: option 3 (also supports options 2 or 1)

Link Descriptor # Option Field Value Description

1 3

Link Designator 1111010nnnnnb Port 3,2,1,0 Enabled; Fabric Interface; Channel Number





2 2






3 1






26 PICMG 3.1 R3.0, May 5, 2016


Table 3-13 Example Link Descriptors: option 3-K (also supports options 3, 2-K, 2, 1-K, or 1)

Link Descriptor #


1 3-K






2 3






3 2-K






4 2






5 1-K






PICMG 3.1 R3.0, May 5, 2016 27


6 1






Table 3-13 Example Link Descriptors: option 3-K (also supports options 3, 2-K, 2, 1-K, or 1)

Link Descriptor #


28 PICMG 3.1 R3.0, May 5, 2016


Table 3-14 Example Link Descriptors: option 3-KR (also supports options 3-K, 3, 2-KR, 2-K, 2, 1-KR, 1-K, or 1)

Link Descriptor #


1 3-K






2 3






3 2-K






4 2






5 1-K






PICMG 3.1 R3.0, May 5, 2016 29


6 1






7 3-KR






8 2-KR






9 1-KR






Table 3-14 Example Link Descriptors: option 3-KR (also supports options 3-K, 3, 2-KR, 2-K, 2, 1-KR, 1-K, or 1) (Continued)

Link Descriptor #


30 PICMG 3.1 R3.0, May 5, 2016


Table 3-15 Example Link Descriptors: option 3-K25 (also supports options 3-KR, 3-K, 3, 2-KR, 2-K, 2, 1-KR, 1-K, or 1)

Link Descriptor #


1 3-K






2 3






3 2-K






4 2






5 1-K






PICMG 3.1 R3.0, May 5, 2016 31


6 1






7 3-K25

Link Designator 1111010nnnnnbPort 3,2,1,0 Enabled; Fabric Interface; Channel Number





8 2-K25






9 1-K25






10 3-KR






Table 3-15 Example Link Descriptors: option 3-K25 (also supports options 3-KR, 3-K, 3, 2-KR, 2-K, 2, 1-KR, 1-K, or 1) (Continued)

Link Descriptor #


32 PICMG 3.1 R3.0, May 5, 2016


11 2-KR






12 1-KR






Table 3-15 Example Link Descriptors: option 3-K25 (also supports options 3-KR, 3-K, 3, 2-KR, 2-K, 2, 1-KR, 1-K, or 1) (Continued)

Link Descriptor #


PICMG 3.1 R3.0, May 5, 2016 33


Table 3-16 Example Link Descriptors: option 4 (also supports options 1-K25, 1-KR, 1-K, 1, or 7)

Link Descriptor #


1 1-K




Link Type Extension

0011b 1000BASE-KX


2 1




Link Type Extension

0000b 1000BASE-BX


3 7




Link Type Extension

0010b FC-PI


4 1-K25




Link Type Extension

0000b 25GBASE-KR


5 1-KR




Link Type Extension

0000b 10GBASE-KR


34 PICMG 3.1 R3.0, May 5, 2016


Table 3-17 Example Link Descriptors: option 5 (also supports options 2-K25, 2-KR, 2-K, 2, 1-K25, 1-KR, 1-K, 1, 4, or 7)

Link Descriptor #


1 2-K






2 2






3 1-K






4 1






5 7




Link Type Extension 0010b FC-PI


PICMG 3.1 R3.0, May 5, 2016 35


6 2-K25






7 1-K25






8 2-KR






9 1-KR






Table 3-17 Example Link Descriptors: option 5 (also supports options 2-K25, 2-KR, 2-K, 2, 1-K25, 1-KR, 1-K, 1, 4, or 7) (Continued)

Link Descriptor #


36 PICMG 3.1 R3.0, May 5, 2016


Table 3-18 Example Link Descriptors: option 6 (also supports options 2-K25, 2-KR, 2-K, 2, 1-K25, 1-KR, 1-K, 1, 5, 4, 8, or 7)

Link Descriptor #


1 2-K






2 2






3 1-K






4 1






5 8






PICMG 3.1 R3.0, May 5, 2016 37


6 7






7 2-K25






8 1-K25






9 2-KR






10 1-KR






Table 3-18 Example Link Descriptors: option 6 (also supports options 2-K25, 2-KR, 2-K, 2, 1-K25, 1-KR, 1-K, 1, 5, 4, 8, or 7) (Continued)

Link Descriptor #


38 PICMG 3.1 R3.0, May 5, 2016


Table 3-19 Example Link Descriptors: option 7

Link Descriptor #


1 7






Table 3-20 Example Link Descriptors: option 8 (also supports option 7)

Link Descriptor #


1 8






2 7






Table 3-21 Example Link Descriptor: option 9

Link Descriptor #


1 9




Link Type Extension 0001b 10GBASE-BX4 [XAUI]


PICMG 3.1 R3.0, May 5, 2016 39


Table 3-22 Example Link Descriptor: option 9-K (also supports option 9)

Link Descriptor #


1 9-K




Link Type Extension 0100b 10GBASE-KX4


2 9






40 PICMG 3.1 R3.0, May 5, 2016


Table 3-23 Example Link Descriptors: option 9-KR (also supports options 9-K, 9, 3-KR, 3-K, 3, 2-KR, 2-K, 2, 1-KR, 1-K, or 1)

Link Descript

or #Option Field Value Description

1 9-K






2 9






3 3-K






4 3






5 2-K






6 2






PICMG 3.1 R3.0, May 5, 2016 41


7 1-K






8 1






9 9-KR




Link Type Extension 0001b 40GBASE-KR4


10 3-KR






11 2-KR






12 1-KR






Table 3-23 Example Link Descriptors: option 9-KR (also supports options 9-K, 9, 3-KR, 3-K, 3, 2-KR, 2-K, 2, 1-KR, 1-K, or 1) (Continued)

Link Descript


42 PICMG 3.1 R3.0, May 5, 2016


Table 3-24 Example Link Descriptors: option 9-K25 (also supports options 9-KR, 9-K, 9, 3-K25, 3-KR, 3-K, 3, 2-K25, 2-KR, 2-K, 2, 1-K25, 1-KR, 1-K, or 1)

Link Descript


1 9-K






2 9





3 3-K




Link Type Extension

0011b 1000BASE-KX


4 3






PICMG 3.1 R3.0, May 5, 2016 43


5 2-K

Link Designator 0011010nnnnnbPort 1,0 Enabled; Fabric Interface; Channel Number



Link Type Extension

0011b 1000BASE-KX


6 2






7 1-K






8 1






Table 3-24 Example Link Descriptors: option 9-K25 (also supports options 9-KR, 9-K, 9, 3-K25, 3-KR, 3-K, 3, 2-K25, 2-KR, 2-K, 2, 1-K25, 1-KR, 1-K, or 1) (Continued)

44 PICMG 3.1 R3.0, May 5, 2016


9 9-K25




Link Type Extension 0001b 100GBASE-KR4


10 3-K25




Link Type Extension 0000b Fixed 25GBASE-KR


11 2-K25






12 1-K25







PICMG 3.1 R3.0, May 5, 2016 45


13 9-KR




Link Type Extension

0001b 40GBASE-KR4


14 3-KR






15 2-KR






16 1-KR







46 PICMG 3.1 R3.0, May 5, 2016


Requirements

REQ 3.3 At least one of the options listed in Table 3-3, “Link options” shall be supported.

REQ 3.4 Ordering of Link Descriptors present in the Board FRU Information Board Point-to-Point Connectivity record should follow the priority shown in Table 3-3, “Link options.”

REQ 3.5 Within the Board FRU Information Board Point-to-Point Connectivity record, for a given Channel, Link Descriptors with a Link Class of either 0000b or 1111b shall be prioritized and listed before all Link Descriptors with a Link Class other than 0000b or 1111b.

REQ 3.6 Four Ports of Ethernet connectivity shall be described in the Board FRU Information Board Point-to-Point Connectivity Record by a single Link Descriptor with Ports 0, 1, 2, and 3 enabled in the Link Designator field.

REQ 3.7 Two Ports of Ethernet connectivity shall be described in the Board FRU Information Board Point-to-Point Connectivity Record by a single Link Descriptor with Ports 0 and 1 enabled in the Link Designator field.

REQ 3.8 Two Ports of Fibre Channel connectivity shall be described in the Board FRU Information Board Point-to-Point Connectivity Record by a single Link Descriptor with Ports 2 and 3 enabled in the Link Designator field.

REQ 3.9 PICMG 3.1-compliant Link Descriptors shall set the Link Grouping ID field to 0.

REQ 3.10 Boards supporting 1000BASE-KX Ethernet options (Link Class 0000b, Link Type Extension 0011b) should support equivalent options for 1000BASE-BX (Link Class 0000b, Link Type Extension 0000b).

REQ 3.11 Boards supporting 10GBASE-KX4 Ethernet options (Link Class 0000b, Link Type Extension 0100b) should support equivalent options for 10GBASE-BX4 (Link Class 0000b, Link Type Extension 0001b).

REQ 3.12 Boards supporting Ethernet options with 10.3125 Gbd signaling (Link Class 0011b) should also support Ethernet options with basic 3.125 Gbd signaling (Link Class 0000b) for backwards compatibility.

REQ 3.12.1 Boards supporting Ethernet options with 25.78125 Gbd signaling (Link Class 0100b) should also support Ethernet options with 10.3125 Gbd signaling (Link Class 0011b) and basic 3.125 Gbd signaling (Link Class 0000b) for backwards compatibility.

3.6 Channel E-keying extensions

¶ 71 PICMG 3.1 introduces extensions to the Link Descriptor found in the Board Point-to-Point Connectivity Record and to the Point-to-Point Channel Descriptor found in the Backplane Point-to-Point Connectivity Record, that allow the Shelf Manager to select appropriate Port Link speeds based on Channel signaling characteristics.

3.6.1 Backplane Channel capabilities

¶ 72 Backplane Channel capabilities are stored in the Backplane Point-to-Point Connectivity Record within the Shelf FRU information. The Backplane Point-To-Point connectivity record is described in PICMG 3.0, Section 3.7.2.2 and contains Channel connectivity

PICMG 3.1 R3.0, May 5, 2016 47


information from each Slot to all other Slots. A Point-to-Point Channel Descriptor defines each connection. The data structure is shown pictorially in Figure 3-1, “Backplane Point-to-Point Connectivity Record structure.”

Figure 3-1 Backplane Point-to-Point Connectivity Record structure

¶ 73 The Backplane Point-to-Point Connectivity Record format for high-speed Backplane support is shown in Table 3-25, “Backplane Point-to-Point Connectivity Record.” The Record Format Version field contains a value of 01h to indicate that the record format supports Channel Signaling Class Capability encoded in the Point-to-Point Channel Descriptors.

Point-to-Point Slot Descriptor Point-to-Point Channel Descriptor

Point-to-Point Channel Descriptor


Point-to-Point Slot Descriptor

Point-to-Point Slot Descriptor

(One descriptor for each point-to-point Channel within the associated Slot)

Point-to-Point Channel DescriptorsPoint-to-Point Slot Descriptor List(One descriptor for each Slot within the Shelf)

Backplane Point-to-Point Connectivity Record

Shelf FRU information


Table 3-25 Backplane Point-to-Point Connectivity Record

Offset Length Definition

0 1Record Type ID. For all records defined in this specification a value of C0h (OEM) is used.

1 1

End of List/Version.

[7:7] - End of List. Set to one for the last record

[6:4] - Reserved, write as 0h

[3:0] - Record format version (=2h for this definition)

2 1 Record Length.

3 1 Record Checksum. Holds the zero checksum of the record.

4 1 Header Checksum. Holds the zero checksum of the header.

5 3Manufacturer ID. LS byte first. Write as the three byte ID assigned to PICMG®. For this specification, the value 12634 (00315Ah) is used

8 1 PICMG Record ID. For the Point-to-Point Connectivity record, the value 04h is used.

9 1 Record Format Version. For this specification, the value 01h is used.

10: (m+9)

M

Point-to-Point Slot Descriptor List. A list of variable length Point-to-Point Slot Descriptors (see Table 3-26, “Point-to-Point Slot Descriptor”) totaling m bytes in length. Each Point-to-Point Slot Descriptor describes the number of Channels and the connectivity for a specific type of point-to-point Channel from one Slot.

48 PICMG 3.1 R3.0, May 5, 2016


¶ 74 The Point-to-Point Slot Descriptor format is shown in Table 3-26, “Point-to-Point Slot Descriptor.” The Point-to-Point Slot Descriptor format is identical to the format used in version 00h of the Backplane Point-to-Point Connectivity Record.

¶ 75 The Signaling Capabilities Class of each Channel is encoded in the Point-to-Point Channel Descriptor for the Channel. The structure of the Backplane Connectivity Record Point-to-Point Channel Descriptor is shown in Table 3-27, “Backplane Point-to-Point Connectivity Record Channel Descriptor.”

¶ 76 Higher values of Channel Signaling Class Capability correspond to higher signaling class capabilities. The Shelf Manager makes sure that a Channel supports at least the minimum required signaling rate before allowing Port operation at that speed.

Requirements

REQ 3.13 Shelf FRU Information Backplane Point-to-Point Connectivity Record and Descriptors shall conform to Table 3-25, “Backplane Point-to-Point Connectivity Record,”

Table 3-26 Point-to-Point Slot Descriptor


0 1

Point-to-Point Channel Type. Indicates the type of point-to-point connectivity described by this descriptor, as follows:

00h - 07h = In use by PICMG® 2.9

08h = PICMG® 3.0 Single Port Fabric Interface

09h = PICMG®3.0 Double Port Fabric Interface

0Ah = PICMG® 3.0 Full Channel Fabric Interface

0Bh = PICMG® 3.0 Base Interface

0Ch = PICMG® 3.0 Update Channel Interface

0Dh = PICMG® 3.0 Base Interface ShMC Cross-connect

All other values are reserved for describing future Backplane capabilities.

1 1Slot Address. Indicates the Slot address for this Slot. For PICMG® 3.0 systems, this is the Hardware Address.

2 1Point-to-Point Channel Count. Indicates the number of point-to-point Channels in this Slot of the type specified in Point-to-Point Channel Type.

3 3*nPoint-to-Point Channel Descriptors. An array of n Point-to-Point Channel Descriptors (each with LS Byte first) where n is specified in the Point-to-Point Channel Count byte.

Table 3-27 Backplane Point-to-Point Connectivity Record Channel Descriptor

Bits Description

23:22 Reserved. Fixed to 0.

21:18

Channel Signaling Class Capability.

0000b = Basic signaling class (backward compatibility) This signaling class is as defined in PICMG 3.0 Section 8.2.4

0011b = 10.3125 Gbd level signaling class

0100b = 25.78125 Gbd level signaling class

Other values are reserved by PICMG for future signaling class level

17:13 Local Channel. Indicates the Channel number within the local Slot.

12:8Remote Channel. Indicates the Channel number within the remote Slot to which this point-to-point connection is routed.

7:0 Remote Slot. In PICMG® 3.0 systems, this is the Hardware Address of the remote Slot.

PICMG 3.1 R3.0, May 5, 2016 49


Table 3-26, “Point-to-Point Slot Descriptor,” and Table 3-27, “Backplane Point-to-Point Connectivity Record Channel Descriptor.”

REQ 3.14 The Signaling Channel Class Capabilities bits found in the Shelf FRU Information Backplane Point-to-Point Connectivity Record Point-to-Point Channel Descriptor shall be set to a value of 0000b for Channels that support a maximum of 3.125 Gbd.

REQ 3.15 The Channel Signaling Class Capabilities bits found in the Shelf FRU Information Backplane Point-to-Point Connectivity Record Point-to-Point Channel Descriptor shall be set to a value of 0011b for Channels that support 10.3125 Gbd as defined by Section 5, “Backplane physical layer interfaces.”

REQ 3.15.1 The Channel Signaling Class Capabilities bits found in the Shelf FRU Information Backplane Point-to-Point Connectivity Record Point-to-Point Channel Descriptor shall be set to a value of 0100b for Channels that support 25.78125 Gbd as defined by Section 5, “Backplane physical layer interfaces.”

3.6.2 Board Channel capabilities

¶ 77 Board Channel capabilities are stored in Board Point-to-Point Connectivity Records within the Board FRU Information. The Board Point-to-Point Connectivity Record is described in PICMG 3.0, Section 3.7.2.3 and describes the connections to the Base, Fabric, and Update Channel Interfaces that are implemented on the Board. A list of Link Descriptors defines each possible connection supported by the Board. The data structure is shown pictorially in Figure 3-2, “Board Point-to-Point Connectivity Record structure.”

Figure 3-2 Board Point-to-Point Connectivity Record structure

Board FRU information

Board Point‐to‐Point

Connectivity Record

Link Descriptor

Link Descriptor

Link Descriptor List

(One descriptor for each supported

point‐to‐point protocol)

Link Descriptor

Link Descriptor

50 PICMG 3.1 R3.0, May 5, 2016


¶ 78 The Board Point-to-Point Connectivity Record format for high-speed Board support is shown in Table 3-28, “Board Point-to-Point Connectivity Record.” The Record Format Version field contains a value of 01h to indicate that the record format supports Link Class encoded in the Link Descriptors.

¶ 79 The Link Descriptor format is shown in Table 3-29, “Link Descriptor.” The Link Descriptor format was originally specified in PICMG 3.0 Table 3-50, “Link Descriptor.” To support high-speed Boards beyond the capability of the original PICMG 3.0 specification, the PICMG 3.1 specification updates the Link Descriptor record by dividing the original 8-bit Link Type field into an upper 4-bit Link Class field and a lower 4-bit Link Type field. The Link Class field indicates the required Backplane Channel signaling class and corresponds directly to the Channel Signaling Class Capability field defined in Table 3-27, “Backplane Point-to-Point Connectivity Record Channel Descriptor.” Since the upper 4 bits of all previously defined PICMG 3.0 Link Types are zero, the Link Class value of 0000b is used for backward compatibility to indicate the PICMG 3.0 defined Backplane signaling class capability for 3.125 Gbd differential interfaces. PICMG 3.0 also defines an OEM GUID Link Type with values in the range of F0h-FEh. For backwards compatibility, the Link Class value of 1111b is defined as the OEM GUID Link Class which is treated the same as Link Class 0000b, basic signaling class capability for 3.125 Gbd differential interfaces. The Link Type field is shortened to 4-bits and retains the original lower 4-bit values of the former 8-bit Link Type field.

Table 3-28 Board Point-to-Point Connectivity Record


0 1 Record Type ID. For all records defined in this specification a value of C0h (OEM) is used.

1 1 End of List/Version.

7:7 - End of List. Set to one for the last record

6:4 - Reserved, write as 0h

3:0 - Record format version (=2h for this definition)

2 1 Record Length.

3 1 Record Checksum. Holds the zero checksum of the record.

4 1 Header Checksum. Holds the zero checksum of the header.

5 3 Manufacturer ID. LS byte first. Write as the three byte ID assigned to PICMG®. For this specification, the value 12634 (00315Ah) is used.

8 1 PICMG Record ID. For the Board Point-to-Point Connectivity record, the value 14h is used.

9 1 Record Format Version. For this specification, the value 01h is used.

10 1 OEM GUID Count. The number, n, of OEM GUIDs defined in this record.

11 16*n OEM GUID List. A list 16*n bytes of OEM GUIDs.

11 + 16*n m Link Descriptor list. A variable length list of four byte Link Descriptors (LS Byte first) (see Table 3-29, “Link Descriptor,” Table 3-30, “Link Class,” and Table 3-31, “Link Type”) totaling m bytes in length.

Each Link Descriptor details one type of point-to-point protocol supported by the referenced Channels.

PICMG 3.1 R3.0, May 5, 2016 51


¶ 80 PICMG 3.0 defines the 8-bit Link Type of F0h…FEh as the E-Keying OEM GUID Definition. To preserve backwards compatibility, Link Class 1111b is maintained as the OEM GUID Definition for PICMG 3.1. When the OEM GUID Link Class is used, the Link Type values 0000b-1110b are defined to be the lower 4 bits of the OEM GUID Definition and the Link Type value 1111b is reserved. OEM GUID Definition Link Types are defined to be basic Link signaling class Links for backwards compatibility. For Link Class values in the range 0000b-1110b, the Link Type is as defined in Table 3-31, “Link Type.”

Table 3-29 Link Descriptor

Bit Offset Descriptor

31:24 Link Grouping ID. Indicates whether the Ports of this Channel are operated together with Ports in other Channels. A value of 0 always indicates a Single-Channel Link. A common, non-zero Link Grouping ID in multiple Link Descriptors indicates that the Ports covered by those Link Descriptors must be operated together. A unique non-zero Link Grouping ID also indicates Single-Channel Link.

23:20 Link Type Extension. Identifies the subset of a subsidiary specification that is implemented and is defined entirely by the subsidiary specification identified in the Link Type field.

19:16 Link Class. Indicates the signaling class of the Link defined in the Link Type and Link Type Extension fields within this record; see Table 3-30, “Link Class.”

15:12 Link Type. Identifies the PICMG® 3.x subsidiary specification that governs this description or identifies the description as proprietary; see Table 3-31, “Link Type.”

11:0 Link Designator. Identifies the Interface Channel and the Ports within the Channel that are being described; see PICMG 3.0 Table 3-51, “Link Designator”.

Table 3-30 Link Class

Class Description

0000b Basic Link signaling class (backward compatibility). This Link Class is as defined in PICMG 3.0 Section 8.2.4 and supports interfaces with differential signaling rates up to 3.125 Gbd.


0011b 10.3125 Gbd Link signaling class. This Link Class is defined in Section 5.3, “1000BASE-KX and 10GBASE-KX4 specifications” and supports interfaces with differential signaling rates up to 10.3125 Gbd.

0100b 25.78125 Gbd Link signaling class. This Link Class is defined in Section 5.6, “100GBASE-KR4 Channel characteristics” and supports interfaces with differential signaling rates up to 25.78125 Gbd.

0101b -1110b Reserved.

1111b OEM GUID Definition. When Link Type value 0000b-1110b

Reserved. When Link Type value is 1111b

Table 3-31 Link Type

Type Description

0000b Reserved

0001b PICMG 3.0 Base Interface 10/100/1000 BASE-T

0010b PICMG 3.1 Ethernet Fabric Interface

0011b PICMG 3.2 InfiniBand Fabric Interface

52 PICMG 3.1 R3.0, May 5, 2016


Requirements

REQ 3.16 Board FRU Information Board Point-to-Point Connectivity Record and Link Descriptors shall conform to Table 3-28, “Board Point-to-Point Connectivity Record,” Table 3-29, “Link Descriptor,” Table 3-30, “Link Class,” and Table 3-31, “Link Type.”

REQ 3.17 The Link Class bits found in the Board Point-to-Point Connectivity Record Link Descriptors shall be set to a value of 0000b for interfaces that support a maximum differential signaling rate of 3.125 Gbd.

REQ 3.18 The Link Class bits found in the Board Point-to-Point Connectivity Record Link Descriptors shall be set to a value of 0011b for interfaces that support a maximum differential signaling rate of 10.3125 Gbd.

REQ 3.18.1 The Link Class bits found in the Board Point-to-Point Connectivity Record Link Descriptors shall be set to a value of 0100b for interfaces that support a maximum differential signaling rate of 25.78125 Gbd.

3.6.3 E-Keying process

¶ 81 The following text describes the updates to the E-Keying process defined in PICMG 3.0 Section 3.7.1, “E-Keying process,” to support high speed signaling Boards and Backplanes. As described in Section 3.6.1, “Backplane Channel capabilities,” the Backplane Point-to-Point Connectivity Record Channel Descriptors have been updated in the Shelf FRU information to include a Channel Signaling Class Capability field which indicates the capabilities of the Backplane Channel. As described in Section 3.6.2, “Board Channel capabilities,” the Board Point-to-Point Connectivity Record Link Descriptors have been updated in the Board FRU Information to include a Link Class field which indicates the signaling class required for each particular Link Descriptor. The Shelf Manager uses this Backplane and Board signaling class information to properly determine Backplane and Board capabilities and configure Boards during the E-Keying process. The role of the Shelf Manager in the E-Keying process is as defined in PICMG 3.0 Section 3.7.1, “E-Keying process,” with the following modifications.

1. After gathering the Board E-Keying entries through the IPMI “Read FRU Data” command, the Shelf Manager analyzes the value of the Backplane Channel Signaling Class Capability compared with the Board's Link Class values. Within its working copy of a Board's Link Descriptors, the Shelf Manager removes all descriptors containing a Link Class with a value greater than the Backplane Channel Signaling Class Capability for the corresponding Channel (excluding Link Class 1111b). This ensures that the E-Keying algorithm does not enable a Port based on a matching Link Descriptor with a signaling speed which the Backplane is incapable of supporting.

2. Next, if the Backplane Channel Signaling Class Capability is greater than 0000b (basic signaling class), the Shelf Manager re-orders its copy of the Board's list of Link Descriptors for the corresponding Channel by moving all of the descriptors with a Link Class value of 0000b or 1111b to the end of the Link Descriptor list. The relative order of descriptor entries within the group of descriptors having a Link Class value of 0000b or 1111b is

0100b PICMG 3.3 StarFabric Fabric Interface

0101b PICMG 3.4 PCI Express Fabric Interface


Table 3-31 Link Type (Continued)

Type Description

PICMG 3.1 R3.0, May 5, 2016 53


maintained. This results in a prioritized list of Link Descriptors for the given Channel from the highest through lowest Link Class (provided that the Link Descriptors with a Link Class other than 0000b or 1111b were already ordered as recommended by the priorities specified in Table 3-3, “Link options,” and the requirements in Section 3.5, “Link and Link Descriptor options”).

3. Finally, the Shelf Manager proceeds with the process of finding a matching Link Descriptor from the descriptor lists (as modified in steps 1 and 2 above) and issues the appropriate “Set Port State” command as defined in PICMG 3.0 Section 3.7.1, “E-Keying process.” An older Shelf Manager, which is unaware of the Backplane Channel Signaling Class Capability and Board Link Class fields, and has not performed steps 1 or 2, will parse the combined 4-bit Link Class and 4-bit Link Type, as an 8-bit Link Type. The Link Descriptor priorities defined in Table 3-3, “Link options,” enable backwards compatibility and interoperability since the basic signaling class descriptors are prioritized first and will match before any descriptors with a Link Class other than 0000b or 1111b.

Requirements

REQ 3.19 During the E-Keying process, if the Backplane Channel Signaling Class Capability value is greater than 0000b (basic signaling class), the Shelf Manager shall re-prioritize the Board's prioritized Link Descriptor list by moving all Link Descriptors for this Channel with a Link Class value of 0000b (basic signaling class) or 1111b (OEM GUID Link Class) to the end of the Board's Link Descriptor list. The order of individual Link Descriptors within multiple descriptors having a Link Class of 0000b or 1111b shall be preserved during this movement.

REQ 3.20 During the E-Keying process, the Shelf Manager shall ignore all Board Link Descriptors containing a Link Class value which exceeds the Backplane Channel Signaling Class Capability value for the Channel (except for Link Class 1111b).

3.6.4 Updated Set and Get Port State Commands

¶ 82 In conjunction with the updated Link Descriptor described in Table 3-29, “Link Descriptor,” the request data of the Set Port State Command defined in PICMG 3.0 Section 3.7.2.4, and the response data of the Get Port State command defined in PICMG 3.0 Section 3.7.2.5 is correspondingly updated as shown in Table 3-32, “Set Port State command,” and Table 3-33, “Get Port State command.” All other aspects and requirements of the Set and Get Port State Commands are unchanged.

54 PICMG 3.1 R3.0, May 5, 2016


Table 3-32 Set Port State command

Byte Data field

Request data 1PICMG Identifier. Indicates that this is a PICMG-defined group extension command. A value of 00h is used.

2:5

Link Info. LS Byte first. Describes the Link to be enabled or disabled.

[31:24] — Link Grouping ID

[23:20] — Link Type Extension

[19:16] — Link Class

[15:12] — Link Type

[11] — Port 3 Bit Flag




[07:06] — Interface

[05:00] — Channel Number

6

State. Indicates the desired state of the Link as described by Link Info.

00h = Disable

01h = Enable

All other values reserved.

Response data 1 Completion Code

2PICMG Identifier. Indicates that this is a PICMG-defined group extension command. A value of 00h is used.

PICMG 3.1 R3.0, May 5, 2016 55


Requirements

REQ 3.21 For the Set Port State command, the data format as defined in Table 3-32, “Set Port State command” shall be used.

REQ 3.22 For the Get Port State command, the data format as defined in Table 3-33, “Get Port State command” shall be used.

Table 3-33 Get Port State command

Byte Data field

Request data 1PICMG Identifier. Indicates that this is a PICMG-defined group extension command. A value of 00h is used.

2

Channel. Describes the Channel being queried.

[07:06] - Interface

[05:00] - Channel Number

Response data 1 Completion Code.

2PICMG Identifier. Indicates that this is a PICMG-defined group extension command. A value of 00h is used.

(3:6)

Link Info 1. LS Byte first. Optional. Describes information about Link one on the specified Channel. If this set of bytes is not provided, the Channel does not have any Links on the Channel.

[31:24] — Link Grouping ID

[23:20] — Link Type Extension

[19:16] — Link Class

[15:12] — Link Type

[11] - Port 3 Bit Flag




[07:06] - Interface

[05:00] - Channel Number

(7)

State 1. Must be present if Link Info 1 is present. Indicates the current state of the Port(s) on the Channel.

00h = Disabled

01h = Enabled

All other values reserved.

(8:11)Link Info 2. LS Byte first. Optional. Similar to Link Info 1. Used for cases where a second Link has been established.

(12) State 2. Similar to state 1.

(13:16)Link Info 3. LS Byte first. Optional. Similar to Link Info 1. Used for cases where a third Link has been established.


(18:21)Link Info 4. LS Byte first. Optional. Similar to Link Info 1. Used for cases where a fourth Link has been established.


56 PICMG 3.1 R3.0, May 5, 2016

Data transport

Data transport 4

4.1 Introduction

¶ 83 Each AdvancedTCA Fabric Channel provides eight differential-signal pairs that are used for Board-to-Board communication. Up to 15 Fabric Channels are provided, which are distributed according the rules detailed in Section 6 of the PICMG 3.0 specification. Each Fabric Channel uses two rows of the connectors in Zone 2, with generic pin mappings as shown in Table 4-1, “AdvancedTCA Fabric Interface generic pin mappings.”

Note: In PICMG 3.0 terminology, each set of two pairs (one pair of transmit and one pair of receive) is referred to as a “Port.” The pins with “0” in the name are part of Port 0, “1” in the name indicates Port 1, etc.

¶ 84 PICMG 3.0 Section 8 specifies the electrical characteristics of the Channels which make them usable as a medium for the Backplane Fabric Link speeds up to 3.125 Gbps. PICMG 3.1 Section 5.6, “100GBASE-KR4 Channel characteristics” specifies the electrical characteristics of the Channels up to 25.78125 Gbd:

• 1000BASE-KX Ethernet, 1000BASE-BX Ethernet or FC-PI: one Tx pair and one Rx pair to carry 1 Gbps Ethernet or Fibre Channel.

• 10GBASE-KX4, 10GBASE-BX4: four transmit pairs and four receive pairs to carry 10 Gbps Ethernet.

• 10GBASE-KR Ethernet: one Tx pair and one Rx pair to carry 10 Gbps Ethernet.

• 40GBASE-KR4: four transmit pairs and four receive pairs to carry 40 Gbps Ethernet.

• 25GBASE-KR Ethernet: one Tx pair and one Rx pair to carry 25 Gbps Ethernet.

• 100GBASE-KR4: four transmit pairs and four receive pairs to carry 100 Gbps Ethernet.

¶ 85 PICMG 3.1 supports Channel types over a Fabric Channel or Update Channel as shown in Table 4-2, “PICMG 3.1 Channel options.”

Table 4-1 AdvancedTCA Fabric Interface generic pin mappings

ZD Pin/Row # A B C D E F G H

Fabric Channel n Tx2+ Tx2- Rx2+ Rx2- Tx3+ Tx3- Rx3+ Rx3-

n + 1 Tx0+ Tx0- Rx0+ Rx0- Tx1+ Tx1- Rx1+ Rx1-

PICMG 3.1 R3.0, May 5, 2016 57

Data transport

Table 4-2 PICMG 3.1 Channel options

Option Electrical interface ProtocolChannel Ports

UsedBit rate [full

duplex]

1 1000BASE-BX Ethernet 1 1 Gbps

1-K 1000BASE-KX Ethernet 1 1 Gbps

1-KR 10GBASE-KR Ethernet 1 10 Gbps

1-K25 25GBASE-KR Ethernet 1 25 Gbps









4 1000BASE-BX

FC-PI

Ethernet

Fibre Channel

1

1

1 Gbps

2 Gbps*

4-K 1000BASE-KX

FC-PI

Ethernet

Fibre Channel

1

1

1 Gbps

2 Gbps*

4-KR 10GBASE-KR

FC-PI

Ethernet

Fibre Channel

1

1

25 Gbps

2 Gbps*

4-K25 25GBASE-KR

FC-PI

Ethernet

Fibre Channel

1

1

25 Gbps

2 Gbps*

5 1000BASE-BX

FC-PI

Ethernet

Fibre Channel

2

1

2 Gbps

2 Gbps*

5-K 1000BASE-KX

FC-PI

Ethernet

Fibre Channel

2

1

2 Gbps

2 Gbps*

5-KR 10GBASE-KR

FC-PI

Ethernet

Fibre Channel

2

1

20 Gbps

2 Gbps*

5-K25 25GBASE-KR

FC-PI

Ethernet

Fibre Channel

2

1

50 Gbps

2 Gbps*

6 1000BASE-BX

FC-PI

Ethernet

Fibre Channel

2

2

2 Gbps

4 Gbps*

6-K 1000BASE-KX

FC-PI

Ethernet

Fibre Channel

2

2

2 Gbps

4 Gbps*

6-KR 10GBASE-KR

FC-PI

Ethernet

Fibre Channel

2

2

20 Gbps

4 Gbps*

6-K25 25GBASE-KR

FC-PI

Ethernet

Fibre Channel

2

2

50 Gbps

4 Gbps*

7 FC-PI Fibre Channel 1 2 Gbps*

8 FC-PI Fibre Channel 2 4 Gbps*

58 PICMG 3.1 R3.0, May 5, 2016

Data transport

Note: *FC-PI may support 1 or 2 Gbps w/Auto-Negotiation. This table assumes 2 Gbps.

¶ 86 In the options that carry multiple Ethernet/Fibre Channel Ports, it is possible to run them as either independent Ports or as a single logically “bundled” or “aggregated” Channel comprised of “n” Ports.

4.2 Pin assignments

¶ 87 In PICMG 3.1, the pin assignments within each Fabric interface are provided in Table 4-3, “Channel Interface pin assignments for 1G, 1000BASE-KX, 10GBASE-KR, and 25GBASE-KR Ethernet Ports”, Table 4-4, “Ethernet with Fibre Channel pin assignments”, and Table 4-5, “Channel Interface pin mappings for 10GBASE-BX4, 10GBASE-KX4, 40GBASE-KR4, and 100GBASE-KR4”.

¶ 88 Table 4-3, “Channel Interface pin assignments for 1G, 1000BASE-KX, 10GBASE-KR, and 25GBASE-KR Ethernet Ports” shows the permissible pin mappings when a 1000BASE-BX, 1000BASE-KX or 10GBASE-KR Ethernet Channel is used.

¶ 89 Table 4-4, “Ethernet with Fibre Channel pin assignments” provides options for when both Ethernet and Fibre Channel are used.

9 10GBASE-BX4 XAUI 4 10 Gbps

9-K 10GBASE-KX4 Ethernet 4 10 Gbps

9-KR 40GBASE-KR4 Ethernet 4 40 Gbps

9-K25 100GBASE-KR4 Ethernet 4 100 Gbps

Table 4-2 PICMG 3.1 Channel options (Continued)

Option Electrical interface ProtocolChannel Ports

UsedBit rate [full

duplex]

Table 4-3 Channel Interface pin assignments for 1G, 1000BASE-KX, 10GBASE-KR, and 25GBASE-KR Ethernet Ports

Channel Configuration ZD Pin/

Row # AB CD EF G H

One 1000BASE-BX, 1000BASE-KX, 10GBASE-KR, or 25GBASE-KR

n NC NC Term Rx2+

Term Rx2-

NC NC Term Rx3+

Term Rx3-

n + 1 Tx0+ Tx0- Rx0+ Rx0- NC NC Term Rx1+

Term Rx1-

Two 1000BASE-BX, 1000BASE-KX, 10GBASE-KR, or25G BASE-K25

n NC NC Term Rx2+

Term Rx2-

NC NC Term Rx3+

Term Rx3-


Four 1000BASE-BX, 1000BASE-KX, 10GBASE-KR, or25G BASE-K25

n Tx2+ Tx2- Rx2+ Rx2- Tx3+ Tx3- Rx3+ Rx3-


PICMG 3.1 R3.0, May 5, 2016 59

Data transport

Note: If termination is not provided, EMI and common mode problems may occur if the transmitter at the far end of the connection is not properly disabled when the system is running.

Note: “NC” signals are no connect signals.

¶ 90 Table 4-5, “Channel Interface pin mappings for 10GBASE-BX4, 10GBASE-KX4, 40GBASE-KR4, and 100GBASE-KR4” shows the pin mappings for when a single Channel of XAUI, 10GBASE-KX4, or 40GBASE-KR4 are used.

Table 4-4 Ethernet with Fibre Channel pin assignments

Channel Configuration

ZD Pin/ Row

#

A B CD EF GH

One 1000BASE-BX, 1000BASE-KX, 10GBASE-KR, or25GBASE-KROne Fibre Channel

n NC NC Term Rx2+

Term Rx2-

FC Tx0+ FC Tx0- FC

Rx0+ FC Rx0-

n + 1 Tx0+ Tx0- Rx0+ Rx0- NC NC Term Rx1+

TermRx1-

Two 1000BASE-BX, 1000BASE-KX, 10GBASE-KR, or25GBASE-KROne Fibre Channel

n NC NC Term Rx2+

Term Rx2-

FC Tx0+ FC Tx0- FC

Rx0+ FC Rx0-


Four 1000BASE-BX, 1000BASE-KX, 10GBASE-KR, or25GBASE-KRTwo Fibre Channel

n FC Tx1+ FC Tx1- FC

Rx1+ FC Rx1- FC Tx0+ FC Tx0- FC

Rx0+ FC Rx0-


One Fibre Channel Only

n NC NC Term Rx2+

Term Rx2-

FC Tx0+ FC Tx0- FC

Rx0+ FC Rx0-

n + 1 NC NC Term Rx0+

Term Rx0- NC NC Term

Rx1+ Term Rx1-

Two Fibre Channel Only

n FC Tx1+ FC Tx1- FC

Rx1+ FC Rx1- FC Tx0+ FC Tx0- FC

Rx0+ FC Rx0-

n + 1 NC NC Term Rx0+

Term Rx0- NC NC Term

Rx1+ Term Rx1-

Table 4-5 Channel Interface pin mappings for 10GBASE-BX4, 10GBASE-KX4, 40GBASE-KR4, and 100GBASE-KR4

Channel Configu-ration

ZD Pin/ Row #

AB CD EF GH

One 10GBASE-BX4, 10GBASE-KX4,40GBASE-KR4, or100GBASE-KR4 Channel

n Tx2+ Tx2- Rx2+ Rx2- Tx3+ Tx3- Rx3+ Rx3-


60 PICMG 3.1 R3.0, May 5, 2016

Data transport

Requirements

REQ 4.1 A Zone 2 Connector may be removed from a Board if none of the Channels assigned to that connector are used by the Board.

REQ 4.2 “TermRxn” Rx signals in all Channels on a populated Zone 2 Connector shall be connected to ground through a 470 pF capacitor and a 50 Ohm resistor to reduce EMI, common mode and noise.

REQ 4.2.1 If a Zone 2 Connector is not present on the Board, the “TermRxn” signal pairs shall not be provided with the termination in REQ 4.2.

PICMG 3.1 R3.0, May 5, 2016 61

Data transport

62 PICMG 3.1 R3.0, May 5, 2016

Backplane physical layer interfaces

Backplane physical layer interfaces 5

¶ 91 PICMG 3.0 provides design guidelines for construction of Boards and Backplanes that support baud rates up to 3.125 Gbd. IEEE 802.3 provides requirements for a variety of Ethernet transceiver technologies. Together, these requirements and guidelines provide enough information to implement AdvancedTCA systems with basic signaling class (LCLASS = 0000b) Channels. Additional physical layer Channel information is provided within this section for two reasons:

1) PICMG 3.1 R1.0 defined two transceiver specifications that are not covered by IEEE standards: 1000BASE-BX and 10GBASE-BX4. Physical layer interface limits for these transceiver types are provided since they are not documented by IEEE.

2) 10GBASE-KR and 40GBASE-KR4 transceivers extend AdvancedTCA signaling rates beyond the 3.125 Gbd originally envisioned for the Channel. This section includes Channel requirements and testing methods in order to extend the signaling rate of the AdvancedTCA Channel to 10.3125 Gbd.

3) 25GBASE-KR and 100GBASE-KR4 transceivers extend AdvancedTCA signaling rates to 25.78125 Gbd, beyond the 3.125 Gbd originally envisioned for the Channel.

¶ 92 Because the PICMG 3.1 basic signaling (LCLASS = 0000b) Channel is designed to support 10 Gigabit Ethernet over 4 Ports, each Port has separate transmit and receive pairs, with each pair capable of handling 3.125 Gbd signaling rates. Each Port can transport either 1 Gbps Ethernet data or 1 Gbps Fibre Channel data. However, if Auto-Negotiation is implemented in the case of FC, the Port can support 2 Gbps.

¶ 93 1000BASE-BX is the PICMG 3.0 electrical specification for transmission of 1 Gbps Ethernet data over the Backplane. This definition was developed by PICMG because at the original release of PICMG 3.1 there were no IEEE standards for Backplane Ethernet. IEEE has since standardized 1000BASE-KX Ethernet which is to be used for all new PICMG implementations. 1000BASE-BX is included in this specification for historical and backward-compatibility reasons only.

¶ 94 10GBASE-BX4 is the PICMG 3.0 electrical specification for transmission of the 10 Gbps XAUI signaling for a Backplane environment. This definition was developed by PICMG because at the original release of PICMG 3.1 there were no IEEE standards for 10Gb Backplane Ethernet. IEEE has since standardized 10GBASE-KX4 Ethernet which is to be used for all new PICMG implementations. 10GBASE-BX4 is included in this specification for historical and backward-compatibility reasons only.

¶ 95 Both 1000BASE-BX and 10GBASE-BX4 are logically PMDs, and they are specified to require minimal logic to implement the PMD function (e.g., I/O drivers and receivers that meet PICMG 3.1 specifications).

PICMG 3.1 R3.0, May 5, 2016 63


5.1 Gigabit Backplane interface, 1000BASE-BX/FC-PI

¶ 96 This section documents requirements associated with 1000BASE-BX and FC-PI transceivers. Requirements for 10GBASE-BX4 are included in section 5.2. Other transceiver-specific requirements are captured by the relevant IEEE specifications.

¶ 97 1000BASE-BX was developed by PICMG because at the original release of PICMG 3.1 there were no IEEE standards for Backplane Ethernet. IEEE has since standardized 1000BASE-KX Ethernet which is to be used for all new PICMG implementations. 1000BASE-BX is included in this specification for historical and backward-compatibility reasons only.

¶ 98 A 1000BASE-BX/FC-PI interface between two Gigabit Ethernet/Fibre Channel Ports is shown in Figure 5-1, “SerDes 1000BASE-BX Ethernet/FC-PI Channel electrical environment.”

Figure 5-1 SerDes 1000BASE-BX Ethernet/FC-PI Channel electrical environment

64 PICMG 3.1 R3.0, May 5, 2016


5.1.1 1000BASE-BX/FC-PI transmitter electrical specifications

Figure 5-2 1000BASE-BX/FC-PI test points

¶ 99 The test points TPT and TPR are mandatory compliance points. The termination and coupling capacitors are bounded by TP1 and TP4.

¶ 100 The values for the TPT are based on the IEEE 802.3 1000BASE-CX and Fibre Channel FC-PI specifications when converted from 150 to 100 differential.

5.1.1.1 Transmitted electrical specifications at TP1

¶ 101 Parameters are identified at TPT. System implementers must account for losses and differences between TPT and TP1 to guarantee robust design at TP1.

Requirements

REQ 5.1 The impedance at the TP1 termination shall be 100 ± 10%.

5.1.1.2 Transmitted electrical specifications at TPT

¶ 102 The output driver is assumed to have output levels supporting the PICMG 3.1 test point (TPT). The test point is the Backplane side of the mated ZD connector as shown in Figure 5-3, “1000BASE-BX/FC-PI transmit test point TPT.”

PICMG 3.1 R3.0, May 5, 2016 65


Figure 5-3 1000BASE-BX/FC-PI transmit test point TPT

Note: Zone 2 Connector ground contacts are connected to Logic Ground.All traces ought to be as short as possible.

Note: *FC-PI may support 1 or 2 Gbps w/Auto-Negotiation. The table assumes 2 Gbps. All measurements are made though a mated pair connector.

¶ 103 All specifications are differential.

¶ 104 TDR measurements are recorded times. Recorded time = TDR Transit time * 2.

5.1.1.3 Transmitted eye mask at TPT

¶ 105 The eye diagram is measured only with high-frequency jitter components that are not tracked by the clock recovery circuit and the lower cutoff frequency for jitter is 637 kHz.

Table 5-1 1000BASE-BX/FC-PI transmitter specifications at TPT

DescriptionValue

Units1000BASE-BX FC-PI

Data rate 1000 800* Mbps

Nominal signaling speed 1250 1062.5* Mbd

Clock tolerance ±100 ppm

Differential output amplitude (p-p) 1350 - 750 mV

Return loss 15 dB

Impedance at connection (TPT) 100 ± 30

Impedance at termination (TP1) 100 ± 10

66 PICMG 3.1 R3.0, May 5, 2016


Figure 5-4 1000BASE-BX/FC-PI absolute eye diagram mask at TPT

Requirements

REQ 5.2 The transmitter shall meet the specifications at TPT as specified in Table 5-1, “1000BASE-BX/FC-PI transmitter specifications at TPT,” Table 5-4, “1000BASE-BX/FC-PI absolute eye diagram mask at TPT,” and Table 5-2, “1000BASE-BX/FC-PI transmitter specifications at TPT.”

REQ 5.3 To maintain interoperability between older and newer technologies and to avoid damage to the components, the maximum drive amplitude of any PICMG 3.1 driver shall not exceed 1600 mVp-p.

Table 5-2 1000BASE-BX/FC-PI transmitter specifications at TPT

Symbol Value Units

X1 0.14 Unit intervals (UI)

X2 0.34 Unit intervals (UI)

PICMG 3.1 R3.0, May 5, 2016 67


5.1.2 1000BASE-BX/FC-PI receiver electrical specifications

5.1.2.1 Receiver electrical specifications at TPR

Figure 5-5 1000BASE-BX/FC-PI receive test point TPR

Note: Zone 2 Connector ground contacts are connected to Logic Ground.All traces ought to be as short as possible.

68 PICMG 3.1 R3.0, May 5, 2016


¶ 106 All specifications are differential.

¶ 107 TDR measurements are recorded times. Recorded time = TDR Transit time * 2.

¶ 108 The connection impedance describes the impedance tolerance through a mated connector. This tolerance is greater than the termination or Backplane impedance due to limits in the connector technology.

5.1.2.2 Received eye mask at TPR

¶ 109 Eye diagrams are measured only with high-frequency jitter components that are not tracked by the clock recovery circuit and the lower cutoff frequency for jitter is 637 kHz.

Table 5-3 1000BASE-BX/FC-PI receiver specifications at TPR

DescriptionValue

Units1000BASE-BX FC-PI

Data rate 1000 1600* Mbps

Nominal signaling speed 1250 2125* Mbd

Clock tolerance ± 100 ppm

Sensitivity (p-p) 1350 - 200 mV

Differential skew 175 ps

Differential return loss 15 dB

Common mode return loss 6 dB

Input impedance, each signal to ground with a 50 Ohm resistor

• TDR rise time TPR 85 ps

• At connection TPR 100 ± 30 W

• At termination TP4 100 ± 10

PICMG 3.1 R3.0, May 5, 2016 69


Figure 5-6 1000BASE-BX/FC-PI received eye mask at TPR

¶ 110 The minimum input amplitude to the receiver listed in Table 5-4, “1000BASE-BX/FC-PI jitter budget,” and Figure 5-6, “1000BASE-BX/FC-PI received eye mask at TPR” is a worst case specification across all environmental conditions. Restricted environments can allow operation at lower minimum differential voltages, allowing significantly longer operating distances.

70 PICMG 3.1 R3.0, May 5, 2016


Requirements

REQ 5.4 The receiver shall be AC-coupled to the media through a receive network.

REQ 5.5 The receive network shall terminate the TxRx connection by an equivalent impedance of 100 , as specified in Figure 5-5, “1000BASE-BX/FC-PI receive test point TPR.”

REQ 5.6 The receiver shall operate within the BER objective (10-12

) when a signal with valid voltage and timing specifications is delivered to the interoperability point from a balanced 100 source.

REQ 5.7 The delivered signal shall be considered valid if it meets the voltage and timing limits specified in Figure 5-6, “1000BASE-BX/FC-PI received eye mask at TPR,” Table 5-3, “1000BASE-BX/FC-PI receiver specifications at TPR,” and Table 5-4, “1000BASE-BX/FC-PI jitter budget,” when measured across a load equivalent to those of Figure 5-5, “1000BASE-BX/FC-PI receive test point TPR.”

REQ 5.8 Receiver input impedance shall result in a differential return loss better than 15 dB and a common mode return loss better than 6 dB from 100 MHz to 2.5 GHz. This includes contributions from all components related to the receiver including coupling components. The return loss reference impedance is 100 for differential return loss and 25 for common mode.

REQ 5.9 To verify compliance with the received eye mask at TPR, all Channels, transmit and receive, should be active in order to include the effects of crosstalk.

5.1.2.3 Receiver electrical specifications at TP4

¶ 111 Parameters are identified at TPR. System implementers must account for losses and differences between TPR and TP4 to guarantee robust design at TP4.

Requirements

REQ 5.10 The AC coupling capacitors at the receiver shall be no more than 10 nF +/-10%. Each signal is measured to ground with a 50 Ohm resistor.

5.1.3 1000BASE-BX/FC-PI jitter specifications

¶ 112 Normative values are highlighted in bold. The deterministic jitter budgetary specifications are shown in Table 5-4, “1000BASE-BX/FC-PI jitter budget” only for informational purposes to assist implementers in specifying components. Compliance points are TPT and TPR as defined in Figure 5-3, “1000BASE-BX/FC-PI transmit test point TPT,” and Figure 5-5, “1000BASE-BX/FC-PI receive test point TPR.”

¶ 113 Deterministic jitter budgetary specifications are included here to assist implementers in specifying components.

PICMG 3.1 R3.0, May 5, 2016 71


Note: *Total jitter is composed of both deterministic and random components. The allowed random jitter equals the allowed total jitter minus the actual deterministic jitter at that point.

Requirement

REQ 5.11 The PICMG 3.1 1000BASE-BX/FC-PI transciever shall meet the total jitter specifications defined in Table 5-4, “1000BASE-BX/FC-PI jitter budget.”

5.2 10 Gigabit Backplane interface, 10GBASE-BX4

¶ 114 This section documents requirements associated with 10GBASE-BX4 transceivers. Requirements for 1000BASE-BX are included in section 5.1. Other transceiver-specific requirements are captured by the relevant IEEE specifications.

¶ 115 10GBASE-BX4 was developed by PICMG because at the original release of PICMG 3.1 there were no IEEE standards for Backplane Ethernet. IEEE has since standardized 10GBASE-KX4 Ethernet which is to be used for all new PICMG implementations. 10GBASE-BX4 is included in this specification for historical and backward-compatibility reasons only.

¶ 116 10 Gigabit Ethernet is supported within PICMG 3.1 by adopting a subset of the IEEE 802.3 XAUI specifications. Where XAUI is a chip to chip interface between the test points TP1 and TP4, PICMG 3.1 specifies what goes into the Backplane at TPT and what comes out of the Backplane at TPR.

¶ 117 A 10GBASE-BX4 interface between two 10 Gigabit Ethernet Ports is shown in Figure 5-7, “10GBASE-BX4 electrical environment.”

¶ 118 The Channel to Channel skew is handled by the XAUI protocol and is not specified in this document.

Table 5-4 1000BASE-BX/FC-PI jitter budget

Compliance point Total jitter* Deterministic jitter

UI ps UI ps

TPT 0.28 223 0.14 112

TPR 0.66 528 0.4 320

72 PICMG 3.1 R3.0, May 5, 2016


Figure 5-7 10GBASE-BX4 electrical environment

¶ 119 The test points TPT and TPR are mandatory compliance points.

¶ 120 The test points TP1 and TP4 are informative and based on the IEEE 802.3ae XAUI electrical specifications as defined in clause 47.3.

Requirement

REQ 5.12 When implementing a 10GBASE-BX4 Channel, Board designers shall implement this Channel with compliant TPT and TPR test points.

5.2.1 10GBASE-BX4 transmitter electrical specifications

5.2.1.1 Transmitted electrical specifications at TP1

¶ 121 PICMG 3.1 specifies the compliance point TPT. The system implementer is required to implement additional margin at TP1 to ensure compliance at TPT.

Requirement

REQ 5.13 The impedance at termination shall be 100 ± 10%.

PICMG 3.1 R3.0, May 5, 2016 73


5.2.1.2 Transmitted electrical specifications at TPT

Note: All measurements are made though a mated pair connector

¶ 122 The output impedance requirement applies to all valid output levels. The reference impedance for differential return loss measurements is 100 .

Equation 1.

s11 = –10 dB for 312.5 MHz < Freq (f) < 625 MHz, and –10 + 10log(f/625) dB for 625 MHz <= Freq (f) = < 3.125 GHz where f is frequency in MHz.

Requirements

REQ 5.14 The PICMG 3.1 drive levels into the Backplane shall conform to the specifications as summarized in Table 5-5, “10GBASE-BX4 transmit specifications at TPT.”

REQ 5.15 To maintain inter-operability between older and newer technologies and to avoid damage to the components, the maximum drive amplitude of any PICMG 3.1 driver shall not exceed 1600 mVp-p.

5.2.1.3 Compliance interconnect definition

¶ 123 The compliance interconnect is a 100 differential system specified with respect to transmission magnitude response and inter-symbol interference (ISI) loss. The compliance interconnect limits have been chosen to allow a realistic differential interconnect of about 50 cm length on FR4 epoxy. The transmission magnitude response, |s21|, of the compliance interconnect in dB satisfies Equation 2.

Table 5-5 10GBASE-BX4 transmit specifications at TPT

Parameter Value Units

Baud rate 3.125 Gbd


Differential amplitude maximum 1600 mVp-p

Absolute output voltage limits -0.4min, 1.6 max V

Differential output return loss (see: Equation 1) dB

Output jitter

Near-end maximums (TPT)

• Total jitter ± 0.175 peak from the mean UI

• Deterministic jitter ± 0.085 peak from the mean UI

74 PICMG 3.1 R3.0, May 5, 2016


Equation 2.

wheree is Euler’s constantf is the frequency in Hz,

¶ 124 This limit applies from DC to 3.125 GHz. The magnitude response above 3.125 GHz does not exceed –11.4 dB. The ISI loss, defined as the difference in magnitude response between two frequencies, is greater than 4.0 dB between 312.5 MHz and 1.5625 GHz. The magnitude response and ISI loss limits are illustrated in Figure 5-8, “10GBASE-BX4 compliant interconnect magnitude response and ISI loss.”

Figure 5-8 10GBASE-BX4 compliant interconnect magnitude response and ISI loss

5.2.2 10GBASE-BX4 receiver electrical specifications

Requirements

REQ 5.16 A PICMG 3.1 receiver shall be AC coupled at or on the receiver chip.

REQ 5.17 The receiver shall operate with a BER of better than 10-12

with any valid input signal as defined at TPR. Each signal is measured to ground with a 50 Ohm resistor.

PICMG 3.1 R3.0, May 5, 2016 75


5.2.2.1 Receiver electrical specifications at TPR

Requirements

REQ 5.18 The input signals shall comply to the eye mask defined in Figure 5-9, “10GBASE-BX4 TPT and TPR eye mask,” and Table 5-6, “10GBASE-BX4 receiver specifications at TPR.”

REQ 5.19 Receiver input impedance shall result in a differential return loss better than 10 dB and a common mode return loss better than 6 dB from 100 MHz to 2.5 GHz.

¶ 125 This includes contributions from all components related to the receiver including coupling components. The return loss reference impedance is 100 for differential return loss and 25 for common mode.

5.2.2.2 Receiver electrical specifications at TP4

¶ 126 PICMG 3.1 specifies the compliance point TPR. The system implementer is required to ensure the additional losses to TP4 are accounted for.

Requirements

REQ 5.20 The AC coupling capacitors at the receiver shall be no more than 470 pF +1% and matched within 2% to each other.

5.2.3 10GBASE-BX4 TPT and TPR eye mask

¶ 127 The eye masks are given in Figure 5-9, “10GBASE-BX4 TPT and TPR eye mask.” The eye mask measurement requirements are specified in IEEE 802.3ae clause 47.4.2. The jitter requirements at TPT are for a maximum total jitter of ± 0.175 UI peak.

Table 5-6 10GBASE-BX4 receiver specifications at TPR

Parameter Value Units

Baud rate 3.125 Gbd


Differential return loss 10 dB

Common mode return loss 6 dB

Jitter amplitude tolerance (p-p) 0.65 UI

Differential skew 75 ps

76 PICMG 3.1 R3.0, May 5, 2016


Figure 5-9 10GBASE-BX4 TPT and TPR eye mask

Requirements

REQ 5.21 The driver shall satisfy either the TPT (near-end) eye mask, or the TPR eye mask.

5.3 1000BASE-KX and 10GBASE-KX4 specifications

¶ 128 Transceiver requirements for 1000BASE-KX and 10GBASE-KX4 are covered by IEEE 802.3 and the Channel requirements are covered by PICMG 3.0.

Requirements

REQ 5.22 1000BASE-KX transceivers shall comply to all requirements in IEEE 802.3-2008 for 1000BASE-KX transceivers.

REQ 5.23 10GBASE-KX4 transceivers shall comply to all requirements in IEEE 802.3-2008 for 10GBASE-KX4 transceivers.

5.4 10GBASE-KR and 40GBASE-KR4 Channel characteristics

¶ 129 This section introduces physical layer Channel requirements to implement a 10.3125 Gbd Channel (LCLASS 0011b). Requirements are given for both Front Boards that implement 10GBASE-KR and 40GBASE-KR4 transceivers, and Backplanes that are intended to support these higher speed Boards.

¶ 130 Since 10.3125 Gbd signaling is a significant departure from the basic signaling class defined in PICMG 3.0, this section also includes information about test methodology and measurement calculations used to validate the Channel. Measurement calculations are given in section 5.4.1.

PICMG 3.1 R3.0, May 5, 2016 77


¶ 131 Three test fixtures (or their equivalent) are required to make these measurements. Parameters for the test fixtures are tightly defined and their requirements are given in sections 5.4.2 through 5.4.4.

¶ 132 Requirements for Front Boards are given in Section 5.4.5 and Backplane requirements are found in section 5.4.6.

¶ 133 Information contained in this section of PICMG 3.1 adopts nomenclature consistent with the IEEE 802.3 standard to facilitate better understanding of both documents.

¶ 134 Figure 5-10, “Test point locations for LCLASS 0011b Channels” shows the test point locations for the endpoints of PICMG 3.1 10GBASE-KR and 40GBASE-KR4 Channels. Direct measurement between these points for all combinations of Boards and Backplanes is infeasible; however, utilizing the requirements and test methods within this chapter will ensure that any combination of Boards/Backplane will result in a Channel that closely resembles the reference Channel found in IEEE 802.3 Annex 69b.

Figure 5-10 Test point locations for LCLASS 0011b Channels

¶ 135 The locations of each of the test points are described in Table 5-7, “Description of LCLASS 0011b Channel test points.”

Table 5-7 Description of LCLASS 0011b Channel test points

Test Point Description

TP0 A test point on the transmitter Board that is at the transmit function. If AC coupling capacitors are required, they are included with the transmit function. The transmit device PCB footprint is also included with the transmit function. TP0 might not be testable in an implemented system.

TP5 A test point on the receiver Board that is at the receive function. If AC coupling capacitors are required, they are included with the receive function. The receiver device PCB footprint is also included with the receive function. TP5 might not be testable in an implemented system.

TP0 to TP5 The complete LCLASS 0011b Channel.

78 PICMG 3.1 R3.0, May 5, 2016


5.4.1 Definitions of measurements and calculations (informative)

¶ 136 This section defines a number of calculations used to validate PICMG 3.1-compliant Channels that are intended to support IEEE 10GBASE-KR and 40GBASE-KR4 signaling. Most of these equations are identical to those found in IEEE 802.3-2008. IEEE 802.3-2008 equation numbers have been given for ease of cross-reference.

5.4.1.1 Fitted attenuation

¶ 137 The fitted attenuation A, is the least mean squares line fit to the insertion loss computed over the frequency range 1.0GHz to 6.0GHz. If the magnitude response of insertion loss (IL) is measured at N uniformly-spaced frequencies fn, A may be computed using the following equations:

Equation 3. (IEEE 802.3-2008 69B-1)

Equation 4. (IEEE 802.3-2008 69B-2)

Equation 5. (IEEE 802.3-2008 69B-3)

Equation 6. (IEEE 802.3-2008 69B-4)

Equation 7. (IEEE 802.3-2008 69B-5)

¶ 138 These calculations are consistent with IEE 802.3-2008 section 69B.4.2.

5.4.1.2 Insertion loss deviation (ILD)

¶ 139 Insertion loss deviation (ILD) is the difference between the insertion loss and the fitted attenuation. It is defined in Equation 8:

favg1N---- fn

n=

ILavg1N---- IL fn

n=

mA

fn favg– IL fn ILavg– n

fn favg– 2

n

-----------------------------------------------------------------------=

bA ILavg mAfavg–=

A f mAf bA+=

PICMG 3.1 R3.0, May 5, 2016 79


Equation 8. (IEEE 802.3-2008 69B-9)

¶ 140 Where IL(f) is the measured insertion loss of the Channel at each frequency, f, and A(f) is the fitted attenuation of the Channel computed by Equation 3 through Equation 7.

¶ 141 This calculation is consistent with IEEE 802.3-2008 section 69B.4.4.

5.4.1.3 Power sum differential near-end crosstalk (PSNEXT)

¶ 142 The power-sum differential near-end crosstalk is calculated as the power sum of the individual near-end crosstalk (NEXT) aggressors. PSNEXT is computed as shown in Equation 9, where NEXTn is the crosstalk loss in dB of aggressor n and N is the total number of aggressors.

Equation 9. (IEEE 802.3-2008 69B-15)

¶ 143 This calculation is consistent with IEEE 802.3-2008 section 69B.4.6.1.

5.4.1.4 Power sum differential far-end crosstalk (PSFEXT)

¶ 144 The power-sum differential far-end crosstalk is calculated as the power sum of the individual far-end crosstalk (FEXT) aggressors. PSFEXT is computed as shown in Equation 10 where FEXTn is the crosstalk loss in dB of aggressor n and N is the total number of aggressors.

Equation 10. (IEEE 802.3-2008 69B-16)


5.4.1.5 Power sum differential crosstalk (PEXT)

¶ 146 The power sum differential crosstalk (PEXT) is the power sum of the individual NEXT and FEXT aggressors. PEXT is computed as follows where PSNEXT(f) is calculated by Equation 9 and PSFEXT(f) is calculated by Equation 10:

Equation 11. (IEEE 802.3-2008 69B-17)


ILD f IL f A f –=

PSNEXT f 10log10 10 NEXTn f – 10

n

N

–=

PSFEXT f 10log10 10 FEXTn f – 10

n

N

–=

PSXT f 10log10 10 PSNEXT f – 10 10 PSFEXT f – 10+ –=

80 PICMG 3.1 R3.0, May 5, 2016


5.4.1.6 Insertion loss to crosstalk ratio (ICR) and fitted ICR

¶ 148 Insertion loss to crosstalk ratio (ICR) is the ratio of the insertion loss to the total crosstalk. ICR at each frequency f may be computed from the insertion loss (IL), and the power sum differential crosstalk (PSXT) in Equation 12:

Equation 12. (IEEE 802.3-2008 69B-18)

¶ 149 Where PSXT(f) is computed using Equation 11.

¶ 150 The fitted insertion loss to crosstalk ratio ICRfit is the least mean squares log-linear fit to the ICR computed over the frequency range 100 MHz to 5.1625 GHz. If ICR is computed at N uniformly-spaced frequencies fn, ICRfit can be computed using following equations:

Equation 13. (IEEE 802.3-2008 69B-19)

Equation 14. (IEEE 802.3-2008 69B-20)

Equation 15. (IEEE 802.3-2008 69B-21)

Equation 16. (IEEE 802.3-2008 69B-22)

Equation 17. (IEEE 802.3-2008 69B-23)

¶ 151 The calculation of ICR and ICRfit is consistent with IEEE 802.3-2008 section 69B.4.6.4.

5.4.2 Backplane test assembly characteristics

¶ 152 The PICMG 3.1 10GBASE-KR and 40GBASE-KR4 Backplane test assembly is used in conjunction with a Backplane test paddle card in order to perform validation of PICMG 3.1-compliant Boards. The purpose of the Backplane test assembly is to provide a reference

ICR f IL f – PSXT f +=

xavg1N---- log10 fn

n=

ICRavg1N---- ICR fn

n=

mICR

log10 fn xavg– ICR fn ICRavg– n

log10 fn xavg– 2

n

---------------------------------------------------------------------------------------------------=

bICR ICRavg mICRxavg–=

ICRfit f( ) mICRlog10 f bICR+=

PICMG 3.1 R3.0, May 5, 2016 81


Backplane segment with tightly controlled characteristics with which Front Board tests can be made. The Backplane test assembly is intended to capture the worst-case conditions that can be encountered with a compliant Backplane.

¶ 153 The Backplane test assembly contains two ADF Backplane connectors connected by differential signals. Some representative Backplane test assemblies are shown in Figure 5-11, “Examples of long and short Backplane test assemblies.”

Figure 5-11 Examples of long and short Backplane test assemblies

¶ 154 Since the length of the Backplane signal paths within a PICMG 3.1 Shelf can vary significantly, two length variations of the Backplane test assembly are defined: long and short. These two lengths are intended to capture both the longest signal path and shortest signal path that a Board can encounter in a PICMG 3.1-compliant environment.

¶ 155 Due to the high speed nature of 10GBASE-KR and 40GBASE-KR4 signals, industry best practices will need to be applied to the implementation of the Backplane test assembly. In particular, care will need to be taken to minimize the number of vias and length of via stubs in order to meet the requirements outlined in this section.

¶ 156 In order to avoid over-specification and promote vendor differentiation, the majority of the Backplane test assembly requirements are given as electrical values. Exact implementation, including mechanical and material options, is not dictated by this specification.

¶ 157 Figure 5-12, “Test point locations for validation of the Backplane test assembly” shows the defined test point locations used for the Backplane test assembly. The test points are described in Table 5-8, “Description of the Backplane test assembly test points.” Unless otherwise specified, all Backplane test assemblies are defined between TPC and TPD.

82 PICMG 3.1 R3.0, May 5, 2016


Figure 5-12 Test point locations for validation of the Backplane test assembly

5.4.2.1 Backplane test assembly common requirements

¶ 158 This section contains requirements that are common to both the long Backplane test assembly and the short Backplane test assembly. Specific requirements for each of these variants are contained in the following sections.

Requirements

REQ 5.24 The differential impedance of the Backplane test assembly shall be 100 Ohms +/- 10 Ohms.

REQ 5.25 The Backplane test assembly shall allow for a standard PICMG 3.0 Board to be physically inserted without modifying the Board.

REQ 5.26 The Backplane test assembly shall terminate at ADF Backplane connectors at either end of the card.

REQ 5.27 The Backplane test assembly shall implement the manufacturer’s recommended footprint for the ADF Backplane connectors.

REQ 5.28 The Backplane test assembly shall include at least three wafers of differential signals at each ADF connector for a total of at least 12 differential pairs of signal connections.

REQ 5.28.1 The differential signal pairs for the Backplane test assembly shall reside on adjacent wafers.

Table 5-8 Description of the Backplane test assembly test points


TPC The interface plane between the top surface of the Backplane and the transmit ADF connector.

TPD The interface plane between the top surface of the Backplane and the receive ADF connector.

TPC to TPD The Backplane Test Assembly Channel segment defined by PICMG 3.1. The ADF connectors are not included in this Channel segment.

PICMG 3.1 R3.0, May 5, 2016 83


REQ 5.29 The Backplane test assembly shall connect transmit signals on one ADF Backplane connector (rows ab and ef) to the corresponding receive pins (row cd and gh) on the other ADF Backplane connector (crossover connection).

REQ 5.30 In order to meet the stringent skew requirements of 10GBASE-KR and 40GBASE-KR4, Backplane test assembly differential skew shall be less than 6 ps. This figure includes signal path length, manufacturing and materials variations.

REQ 5.30.1 Compliance to REQ 5.30 might be difficult to establish by direct measurement. Suppliers shall ensure REQ 5.30 is met by design.

REQ 5.31 Backplane test assembly signal paths shall have no vias except those terminating at the connectors.

5.4.2.2 Short Backplane test assembly requirements

¶ 159 Requirements in this section apply specifically to the short implementation of the Backplane test assembly. Requirements for the long version of the Backplane test assembly are included in the next section.

5.4.2.2.1 Fitted attenuation

¶ 160 The fitted attenuation for each signal path within the short Backplane test assembly with connectors removed is defined by Equation 18 and Equation 19.

Equation 18.

For 1.0 GHz < f < 6.0 GHz (where f is expressed in Hz)

Note: The upper and lower frequency limits for Amin are derived from IEEE 802.3-2008 Table 69B-1.

Equation 19.


Note: The upper and lower frequency limits for Amax are derived from IEEE 802.3-2008 Table 69B-1..

Note: This limit was derived through simulation of 4” (101mm) of 6 mil trace width x 8 mil edge-to-edge spacing through Nelco 4000-13 material. The actual implementation can vary so long as all requirements are met.

¶ 161 The fitted attenuation limits for the short Backplane test assembly are shown in Figure 5-13, “Fitted attenuation limits for short Backplane test assembly.”

A f Amin f( ) 6.3310–10 f 0.865–=

A f Amax f( ) 7.4810–10 f 0.454+=

84 PICMG 3.1 R3.0, May 5, 2016


Figure 5-13 Fitted attenuation limits for short Backplane test assembly

Requirement

REQ 5.32 The fitted attenuation for each signal path within the short Backplane test assembly with connectors removed shall meet the limits Amin and Amax as defined by Equation 18 and Equation 19.

5.4.2.2.2 Insertion loss deviation

¶ 162 The insertion loss deviation (ILD) response for each signal path within the short Backplane test assembly with connectors removed is defined by Equation 20 and Equation 21.

Equation 20.


Note: The upper and lower frequency limits for ILDmax+ are derived from IEEE 802.3-2008 Table 69B-1.

Equation 21.


Note: The upper and lower frequency limits for ILDmax- are derived from IEEE 802.3-2008 Table 69B-1.


ILD f ILDmax+ f( ) 3.5010–10 f 0.150+=

ILD f ILDmax- f( ) 3.50–10–10 f 0.150–=

PICMG 3.1 R3.0, May 5, 2016 85


¶ 163 The peaks of the insertion loss deviation (ILD) response for each signal path within the short Backplane test assembly with connectors removed is defined by Equation 22 and Equation 23.

Equation 22.


Note: The upper frequency limit for ILDmin+ are derived from IEEE 802.3-2008 Table 69B-1. The lower frequency limit is set at the point where ILDmin+(f)=0.

Equation 23.


Note: The upper frequency limit for ILDmin- are derived from IEEE 802.3-2008 Table 69B-1. The lower frequency limit is set at the point where ILDmin-(f)=0

Note: It is expected that the insertion loss deviation response will pass through this limit region. The requirement only applies to the peaks of the insertion loss deviation response.


¶ 164 The minimum and maximum ILD limits for the short Backplane test assembly are shown in Figure 5-14, “Insertion loss deviation limits for short Backplane test assembly.”

Figure 5-14 Insertion loss deviation limits for short Backplane test assembly

ILD f ILDmin+ f( ) 2.2210–10 f 0.833–=

ILD f ILDmin- f( ) 2.22–10–10 f 0.833+=

86 PICMG 3.1 R3.0, May 5, 2016


Requirements

REQ 5.33 The insertion loss deviation (ILD) response for each signal path within the short Backplane test assembly with connectors removed shall fall between the worst-case insertion loss deviation limits, ILDmax+ and ILDmax-, as defined by Equation 20 and Equation 21.

REQ 5.34 The peaks of the insertion loss deviation (ILD) response for each signal path within the short Backplane test assembly with connectors removed shall not fall between the worst-case insertion loss deviation limits, ILDmin+ and ILDmin-, as defined by Equation 22 and Equation 23.

5.4.2.2.3 Insertion loss to crosstalk ratio

¶ 165 The worst case insertion loss to crosstalk ratio (ICR) within the short Backplane test assembly with connectors removed is defined by Equation 24 and Equation 25.

Equation 24.

For 500 MHz < f < 5.1625 GHz (where f is expressed in Hz)

Equation 25.


Note: The upper frequency limit is derived from IEEE 802.3-2008 Table 69B-1. The lower frequency limit was selected for PICMG 3.1 because it was felt that the IEEE lower frequency limits were too stringent.


¶ 166 The ICR limits are shown in Figure 5-15, “Insertion loss to crosstalk ratio limits for short Backplane test assembly.”

ICR f ICRmax f( ) 20.259 log10 f – 235.0+=

ICR f ICRmin f( ) 20.141 log10 f – 231.38+=

PICMG 3.1 R3.0, May 5, 2016 87


Figure 5-15 Insertion loss to crosstalk ratio limits for short Backplane test assembly

Requirements

REQ 5.35 The worst case insertion loss to crosstalk ratio (ICR) within the short Backplane test assembly with connectors removed shall meet the insertion loss to crosstalk ratio limits, ICRmax and ICRmin, as defined by Equation 24 and Equation 25.

5.4.2.3 Long Backplane test assembly requirements

¶ 167 The requirements in this section apply specifically to the long version of the Backplane test assembly. General requirements for the Backplane test assembly and specific requirements for the short version of the Backplane test assembly are included in the previous sections.


¶ 168 The fitted attenuation for each signal path within the long Backplane test assembly with the connectors removed is defined by Equation 26 and Equation 27.

Equation 26.


Equation 27.


Note: The upper and lower frequency limits are derived from IEEE 802.3-2008 Table 69B-1.

A f Amin f( ) 1.349–10 f 0.686+=

A f Amax f( ) 1.819–10 f 1.96+=

88 PICMG 3.1 R3.0, May 5, 2016



¶ 169 The fitted attenuation limits for the long Backplane test assembly are shown in Figure 5-16, “Fitted attenuation limits for long Backplane test assembly.”

Figure 5-16 Fitted attenuation limits for long Backplane test assembly

Requirements

REQ 5.36 The fitted attenuation for each signal path within the long Backplane test assembly with the connectors removed shall meet the limits Amax and Amin as defined by Equation 26 and Equation 27.


¶ 170 The insertion loss deviation (ILD) response for each signal path within the long Backplane test assembly with connectors is defined by Equation 28 and Equation 29.

Equation 28.


Equation 29.



ILD f ILDmax+ f( ) 5.011–10 f 0.95+=

ILD f ILDmax- f( ) 5.0–11–10 f 0.95–=

PICMG 3.1 R3.0, May 5, 2016 89


¶ 171 The maximum ILD limits for the long Backplane test assembly are shown in the Figure 5-17, “Insertion loss deviation limits for long Backplane test assembly.”

Figure 5-17 Insertion loss deviation limits for long Backplane test assembly

Requirements

REQ 5.37 The insertion loss deviation (ILD) response for each signal path within the long Backplane test assembly with connectors removed shall fall between the worst-case insertion loss deviation limits, ILDmax+ and ILDmax-, as defined by Equation 28 and Equation 29.


¶ 172 The worst case insertion loss to crosstalk ratio (ICR) within the long Backplane test assembly with connectors removed is defined by Equation 30 and Equation 31.

Equation 30.


Equation 31.






90 PICMG 3.1 R3.0, May 5, 2016


¶ 173 The ICR limits are shown in Figure 5-18, “Insertion loss to crosstalk ratio for long Backplane test assembly.”

Figure 5-18 Insertion loss to crosstalk ratio for long Backplane test assembly

Requirements

REQ 5.38 The long Backplane test assembly shall include an additional 14 ADF Backplane connector footprints evenly spaced along the length of the assembly in order to replicate the effects of additional Slots in a real Backplane. Actual connectors need not be populated.

REQ 5.39 Through-holes in the additional footprints shall be grounded.

REQ 5.40 The worst case insertion loss to crosstalk ratio (ICR) within the long Backplane test assembly with connectors removed shall meet the insertion loss to crosstalk ratio limits, ICRmax and ICRmin, as defined by Equation 30 and Equation 31.

5.4.3 Front Board test card requirements

¶ 174 The PICMG 3.1 10GBASE-KR and 40GBASE-KR4 Front Board test card is used to perform S-parameter and crosstalk validation of PICMG 3.1-compliant Front Boards. The Front Board test card contains one ADF Backplane connector that is fanned out to test points. The Front Board test card provides a controlled reference by which Front Board Channel measurements can be made. Provisions must also be made to power the unit under test. How this is accomplished is not covered by this specification.

¶ 175 A representative Front Board test card is shown in Figure 5-19, “Example Front Board test assembly.” An optimal implementation would allow Front Boards to be tested without having to alter the Front Board. Although RP-SMA connectors are shown in this figure, the actual connector/probe point design is not dictated by this specification.

PICMG 3.1 R3.0, May 5, 2016 91


Figure 5-19 Example Front Board test assembly

¶ 176 Due to the high speed nature of 10GBASE-KR and 40GBASE-KR4 signals, industry best practices will need to be applied to the implementation of the Front Board test card. In particular, care will need to be taken to minimize the number of vias and length of via stubs in order to meet the requirements outlined in this section.

¶ 177 In order to avoid over-specification and promote vendor differentiation, the majority of the Front Board test card requirements are given as electrical values. Exact implementation, including mechanical and material options, is not dictated by this specification.

¶ 178 Figure 5-20, “Test point locations for Front Board test card” shows the defined test point locations used for the Front Board test card. The test points are described in Table 5-9, “Description of Front Board test card test points.” Unless otherwise specified, all Front Board test cards are defined between TP2 or TP3 to TPA.

92 PICMG 3.1 R3.0, May 5, 2016


Figure 5-20 Test point locations for Front Board test card

Requirements

REQ 5.41 The differential impedance of the Front Board test card shall be 100 Ohms +/- 5 Ohms.

REQ 5.42 The Front Board test card shall terminate at an ADF Backplane connector at one end of the signal paths.

REQ 5.43 The Front Board test card shall implement the manufacturer’s recommended footprint for the ADF Backplane connector.

REQ 5.44 The Front Board test assembly shall include at least two wafers of differential signals to the ADF connector for a total of at least 8 differential pairs of signal connections.

REQ 5.44.1 The differential signal pairs for the Front Board test card shall reside on adjacent wafers.

REQ 5.45 In order to meet the stringent skew requirements of 10GBASE-KR and 40GBASE-KR4, Front Board test card differential skew shall be less than 6 ps. This figure includes signal path length, manufacturing and materials variations.

REQ 5.45.1 Compliance to REQ 5.45 might be difficult to establish by direct measurement. For this reason, suppliers shall ensure REQ 5.45 is met by design.

REQ 5.46 Front Board test card signal paths shall have no vias except those terminating at the connectors.

Table 5-9 Description of Front Board test card test points


TP2/TP3A test point located between the SMA (or equivalent) connector and the test equipment. TP2 refers to transmit connections, TP3 corresponds to receive.

TPAA test point located between the top surface of the Front Board test card PCB at the ADF connector via and the test equipment cabling.

TP2/TP3 to TPAThe Front Board test card test Channel segment defined by PICMG 3.1. This Channel segment extends from the SMA (or equivalent connectors) through to the ADF connector vias. The ADF connector is not included in this Channel segment.

PICMG 3.1 R3.0, May 5, 2016 93



¶ 179 The fitted attenuation for each signal path within the Front Board test card with connectors removed is defined by Equation 32 and Equation 33.

Equation 32.


Equation 33.



Note: This limit was derived through simulation of 4.5” (114.3mm) of 6 mil trace width x 8 mil edge-to-edge spacing through Nelco 4000-13 material. The actual implementation can vary so long as all requirements are met.

¶ 180 The fitted attenuation limits for the Front Board test card are shown in Figure 5-21, “Fitted attenuation limits for the Front Board test card.”

Figure 5-21 Fitted attenuation limits for the Front Board test card

Requirements

REQ 5.47 The fitted attenuation for each signal path within the Front Board test card with connectors removed shall meet the limits Amin and Amax as defined by Equation 32 and Equation 33.

A f Amin f( ) 5.9110–10 f 0.18–=

A f Amax f( ) 6.6710–10 f 0.93+=

94 PICMG 3.1 R3.0, May 5, 2016



¶ 181 The insertion loss deviation (ILD) response for each signal path within the Front Board test card with connectors removed is defined by Equation 34 and Equation 35.

Equation 34.


Equation 35.


Note: The upper frequency and lower frequency limits are derived from IEEE 802.3-2008 Table 69B-1.


¶ 182 The maximum ILD limits for the Front Board test card are shown in Figure 5-22, “Insertion loss deviation limits for Front Board test card.”

Figure 5-22 Insertion loss deviation limits for Front Board test card

Requirements

REQ 5.48 The insertion loss deviation (ILD) response for each signal path within the Front Board test card with connectors removed shall fall between the worst-case insertion loss deviation limits, ILDmax+ and ILDmax-, as defined by Equation 34 and Equation 35.

ILD f ILDmax+ f( ) 0.375=

ILD f ILDmax- f( ) 0.375–=

PICMG 3.1 R3.0, May 5, 2016 95


5.4.3.1.2 Return loss

¶ 183 The return loss (RL) of the Front Board test card with connectors removed is defined by Equation 36.

Equation 36.

For 10.0 MHz < f < 10.0 GHz (where f is expressed in Hz)

Note: The upper and lower frequency limits are derived from IEEE 802.3ba-2010 Equation 85-37.


¶ 184 The RL limit is shown in Figure 5-23, “Return loss limit for Front Board test card.”

Figure 5-23 Return loss limit for Front Board test card

Requirements

REQ 5.49 The return loss (RL) of the Front Board test card with connectors removed shall meet the return loss limit, RLmin as defined by Equation 36.

5.4.3.1.3 Common mode return loss

¶ 185 The common mode return loss (CMRL) of the Front Board test card with connectors removed is defined by Equation 37.

Equation 37.


RL f RLmin f( ) -5.19 log10 f 67.70+=

CMRL f CMRLmin f( ) 0.15 log10 f 5.8+=

96 PICMG 3.1 R3.0, May 5, 2016




¶ 186 The CMRL limit is shown in Figure 5-24, “Common mode return loss limit for the Front Board test card.”

Figure 5-24 Common mode return loss limit for the Front Board test card

Requirements

REQ 5.50 The common mode return loss (CMRL) of the Front Board test card with connectors removed shall meet the common mode return loss limit, CMRLmin as defined by Equation 37.

5.4.3.1.4 Common mode conversion loss

¶ 187 The common mode conversion loss (CMCL) of the Front Board test card with connectors removed is defined by Equation 38.

Equation 38.




CMCL f CMCLmin f( ) 11.67 – log10 f 142.0+=

PICMG 3.1 R3.0, May 5, 2016 97


¶ 188 The CMCL limit is shown in Figure 5-25, “Common mode conversion loss limit for Front Board test card.”

Figure 5-25 Common mode conversion loss limit for Front Board test card

5.4.3.1.5 Requirements

REQ 5.51 The common mode conversion loss (CMCL) of the Front Board test card with connectors removed shall meet the common mode conversion loss limit, CMCLmin as defined by Equation 38.


¶ 189 The worst case insertion loss to crosstalk ratio (ICR) within the Front Board test card with connectors removed is defined by Equation 39 and Equation 40.

Equation 39.


Equation 40.






98 PICMG 3.1 R3.0, May 5, 2016


¶ 190 The ICR limits are shown in Figure 5-26, “Insertion loss to crosstalk ratio limits for the Front Board test card.”

Figure 5-26 Insertion loss to crosstalk ratio limits for the Front Board test card

Requirements

REQ 5.52 The worst case insertion loss to crosstalk ratio (ICR) within the Front Board test card with connectors removed shall meet the insertion loss to crosstalk ratio limits, ICRmax and ICRmin, as defined by Equation 39 and Equation 40.

5.4.4 Backplane test paddle card requirements

¶ 191 The PICMG 3.1 10GBASE-KR and 40GBASE-KR4 Backplane test paddle card is used in conjunction with a Backplane test assembly in order to perform validation of PICMG 3.1-compliant Boards. In addition, Backplane test paddle cards are used to validate PICMG 3.1-compliant Backplanes. The Backplane test paddle card contains one ADFplus Board connector connected by differential signals to several connectors/probe points. The Backplane test paddle card provides a controlled reference by which Board measurements can be made. A representative Backplane test paddle card is shown in Figure 5-27, “Example Backplane test paddle card.” Although RP-SMA connectors are shown in this figure, the actual connector/probe point design is not dictated by this specification.

PICMG 3.1 R3.0, May 5, 2016 99


Figure 5-27 Example Backplane test paddle card

¶ 192 Due to the high speed nature of 10GBASE-KR and 40GBASE-KR4 signals, industry best practices will need to be applied to the implementation of the Backplane test paddle card. In particular, care will need to be taken to minimize the number of vias and length of via stubs in order to meet the requirements outlined in this section.

¶ 193 In order to avoid over-specification and promote vendor differentiation, the majority of the Backplane test paddle card requirements are given as electrical values. Exact implementation, including mechanical and material options, is not dictated by this specification.

¶ 194 Figure 5-28, “Test Point locations for the Backplane test paddle card” shows the defined test point locations used for the Backplane paddle card. These test points were adapted from IEEE 802.3ba-2010 section 85.7.1 in order to match the implementation of AdvancedTCA. The test points are described in Table 5-10, “Description of the Backplane test paddle card test points.” Unless otherwise specified, all Backplane paddle cards are defined between TP1/TP4 and TPB.

100 PICMG 3.1 R3.0, May 5, 2016


Figure 5-28 Test Point locations for the Backplane test paddle card

¶ 195 In the interest of testability, it can be useful to make measurements between TP1 and TP4 using a loopback connection as shown in Figure 5-29, “Possible loopback measurement configuration for the Backplane test paddle card.” As long as the Channel from TP1 to TPB and TP4 to TPB are symmetrical, measurements can be divided by two to compute the values from TP1 or TP4 to TPB.

Table 5-10 Description of the Backplane test paddle card test points


TP1/TP4 A test point located between the SMA (or equivalent) connector and the test equipment. TP1 refers to transmit connections, TP4 corresponds to receive.

TPB A test point located between the mated ADF connector and the test equipment. The test point is located at the position where the ADF connector pin would come in contact with the top surface of a PCB if it was installed in a PCB.

TP1/TP4 to TPB The Backplane paddle card Channel segment defined by PICMG 3.1. This Channel segment extends from the SMA (or equivalent connectors) through to the mated ADFplus/ADF connector pair.

PICMG 3.1 R3.0, May 5, 2016 101


Figure 5-29 Possible loopback measurement configuration for the Backplane test paddle card

Requirements

REQ 5.53 The differential impedance of the Backplane test paddle card shall be 100 Ohms +/-5 Ohms.

REQ 5.54 The Backplane test paddle card shall terminate at an ADFplus connector at one end of the signal paths.

REQ 5.55 The Backplane test paddle card shall implement the manufacturer’s recommended footprint for the ADFplus connector.

REQ 5.56 The Backplane test paddle card shall include at least two wafers of differential signals to the ADFplus connector for a total of at least 8 differential pairs of signal connections.

REQ 5.56.1 The differential signal pairs on the Backplane test paddle card shall reside on adjacent wafers.

REQ 5.57 Backplane test paddle card differential signal path lengths shall compensate for propagation time differences within the ADFplus connector.

REQ 5.58 In order to meet the stringent skew requirements of 10GBASE-KR and 40GBASE-KR4, Backplane test paddle card differential skew shall be less than 6 ps. This figure includes connector, signal path length, manufacturing and materials variations.


REQ 5.59 Backplane test paddle card signal paths shall have no vias except those terminating at the connectors

Note: There is no skew matching requirement from one pair to another pair.


¶ 196 The fitted attenuation for each signal path within the Backplane test paddle card including the mated ADFplus connector is defined by Equation 41 and Equation 42.

102 PICMG 3.1 R3.0, May 5, 2016


Equation 41.


Equation 42.




¶ 197 The fitted attenuation limits for the Backplane test paddle card are shown in Figure 5-30, “Fitted attenuation limits for the Backplane test paddle card.”

Figure 5-30 Fitted attenuation limits for the Backplane test paddle card

Requirement

REQ 5.60 The fitted attenuation for each signal path within the Backplane test paddle card including the mated ADFplus connector shall meet the limits Amin and Amax as defined by Equation 41 and Equation 42.

A f Amin f( ) 7.0810–10 f 0.43+=

A f Amax f( ) 8.7010–10 f 1.03+=

PICMG 3.1 R3.0, May 5, 2016 103


5.4.4.2 Insertion loss deviation

¶ 198 The insertion loss deviation (ILD) response for each signal path within the Backplane test paddle card including the mated ADFplus connector is defined by Equation 43 and Equation 44.

Equation 43.


Equation 44.


Note: The upper frequency and lower frequency limits are derived from IEEE 802.3-2008 Table 69B-1.


¶ 199 The maximum ILD limits for the Backplane test paddle card are shown in Figure 5-31, “Insertion loss deviation limits for the Backplane test paddle card.”

Figure 5-31 Insertion loss deviation limits for the Backplane test paddle card

Requirement

REQ 5.61 The insertion loss deviation (ILD) response for each signal path within the Backplane test paddle card including the mated ADFplus connector shall fall between the worst-case insertion loss deviation limits, ILDmax+ and ILDmax-, as defined by Equation 43 and Equation 44.

ILD f ILDmax+ f( ) 2.511–10 f 0.35+=

ILD f ILDmax- f( ) 2.5–11–10 f 0.35–=

104 PICMG 3.1 R3.0, May 5, 2016


5.4.4.3 Return loss

¶ 200 The return loss (RL) of the Backplane test paddle card including the mated ADFplus connector is defined by Equation 45.

Equation 45.


Note: The upper frequency and lower frequency limits are derived from IEEE 802.3ba-2010 Equation 85-37.


¶ 201 The RL limit is shown in Figure 5-32, “Return loss limits for the Backplane test paddle card.”

Figure 5-32 Return loss limits for the Backplane test paddle card

Requirement

REQ 5.62 The return loss (RL) of the Backplane test paddle card including the mated ADFplus connector shall meet the return loss limit, RLmin as defined by Equation 45.

5.4.4.4 Common mode return loss

¶ 202 The common mode return loss (CMRL) of the Backplane test paddle card including the mated ADFplus connector is defined by Equation 46.

RL f RLmin f( ) 8.97 log10 f – 94.01+=

PICMG 3.1 R3.0, May 5, 2016 105


Equation 46.




¶ 203 The CMRL limit is shown in Figure 5-33, “Common mode return loss limit for the Backplane test paddle card.”

Figure 5-33 Common mode return loss limit for the Backplane test paddle card

Requirements

REQ 5.63 The common mode return loss (CMRL) of the Backplane test paddle card including the mated ADFplus connector shall meet the common mode return loss limit, CMRLmin as defined by Equation 46.

5.4.4.5 Common mode conversion loss

¶ 204 The common mode conversion loss (CMCL) of the Backplane test paddle card including the mated ADFplus connector is defined by Equation 47.

Equation 47.



CMRL f CMRLmin f( ) 4.97 – log10 f 50.4+=

CMCL f CMCLmin f( ) 14.60 – log10 f 150.3+=

106 PICMG 3.1 R3.0, May 5, 2016



¶ 205 The CMCL limit is shown in Figure 5-34, “Common mode conversion loss limit for the Backplane test paddle card.”

Figure 5-34 Common mode conversion loss limit for the Backplane test paddle card

Requirements

REQ 5.64 The common mode conversion loss (CMCL) of the Backplane test paddle card including the mated ADFplus connector shall meet the common mode conversion loss limit, CMCLmin as defined by Equation 47.

5.4.4.6 Insertion loss to crosstalk ratio

¶ 206 The worst case insertion loss to crosstalk ratio (ICR) within the Backplane test paddle card including the mated ADFplus connector is defined by Equation 48 and Equation 49.

Equation 48.


Equation 49.





PICMG 3.1 R3.0, May 5, 2016 107



¶ 207 The ICR limits are shown in Figure 5-35, “Insertion loss to crosstalk ratio limits for the Backplane test paddle card.”

Figure 5-35 Insertion loss to crosstalk ratio limits for the Backplane test paddle card

Requirements

REQ 5.65 The worst case insertion loss to crosstalk ratio (ICR) within the Backplane test paddle card including the mated ADFplus connector shall meet the insertion loss to crosstalk ratio limits, ICRmax and ICRmin, as defined by Equation 48 and Equation 49.

Note: The following crosstalk aggressors are defined for this measurement.FEXT: CD1 and CD3 on the connector side of the paddle cardNEXT: AB1, AB2, AB3, EF1, EF2, and EF3 at the testpoint side of the paddle cardVictim: CD2 at the testpoint side of the paddle card.

5.4.5 Front Board Channel requirements

¶ 208 This section describes tests and requirements for PICMG 3.1 compliant Front Boards. These requirements are specific to signal paths that support 10GBASE-KR or 40GBASE-KR4 signaling (LCLASS 0011b). Channel requirements for signal paths of other signaling classes are governed by the PICMG 3.0 specification requirements.

¶ 209 Not all signal paths within a Front Board must comply with the specifications defined in this section; however, any LCLASS 0011b signal paths must meet all of the requirements given.

¶ 210 Due to the high speed nature of 10GBASE-KR and 40GBASE-KR4 signals, industry best practices will need to be applied to the implementation. In particular, care will need to be taken to minimize the number of vias and length of via stubs in order to meet the requirements outlined in this section.

108 PICMG 3.1 R3.0, May 5, 2016


¶ 211 In order to avoid over-specification and promote vendor differentiation, the majority of the Front Board requirements are given as electrical values. Exact implementation, including mechanical and material options, is not dictated by this specification.


Requirements

REQ 5.66 Each implemented LCLASS 0011b signal path shall be terminated with an IEEE compliant 10GBASE-KR or 40GBASE-KR4 transceiver.

REQ 5.67 The differential impedance of LCLASS 0011b signal paths within the Front Board shall be 100 Ohms +/- 10 Ohms.

REQ 5.68 LCLASS 0011b signal paths within a Front Board shall terminate at an ADFplus connector.

REQ 5.69 Front Board LCLASS 0011b differential signal path lengths shall compensate for Front Board propagation time differences within the ADFplus connector.

REQ 5.70 In order to meet the stringent skew requirements of 10GBASE-KR and 40GBASE-KR4, Front Board LCLASS 0011b differential skew shall be less than 6 ps. This figure includes connector, signal path length, manufacturing and materials variations.



¶ 212 The fitted attenuation for each LCLASS 0011b signal path within the Front Board including mated ADFplus connectors is defined by Equation 50, as specified from the transmitter pad to the Backplane side of the mated ADF connector pin.

Equation 50.



Note: This attenuation can be met with 5” of 6 mil traces and terminating vias within Nelco 4000-6 material. The actual implementation is not specified.

¶ 213 The fitted attenuation limit for the Front Board is shown in Figure 5-36, “Fitted attenuation limit for LCLASS 0011b signal paths in Front Board.”

A f Amax f( ) 8.4810–10 f 0.42+=

PICMG 3.1 R3.0, May 5, 2016 109


Figure 5-36 Fitted attenuation limit for LCLASS 0011b signal paths in Front Board

Requirements

REQ 5.71 The Front Board fitted attenuation for each LCLASS 0011b signal path including mated ADFplus connectors shall meet the limits Amax as defined by Equation 50, as specified from the transmitter pad to the Backplane side of the mated ADF connector pin.

REQ 5.71.1 Compliance to REQ 5.71 might be difficult to establish by direct measurement. For this reason, suppliers may ensure REQ 5.71 is met by simulation or design.

5.4.5.2 S-Parameter and jitter testing and requirements

¶ 214 Front Board S-parameter and jitter measurements are made using a PICMG 3.1 Front Board test card. The unit under test is inserted into the ADF connector on the test card and test equipment is connected to the Front Board test card. A representative unit under test and test card are shown in Figure 5-37, “Front Board Inserted into Front Board test card.” The tester will also need to provide power the unit under test.

110 PICMG 3.1 R3.0, May 5, 2016


Figure 5-37 Front Board Inserted into Front Board test card

¶ 215 The recommended test setup for Front Board S-parameter and jitter tests is shown in Figure 5-38, “Recommended test setup for Front Board S-parameter and jitter tests.”

Figure 5-38 Recommended test setup for Front Board S-parameter and jitter tests

5.4.5.3 Return loss

¶ 216 The Return Loss (RL) for each Front Board LCLASS 0011b signal is defined by Equation 51 and Equation 52, when measured at TP2 and TP3 of the Front Board test card.

PICMG 3.1 R3.0, May 5, 2016 111


Equation 51.


Equation 52.


Note: The frequency limits are derived from IEEE 802.3ba-2010 Equation 85-1.

¶ 217 The RL limit is shown in Figure 5-39, “Return loss limits for LCLASS 0011b signal paths in Front Board.”

Figure 5-39 Return loss limits for LCLASS 0011b signal paths in Front Board

Requirements

REQ 5.72 The Return Loss (RL) for each Front Board LCLASS 0011b signal shall meet the return loss requirement given in Equation 51 and Equation 52, when measured at TP2 and TP3 of the Front Board test card.


¶ 218 The transmitter’s Common Mode Return Loss (CMRL) for each Front Board LCLASS 0011b Signal is defined in Equation 53 and Equation 54, when measured at TP2 of the Front Board test card.

RL f RLmin f( ) 11.0 2 f 1910–=

RL f RLmin f( ) 5.3 13log10 f 5.5910 –=

112 PICMG 3.1 R3.0, May 5, 2016


Equation 53.


Equation 54.


Note: The upper frequency limit is derived from IEEE 802.3-2008 Equation 72-5. The lower frequency limit was selected for PICMG 3.1 because it was felt that the IEEE lower frequency limits were too stringent.

¶ 219 The CMRL limit is shown in Figure 5-40, “Common mode return loss limits for LCLASS 0011b signal paths in a Front Board.”

Figure 5-40 Common mode return loss limits for LCLASS 0011b signal paths in a Front Board

Requirements

REQ 5.73 The transmitter’s Common Mode Return Loss (CMRL) for each Front Board LCLASS 0011b Signal shall meet the transmitter’s common mode return loss requirements given in Equation 53 and Equation 54, when measured at TP2 of the Front Board test card.

REQ 5.74 The maximum random jitter of any Front Board LCLASS 0011b signal shall be no more than 14.6 ps when measured at TP2 of the Front Board test card. This measurement is equivalent to 0.15 unit intervals (UI).

REQ 5.75 The maximum Duty Cycle Distortion (DCD) of any Front Board LCLASS 0011b signal shall be no more than 3.4 ps when measured at TP2 of the Front Board test card or electrical equivalent. This measurement is equivalent to 0.035 unit intervals (UI).

CMRL f CMRLmin f( ) 6.0=

CMRL f CMRLmin f( ) 6.0 12log10 f 2.5910 –=

PICMG 3.1 R3.0, May 5, 2016 113


REQ 5.76 The maximum total jitter excluding data dependent jitter (DDJ) of any Front Board LCLASS 0011b Link shall be no more than 24.24ps when measured at TP2 of the Front Board test card. This is equivalent to 0.25 unit intervals (UI).

REQ 5.77 The signaling rate shall be in a range of 10.3125 +/- 100 ppm Gbd when measured at TP2 of the Front Board test card or electrical equivalent.

REQ 5.78 The Transmitter DC amplitude shall be greater than 0.3 V and less than or equal to 0.6 V when measured at TP2 of the Front Board test card or electrical equivalent using the procedure of IEEE 802.3-2008 section 85.8.3.3.

REQ 5.79 The peak of the linear fit pulse response shall be greater than 0.6 × DC amplitude when measured at TP2 of the Front Board test card or electrical equivalent using the procedure of IEEE 802.3-2008 section 85.8.3.3.

REQ 5.80 The RMS value of the error between the linear fit and the measured waveform normalized to the peak value of the pulse shall be no greater than 0.045 when measured at TP2 of the Front Board test card or electrical equivalent using the procedure of IEEE 802.3-2008 section 85.8.3.3.

5.4.5.5 Crosstalk and error rate testing and requirements

¶ 220 Crosstalk and bit error rate testing of Front Boards requires two fixture configurations to emulate the different Backplane environments that the card might be inserted into.

¶ 221 The short Channel test fixture (or equivalent) is used to test Front Board behavior as it drives signals through a Channel that is similar to a short Backplane signal path. The short Channel test fixture consists of a Backplane test paddle card inserted into a short Backplane test assembly as shown in Figure 5-41, “Front Board transmit/receive setup with the short Backplane test assembly.”

Figure 5-41 Front Board transmit/receive setup with the short Backplane test assembly

¶ 222 The long Channel test fixture (or equivalent) is used to test Front Board behavior as it drives signals through a Channel that is similar to a long Backplane signal path. The long Channel test fixture consists of a Backplane test paddle card inserted into a long Backplane test assembly.

114 PICMG 3.1 R3.0, May 5, 2016


¶ 223 In the case of both the short and the long test fixtures, the unit under test is inserted into the empty ADF connector on the Backplane test assembly and a Backplane test paddle card is inserted into the other connector. Test equipment is connected to the Backplane test paddle card.

¶ 224 Some test fixtures may be capable of emulating the S-parameter characteristics of part or all of the above test fixtures. Alternatively the effects of test fixtures may be added to direct measurements through post-measurement computations. Either of these methods is allowed so long as the characteristics of the emulated/computed fixtures match the requirements found within this specification.

¶ 225 A recommended test setup for measurement of bit error rates is shown in Figure 5-42, “Recommended test setup for Front Board bit error rate testing.” This setup is based on the test setup defined in IEEE Annex 69A of 802.3-2008. Alternate test setups may be required due to availability and maturity of test equipment, and the instrumentation of the receiver on the unit under test.

Figure 5-42 Recommended test setup for Front Board bit error rate testing

Requirements

REQ 5.81 Front Boards shall obtain a bit error rate of 10-12 or better when tested with a PICMG 3.1 short Channel test fixture and Backplane test paddle card.

REQ 5.81.1 Compliance to REQ 5.81 might be difficult to establish by direct measurement due to the maturity of test equipment. For this reason, suppliers may ensure REQ 5.81 is met by simulation.

REQ 5.82 Front Boards shall obtain a bit error rate of 10-12 or better when tested with a PICMG 3.1 long Channel test fixture and Backplane test paddle card.

REQ 5.82.1 Compliance to REQ 5.82 might be difficult to establish by direct measurement due to the maturity of test equipment. For this reason, suppliers may ensure REQ 5.82 is met by simulation.

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5.4.6 Backplane Channel requirements

¶ 226 This section describes tests and requirements for PICMG 3.1 compliant Backplanes. These requirements are specific to signal paths that support 10GBASE-KR and 40GBASE-KR4 signaling (LCLASS 0011b). Channel requirements for signal paths of other signaling classes are governed by the PICMG 3.0 or relevant subsidiary specification requirements.

¶ 227 Not all signal paths within a Backplane must comply with the specifications defined in this section, however, any LCLASS 0011b signal paths must meet all of the requirements given.

¶ 228 Due to the high speed nature of 10GBASE-KR and 40GBASE-KR4 signals, industry best practices will need to be applied to the implementation. In particular, care will need to be taken to minimize the number of vias and length of via stubs in order to meet the requirements outlined in this section.

¶ 229 In order to avoid over-specification and promote vendor differentiation, the majority of the Backplane Channel requirements are given as electrical values. Exact implementation, including mechanical and material options, is not dictated by this specification.


Figure 5-43 Test point locations for Backplane testing

¶ 230 Test setup includes a Backplane test paddle card installed into the Backplane’s ADF Zone 2 Connectors at each end of the Channel under test as shown in Figure 5-44, “Backplane test setup with two Backplane test paddle cards.” Test equipment is connected directly to each of the Backplane test paddle cards in order to make measurements.

¶ 231 Some test equipment may be capable of emulating the S-parameter characteristics of part or all of the mated paddle card assembly. Alternatively the effects of test fixtures may be added to direct measurements through post-measurement computations. Either of these methods is allowed so long as the characteristics of the emulated/computed fixtures match the test fixture characteristics found within this specification.

116 PICMG 3.1 R3.0, May 5, 2016


Figure 5-44 Backplane test setup with two Backplane test paddle cards

Requirements

REQ 5.83 The differential impedance of LCLASS 0011b signal paths within the Backplane shall be 100 Ohms +/- 10 Ohms.

REQ 5.84 In order to meet the stringent skew requirements of 10GBASE-KR and 40GBASE-KR4, LCLASS 0011b Backplane signal path differential skew shall be less than 6 ps. This figure includes signal path length, manufacturing and materials variations.


REQ 5.85 LCLASS 0011b Backplane signal path S-parameter and crosstalk measurements shall be made between TP1 and TP4 of connected Backplane test paddle cards, or their electrical or computational equivalent, as defined in Figure 5-43, “Test point locations for Backplane testing.”


¶ 232 The fitted attenuation for each LCLASS 0011b signal paths within the Backplane is defined by Equation 55.

Equation 55.



Note: This limit includes the impact of the two Backplane test paddle cards used in the required test setup.

A f Amax f( ) 3.639–10 f 3.22+=

PICMG 3.1 R3.0, May 5, 2016 117


Note: This limit was derived through simulation of 6 mil trace width x 8 mil edge-to-edge spacing through Nelco 4000-13 material with 106 mil via stubs. The actual implementation can vary so long as all requirements are met.

¶ 233 The fitted attenuation limit for LCLASS 0011b signal paths within the Backplane is shown in Figure 5-45, “Fitted attenuation limits for LCLASS 0011b Backplane signal paths.”

Figure 5-45 Fitted attenuation limits for LCLASS 0011b Backplane signal paths

Requirement

REQ 5.86 The fitted attenuation for each LCLASS 0011b signal paths within the Backplane is defined by Equation 55.


¶ 234 The insertion loss deviation (ILD) response for each LCLASS 0011b signal path within the Backplane is defined by Equation 56 and Equation 57.

Equation 56.


Equation 57.



Note: These limits include the impact of the two Backplane test paddle cards used in the required test setup.

ILD f ILDmax+ f( ) 6.010–10 f 0.9+=

ILD f ILDmax- f( ) 6.0–10–10 f 0.9–=

118 PICMG 3.1 R3.0, May 5, 2016



¶ 235 The ILD limits for LCLASS 0011b Backplane signal paths are shown in Figure 5-46, “Insertion loss deviation limits for LCLASS 0011b Backplane signal paths.”

Figure 5-46 Insertion loss deviation limits for LCLASS 0011b Backplane signal paths

Requirements

REQ 5.87 The insertion loss deviation (ILD) response for each LCLASS 0011b signal path within the Backplane shall meet the worst-case insertion loss deviation limits, ILDmax+ and ILDmax-, as defined by Equation 56 and Equation 57.


¶ 236 The worst case insertion loss to crosstalk ratio (ICR) for LCLASS 0011b signal paths within the Backplane is defined by Equation 58.

Equation 58.



Note: This limit includes the impact of the two Backplane test paddle cards used in the required test setup.


ICR f ICRmin f( ) 18.79log10 f – 205.97+=

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¶ 237 The ICR limit for LCLASS 0011b Backplane signal paths is shown in Figure 5-47, “Insertion loss to crosstalk ratio limits for LCLASS 0011b Backplane signal paths.”

Figure 5-47 Insertion loss to crosstalk ratio limits for LCLASS 0011b Backplane signal paths

Requirement

REQ 5.88 The worst case insertion loss to crosstalk ratio (ICR) for LCLASS 0011b signal paths within the Backplane shall meet the insertion loss to crosstalk ratio limit, ICRmin , as defined by Equation 58.

5.4.7 Channel fitted attenuation (informative)

¶ 238 This section provides information about the fitted attenuation of the complete PICMG 3.1 LCLASS 0011b Channel, including the characteristics of two Front Boards, two sets of mated connectors and a Backplane.

¶ 239 No requirements are given within this section. This information is being provided to show how the combination of PICMG 3.1-compliant Front Boards and Backplanes results in a Channel that is very similar to the reference Channel found in IEEE 802.3-2008 Annex 69B.

¶ 240 The maximum Channel fitted attenuation for a given frequency can be found using Equation 59.

Equation 59.

Where

f is the frequency in Hz

AChmax is the maximum complete Channel fitted attenuation

AChmax f ABPmax f( ) 2APaddlemin f( )– 2ABrdmax f( )+=

120 PICMG 3.1 R3.0, May 5, 2016


ABPmax is the maximum Backplane fitted attenuation between TP1 and TP4 as defined in Equation 55

APaddlemin is the minimum fitted attenuation contribution from a Backplane paddle test card (from TP1 to TPB) as defined in Equation 41

ABrdmax is the maximum Front Board fitted attenuation as defined in Equation 50

Figure 5-48 Example Channel fitted attenuation loss at 5.15625 GHz

SMA Connectors

SMA Connectors

BackplaneBackplane Test

Paddle CardBackplane Test

Paddle Card

TP1 TP4

TransmitFunction

Receive Function

Front Board (TX) Front Board (RX)

PCB Traces

PCB Traces

TPB TPB

21.94 dB 4.08 dB 4.08 dB

4.79 dB 4.79 dB

Achmax(5.15625GHz) = 21.94 – (2 x 4.08) + (2 x 4.79) = 23.36 dB

TP0 TP5“TPB” “TPB”

PICMG 3.1 R3.0, May 5, 2016 121


5.5 Auto-Negotiation (informative)

5.5.1 1000BASE-BX to 10GBASE-BX4 Auto-Negotiation

¶ 241 Fibre Channel, 1000BASE-BX, and 10GBASE-BX4 operation are treated as separate Channel implementations by electronic keying. PICMG 3.1 does not require or assume any form of Auto-Negotiation or configuration within the Channel between these signaling interfaces. The out of band electronic keying mechanism defined by PICMG 3.0 manages the configuration of Port/Channel allocations.

5.5.2 1000BASE-KX/10GBASE-KX4/10GBASE-KR/40GBASE-KR4 Auto-Negotiation

¶ 242 IEEE 802.3-2008, as amended by IEEE 802.3ba-2010, defines Auto-Negotiation between the 1000BASE-KX, 10GBASE-KX4, 10GBASE-KR and 40GBASE-KR4 physical layers. The use of Auto-Negotiation is optional per the 802.3 specification. PICMG 3.1 treats 1000BASE-KX, 10GBASE-KX4, 10GBASE-KR and 40GBASE-KR4 as separate Channel implementations selected by electronic keying. Although PICMG 3.1 does not require any form of Auto-Negotiation within the Channel between these interfaces, Auto-Negotiation can be useful to configure other features beyond the medium dependent interface (MDI) such as forward error correction (FEC) and PAUSE capability.

¶ 243 If Auto-Negotiation is enabled in a PICMG 3.1 Board, care must be taken to ensure that the technologies advertised via the Technology Ability Field during the 802.3 Auto-Negotiation process correspond with the Link Descriptors enabled during the E-Keying process so that the Board does not attempt to negotiate a Link beyond the Channel’s capabilities.

5.6 100GBASE-KR4 Channel characteristics

¶ 244 This section introduces physical layer Channel requirements to implement a 25.78125 Gbd Channel (LCLASS 0100b). Requirements are given for both Front Boards that implement 100GBASE-KR4 transceivers, and Backplanes that are intended to support these higher speed Boards.

¶ 245 Since 25.78125 Gbd signaling is a significant departure from the basic signaling class defined in PICMG 3.0, this section also includes information about test methodology and measurement calculations used to validate the Channel.

¶ 246 Three test fixtures (or their equivalent) are required to make these measurements. Parameters for the test fixtures are tightly defined and their requirements are given in Section 5.6.2, “100GBASE-KR4 Backplane test assembly characteristics” through Section 5.6.4, “100GBASE-KR4 Backplane test paddle card requirements.”

¶ 247 Requirements for Front Boards are given in Section 5.6.5, “Front Board Channel requirements” and Backplane requirements are found in Section 5.6.6, “Backplane Channel requirements.”

¶ 248 Information contained in this section of PICMG 3.1 adopts nomenclature consistent with the IEEE 802.3 standard to facilitate better understanding of both documents.

122 PICMG 3.1 R3.0, May 5, 2016


¶ 249 Figure 5-49, “Test point locations for LCLASS 0100b Channels” shows the test point locations for the endpoints of PICMG 3.1 100GBASE-KR4 Channels. Direct measurement between these points for all combinations of Boards and Backplanes is infeasible; however, utilizing the requirements and test methods within this chapter will ensure that any combination of Boards/Backplane will result in a Channel that closely resembles the reference Channel defined by IEEE 802.3 for 100GBASE-KR4.

Figure 5-49 Test point locations for LCLASS 0100b Channels

¶ 250 The locations of each of the test points are described in Table 5-11, “Description of LCLASS 0100b Channel test points” below.

5.6.1 Definitions of measurements and calculations (informative)

¶ 251 This section defines a number of calculations used to validate PICMG 3.1-compliant Channels that are intended to support IEEE 100GBASE-KR4 signaling. These definitions are identical to those found in IEEE 802.3bjtm-2014. IEEE 802.3bj-2014 equation numbers have been given for ease of cross-reference.

Table 5-11 Description of LCLASS 0100b Channel test points


TP0A test point on the transmitter Board that is at the package-to-board interface of the transmit function.

TP5A test point on the receiver Board that is at the package-to-board interface of the receive function.

TP0 to TP5The complete LCLASS 0100b Channel. This is equivalent to the electrical Backplane Channel for 100GBASE-KR4 as specified by IEEE.

PICMG 3.1 R3.0, May 5, 2016 123


5.6.1.1 Channel Operating Margin

¶ 252 The Channel Operating Margin (COM) is a figure of merit for 100GBASE-KR4 Ethernet defined by IEEE 802.3bj-2014. Calculation of this parameter is quite complex and is derived from measurement of the Channel’s scattering parameters. COM is related to the ratio of signal amplitude to a calculated noise amplitude as show in the following equation.

Equation 60. (802.3bjtm-2014 93A-1)

COM = 20 log10(As/Ani)

For precise calculation of COM, the reader is referred to the IEEE document.

5.6.2 100GBASE-KR4 Backplane test assembly characteristics

¶ 253 The PICMG 3.1 100GBASE-KR4 Backplane test assembly is used in conjunction with a 100GBASE-KR4 Backplane test paddle card in order to perform validation of PICMG 3.1-compliant Boards. The purpose of the Backplane test assembly is to provide a reference Backplane segment with tightly controlled characteristics with which Front Board tests can be made. The Backplane test assembly is intended to capture the worst-case conditions that can be encountered with a compliant Backplane.

¶ 254 The Backplane test assembly contains two ADF++ Backplane connectors connected by differential signals. Some representative Backplane test assemblies are shown in Figure 5-50, “Examples of long and short 100GBASE-KR4 Backplane test assemblies.”

Figure 5-50 Examples of long and short 100GBASE-KR4 Backplane test assemblies

¶ 255 Since the length of the Backplane signal paths within a PICMG 3.1 Shelf can vary significantly, two length variations of the 100GBASE-KR4 Backplane test assembly are defined: long and short. These two lengths are intended to capture both the longest signal path and shortest signal path that a Board can encounter in a PICMG 3.1-compliant environment.

¶ 256 Due to the high speed nature of 100GBASE-KR4 signals, industry best practices will need to be applied to the implementation of the Backplane test assembly. In particular, care will need to be taken to minimize the number of vias and length of via stubs in order to meet the requirements outlined in this section.

¶ 257 In order to avoid over-specification and promote vendor differentiation, the majority of 100GBASE-KR4 Backplane test assembly requirements are given as electrical values. Exact implementation, including mechanical and material options, is not dictated by this specification.

124 PICMG 3.1 R3.0, May 5, 2016


¶ 258 Figure 5-51, “Test point locations for validation of the 100GBASE-KR4 Backplane test assembly” shows the defined test point locations used for the 100GBASE-KR4 Backplane test assembly. The test points are described in Table 5-12, “Description of the 100GBASE-KR4 Backplane test assembly test points.” Unless otherwise specified, all 100GBASE-KR4 Backplane test assemblies are defined between TPC and TPD.

Figure 5-51 Test point locations for validation of the 100GBASE-KR4 Backplane test assembly

5.6.2.1 100GBASE-KR4 Backplane test assembly common requirements

¶ 259 This section contains requirements that are common to both the long 100GBASE-KR4 Backplane test assembly and the short 100GBASE-KR4 Backplane test assembly. Specific requirements for each of these variants are contained in the following sections.

Requirements

REQ 5.89 The differential impedance of the 100GBASE-KR4 Backplane test assembly shall be 100 Ohms +/- 10 Ohms.

REQ 5.90 The 100GBASE-KR4 Backplane test assembly shall allow for a standard PICMG 3.0 Board to be physically inserted without modifying the Board.

Table 5-12 Description of the 100GBASE-KR4 Backplane test assembly test points


TPCThe interface plane between the top surface of the Backplane and the transmit ADF++ connector.

TPDThe interface plane between the top surface of the Backplane and the receive ADF++ connector.

TPC to TPDThe Backplane test assembly Channel segment defined by PICMG 3.1. The ADF++ connectors are not included in this Channel segment.

PICMG 3.1 R3.0, May 5, 2016 125


REQ 5.91 The 100GBASE-KR4 Backplane test assembly shall terminate at ADF++ Backplane connectors at either end of the card.

REQ 5.92 The 100GBASE-KR4 Backplane test assembly shall implement the manufacturer’s recommended footprint for the ADF++ Backplane connectors.

REQ 5.93 The 100GBASE-KR4 Backplane test assembly shall include at least three wafers of differential signals at each ADF++ connector for a total of at least 12 differential pairs of signal connections.

REQ 5.93.1 The differential signal pairs for the 100GBASE-KR4 Backplane test assembly shall reside on adjacent wafers.

REQ 5.94 The 100GBASE-KR4 Backplane test assembly shall connect transmit signals on one ADF++ Backplane connector (rows ab and ef) to the corresponding receive pins (row cd and gh) on the ADF++ 100GBASE-KR4 Backplane connector (crossover connection).

REQ 5.95 In order to meet the stringent skew requirements of 100GBASE-KR4, Backplane test assembly differential skew shall be less than 6 ps. This figure includes signal path length, manufacturing and materials variations.

REQ 5.95.1 Compliance to REQ 5.95 might be difficult to establish by direct measurement. In this case, suppliers shall ensure REQ 5.95 is met by design.

REQ 5.96 100GBASE-KR4 Backplane test assembly signal paths shall have no vias except those terminating at the connectors.

5.6.2.2 Short 100GBASE-KR4 Backplane test assembly requirements

¶ 260 Requirements in this section apply specifically to the short implementation of the 100GBASE-KR4 Backplane test assembly. Requirements for the long version of the 100GBASE-KR4 Backplane test assembly are included in the next section.


¶ 261 The fitted attenuation for each signal path within the short 100GBASE-KR4 Backplane test assembly with connectors removed is defined by Equation 61, Equation 62, and Table 5-13, “Short Backplane Test Assembly Fitted Attenuation Parameters.”

Equation 61.

Afitted > Amin = m1 f + b1

for all frequencies between f1 and f2

Equation 62.

Afitted < Amax = m2 f + b2


126 PICMG 3.1 R3.0, May 5, 2016


¶ 262 The fitted attenuation limits for the short 100GBASE-KR4 Backplane test assembly are shown in the following figure.

Figure 5-52 Fitted attenuation limits for short 100GBASE-KR4 Backplane test assembly

Requirements

REQ 5.97 The fitted attenuation for each signal path within the short 100GBASE-KR4 Backplane test assembly with connectors removed shall meet the limits Amin and Amax as defined by Equation 61, Equation 62, and Table 5-13, “Short Backplane Test Assembly Fitted Attenuation Parameters.”


¶ 263 The insertion loss deviation (ILD) response for each signal path within the short 100GBASE-KR4 Backplane test assembly with connectors removed is defined by Equation 63, Equation 64, and Table 5-14, “Insertion loss deviation limits for short 100GBASE-KR4 Backplane test assembly.”

Equation 63.

ILD > ILDmin = m1 f + b1


Table 5-13 Short Backplane Test Assembly Fitted Attenuation Parameters

Parameter Value Parameter Valuem1 1.71E-10 f1 (Hz) 1.00E+09

b1 -0.143 f2 (Hz) 1.50E+10

m2 2.54E-10

b2 0.997

PICMG 3.1 R3.0, May 5, 2016 127


Equation 64.

ILD < ILDmax = m2 f + b2


¶ 264 The insertion loss deviation limits for the short 100GBASE-KR4 Backplane test assembly are shown in the following figure.

Figure 5-53 Insertion loss deviation limits for the short 100GBASE-KR4 Backplane test assembly

Requirements

REQ 5.98 The insertion loss deviation (ILD) response for each signal path within the short 100GBASE-KR4 Backplane test assembly with connectors removed shall fall between the worst-case insertion loss deviation limits, ILDmax+ and ILDmax-, as defined by Equation 63, Equation 64, and Table 5-14, “Insertion loss deviation limits for short 100GBASE-KR4 Backplane test assembly.”


¶ 265 The worst case insertion loss to crosstalk ratio (ICR) within the short 100GBASE-KR4 Backplane test assembly with connectors removed is defined by Equation 65, Equation 66, and Table 5-15, “Parameters for Short Backplane test assembly Insertion Loss to Crosstalk Ratio.”

Table 5-14 Insertion loss deviation limits for short 100GBASE-KR4 Backplane test assembly

Parameter Value Parameter Valuem1 -2.11E-11 f1 (Hz) 1.00E+09

b1 -0.75 f2 (Hz) 1.50E+10

m2 2.11E-11

b2 0.75

128 PICMG 3.1 R3.0, May 5, 2016


Equation 65.

ICR > ICRmin = m1 LOG10(f) + b1


Equation 66.

ICR < ICRmax = m2 LOG10(f) + b2


¶ 266 The ICR limits are shown in the following figure.

Figure 5-54 Insertion loss to crosstalk ratio limits for the short 100GBASE-KR4 Backplane test assembly

Requirements

REQ 5.99 The worst case insertion loss to crosstalk ratio (ICR) within the short 100GBASE-KR4 Backplane test assembly with connectors removed shall meet the insertion loss to crosstalk ratio limits, ICRmax and ICRmin, as defined by Equation 65, Equation 66, and Table 5-15, “Parameters for Short Backplane test assembly Insertion Loss to Crosstalk Ratio.”

Table 5-15 Parameters for Short Backplane test assembly Insertion Loss to Crosstalk Ratio

Parameter Value Parameter Value

m1 -2.14E+01 f1 (Hz) 5.00E+08

b1 236.54 f2 (Hz) 1.25E+10

m2 -2.14E+01

b2 252.36

PICMG 3.1 R3.0, May 5, 2016 129


Note: When victim CD2 is evaluated, the following aggressors are defined:FEXT: AB1 and AB3 at the opposite (far) end of the Backplane test assemblyNEXT: AB1, AB2, AB3, EF1, EF2, and EF3 at the same (near) end as the victim test points

Note: When victim GH2 is evaluated, the following aggressors are defined:FEXT: EF1 and EF3 at the opposite (far) end of the Backplane test assemblyNEXT: EF1, EF2, EF3 at the same (near) end as the victim test points

5.6.2.3 Long 100GBASE-KR4 Backplane test assembly requirements

¶ 267 The requirements in this section apply specifically to the long version of the 100GBASE-KR4 Backplane test assembly. General requirements for the 100GBASE-KR4 Backplane test assembly and specific requirements for the short version of the 100GBASE-KR4 Backplane test assembly are included in the previous sections.


¶ 268 The fitted attenuation for each signal path within the long 100GBASE-KR4 Backplane test assembly with the connectors removed is defined by Equation 67, Equation 68, and Table 5-16, “Long Backplane test assembly Fitted Attenuation parameters.”

Equation 67.



Equation 68.



¶ 269 The fitted attenuation limits for the long 100GBASE-KR4 Backplane test assembly are shown in the following figure.

Table 5-16 Long Backplane test assembly Fitted Attenuation parameters


m1 5.69E-10 f1 (Hz) 1.00E+09

b1 0.94 f2 (Hz) 1.50E+10

m2 6.54E-10

b2 2.09

130 PICMG 3.1 R3.0, May 5, 2016


Figure 5-55 Fitted attenuation limits for the long 100GBASE-KR4 Backplane test assembly

Requirements

REQ 5.100 The fitted attenuation for each signal path within the long Backplane test assembly with the connectors removed shall meet the limits Amax and Amin as defined by Equation 67, Equation 68, and Table 5-16, “Long Backplane test assembly Fitted Attenuation parameters.”


¶ 270 The insertion loss deviation (ILD) response for each signal path within the long 100GBASE-KR4 Backplane test assembly with connectors is defined by Equation 69, Equation 70, and Table 5-17, “Insertion loss deviation limits for long 100GBASE-KR4 Backplane test assembly.”

Equation 69.



Equation 70.



PICMG 3.1 R3.0, May 5, 2016 131


¶ 271 The maximum ILD limits for the long 100GBASE-KR4 Backplane test assembly are shown in the following figure.

Figure 5-56 Insertion loss deviation limits for the long Backplane test assembly

Requirements

¶ 272 The insertion loss deviation (ILD) response for each signal path within the long 100GBASE-KR4 Backplane test assembly with connectors removed shall fall between the worst-case insertion loss deviation limits, ILDmax+ and ILDmax-, as defined byEquation 69, Equation 70, and Table 5-17, “Insertion loss deviation limits for long 100GBASE-KR4 Backplane test assembly.”


¶ 273 The worst case insertion loss to crosstalk ratio (ICR) within the long 100GBASE-KR4 Backplane test assembly with connectors removed is defined by Equation 71, Equation 72, and Table 5-18, “Parameters for long Backplane test assembly Insertion Loss to Crosstalk Ratio.”

Table 5-17 Insertion loss deviation limits for long 100GBASE-KR4 Backplane test assembly


m1 0.00 f1 (Hz) 1.00E+09

b1 -1.12 f2 (Hz) 1.50E+10

m2 0.00

b2 1.12

132 PICMG 3.1 R3.0, May 5, 2016


Equation 71.



Equation 72.



¶ 274 The ICR limits are shown in the following figure.

Figure 5-57 Insertion loss to crosstalk ratio for the long 100GBASE-KR4 Backplane test assembly

Requirements

REQ 5.101 The long Backplane test assembly shall include additional six ADF++ Backplane connector footprints evenly spaced along the length of the assembly in order to replicate the effects of additional Slots in a real Backplane. Actual connectors need not be populated.

REQ 5.102 Rough-holes in the additional footprints shall be grounded.

Table 5-18 Parameters for long Backplane test assembly Insertion Loss to Crosstalk Ratio


m1 -2.15E+01 f1 (Hz) 5.00E+08

b1 237.42 f2 (Hz) 1.25E+10

m2 -2.16E+01

b2 254.07

PICMG 3.1 R3.0, May 5, 2016 133


REQ 5.103 The worst case insertion loss to crosstalk ratio (ICR) within the long 100GBASE-KR4 Backplane test assembly with connectors removed shall meet the insertion loss to crosstalk ratio limits, ICRmax and ICRmin, as defined by Equation 71, Equation 72, and Table 5-18, “Parameters for long Backplane test assembly Insertion Loss to Crosstalk Ratio.”

Note: When victim CD2 is evaluated, the following aggressors are defined:FEXT: AB1 and AB3 at the opposite (far) end of the Backplane test assemblyNEXT: AB1, AB2, AB3, EF1, EF2, and EF3 at the same (near) end as the victim test points

Note: When victim GH2 is evaluated, the following aggressors are defined:FEXT: EF1 and EF3 at the opposite (far) end of the Backplane test assemblyNEXT: EF1, EF2, EF3 at the same (near) end as the victim test points

5.6.3 100GBASE-KR4 Front Board test card requirements

¶ 275 The PICMG 3.1 100GBASE-KR4 Front Board test card is used to perform S-parameter and crosstalk validation of PICMG 3.1-compliant Front Boards. The 100GBASE-KR4 Front Board test card contains one ADF++ Backplane connector that is fanned out to test points. The Front Board test card provides a controlled reference by which Front Board Channel measurements can be made. Provisions must also be made to power the unit under test. How this is accomplished is not covered by this specification.

¶ 276 A representative 100GBASE-KR4 Front Board test card is shown in Figure 5-58, “Example 100GBASE-KR4 Front Board test assembly.” An optimal implementation would allow Front Boards to be tested without having to alter the Front Board. Although RP-SMA connectors are shown in this figure, the actual connector/probe point design is not dictated by this specification.

Figure 5-58 Example 100GBASE-KR4 Front Board test assembly

¶ 277 Due to the high speed nature of 100GBASE-KR4 signals, industry best practices will need to be applied to the implementation of the 100GBASE-KR4 Front Board test card. In particular, care will need to be taken to minimize the number of vias and length of via stubs in order to meet the requirements outlined in this section.

134 PICMG 3.1 R3.0, May 5, 2016


¶ 278 In order to avoid over-specification and promote vendor differentiation, the majority of the 100GBASE-KR4 Front Board test card requirements are given as electrical values. Exact implementation, including mechanical and material options, is not dictated by this specification.

¶ 279 Figure 5-59, “Test point locations for the 100GBASE-KR4 Front Board test card” shows the defined test point locations used for the 100GBASE-KR4 Front Board test card. The test points are described in Table 5-19, “Description of the Front Board test card test points.” Unless otherwise specified, all 100GBASE-KR4 Front Board test cards are defined between TP2 or TP3 to TPA.

Figure 5-59 Test point locations for the 100GBASE-KR4 Front Board test card

Table 5-19 Description of the Front Board test card test points


TP2/TP3A test point located between the SMA (or equivalent) connector and the test equipment. TP2 refers to transmit connections, TP3 corresponds to receive.

TPAA test point located between the top surface of the Front Board test card PCB at the ADF++ connector via and the test equipment cabling.

TP2/TP3 to TPA

The 100GBASE-KR4 Front Board test card test Channel segment defined by PICMG 3.1. This Channel segment extends from the SMA (or equivalent connectors) through to the ADF++ connector vias. The ADF++ connector is not included in this Channel segment.

PICMG 3.1 R3.0, May 5, 2016 135


Requirements

REQ 5.104 The differential impedance of the 100GBASE-KR4 Front Board test card shall be 100 Ohms +/- 5 Ohms.

REQ 5.105 The 100GBASE-KR4 Front Board test card shall terminate at an ADF++ Backplane connector at one end of the signal paths.

REQ 5.106 The 100GBASE-KR4 Front Board test card shall implement the manufacturer’s recommended footprint for the ADF++ Backplane connector.

REQ 5.107 The 100GBASE-KR4 Front Board test assembly shall include at least two wafers of differential signals to the ADF++ connector for a total of at least eight differential pairs of signal connections.

REQ 5.107.1The differential signal pairs for the 100GBASE-KR4 Front Board test card shall reside on adjacent wafers.

REQ 5.108 In order to meet the stringent skew requirements of 100GBASE-KR4, 100GBASE-KR4 Front Board test card differential skew shall be less than 6 ps. This figure includes signal path length, manufacturing and materials variations.

REQ 5.108.1Compliance to REQ 5.108 might be difficult to establish by direct measurement. For this reason, suppliers shall ensure REQ 5.108 is met by design.

REQ 5.109 100GBASE-KR4 Front Board test card signal paths shall have no vias except those terminating at the connectors.


¶ 280 The fitted attenuation for each signal path within the 100GBASE-KR4 Front Board test card with connectors removed is defined by Equation 73, Equation 74, and Table 5-20. This applies to measurements from TP 2/TP 3 to TP A as well as from TP A to TP 2/TP 3.

Equation 73.



Equation 74.



Table 5-20 Parameters for 100GBASE-KR4 Front Board test card fitted attenuation


m1 2.06E-10 f1 (Hz) 1.00E+09

b1 -0.076 f2 (Hz) 1.50E+10

m2 2.52E-10

b2 1.048

136 PICMG 3.1 R3.0, May 5, 2016


¶ 281 The fitted attenuation limits for the Front Board test card are shown in Figure 5-60, “Fitted attenuation limits for the 100GBASE-KR4 Front Board test card.”

Figure 5-60 Fitted attenuation limits for the 100GBASE-KR4 Front Board test card

Requirement

REQ 5.110 The fitted attenuation for each signal path within the 100GBASE-KR4 Front Board test card with connectors removed shall meet the limits Amin and Amax as defined by Equation 73, Equation 74, and Table 5-20 when measured from TP 2/TP 3 to TP A and when measured from TP A to TP 2/TP 3.


¶ 282 The insertion loss deviation (ILD) response for each signal path within the 100GBASE-KR4 Front Board test card with connectors removed is defined by Equation 75, Equation 76, and Table 5-21. This applies to measurements from TP 2/TP 3 to TP A as well as from TP A to TP 2/TP 3.

Equation 75.



Equation 76.



PICMG 3.1 R3.0, May 5, 2016 137


¶ 283 The maximum ILD limits for the 100GBASE-KR4 Front Board test card are shown in Figure 5-61, “Insertion loss deviation limits for the 100GBASE-KR4 Front Board test card.”

Figure 5-61 Insertion loss deviation limits for the 100GBASE-KR4 Front Board test card

Requirement

REQ 5.111 The insertion loss deviation (ILD) response for each signal path within the 100GBASE-KR4 Front Board test card with connectors removed shall fall between the worst-case insertion loss deviation limits, ILDmax+ and ILDmax-, as defined by Equation 75, Equation 76, and Table 5-21 when measured from TP 2/TP 3 to TP A and when measured from TP A to TP 2/TP 3.

5.6.3.3 Return loss at TP A

¶ 284 The return loss (RL) of the 100GBASE-KR4 Front Board test card with connectors removed, measured at TP A, is defined by Equation 77 and Table 5-22.

Equation 77.

RL > RLmin = m1 f + b1 for all frequencies between f1 and f2

Table 5-21 Parameters for 100GBASE-KR4 Front Board test card insertion loss deviation


m1 0.000 f1 (Hz) 1.00E+09

b1 -0.557 f2 (Hz) 1.50E+10

m2 0.000

b2 0.557

138 PICMG 3.1 R3.0, May 5, 2016


m2 f + b2 for all frequencies between f2 and f3

¶ 285 The RL limit is shown in Figure 5-62, “Return loss limit for the 100GBASE-KR4 Front Board test card at TP A.”

Figure 5-62 Return loss limit for the 100GBASE-KR4 Front Board test card at TP A

Requirement

REQ 5.112 The return loss (RL) of the 100GBASE-KR4 Front Board test card at TP A, with connectors removed, shall meet the return loss limit, RLmin, as defined by Equation 77 and Table 5-22.

5.6.3.4 Return loss at TP 2/TP 3

¶ 286 The return loss (RL) of the 100GBASE-KR4 Front Board test card at TP 2/TP 3, with connectors removed, is defined by Equation 78 and Table 5-23.

Equation 78.



Table 5-22 Parameters for 100GBASE-KR4 Front Board test card return loss at TP A


m1 -1.79E-09 f1 (Hz) 1.00E+07

b1 22.018 f2 (Hz) 7.00E+09

m2 -1.92E-10 f3 (Hz) 2.00E+10

b2 10.846

PICMG 3.1 R3.0, May 5, 2016 139


¶ 287 The RL limit is shown in Figure 5-63, “Return loss limit for 100GBASE-KR4 Front Board test card at TP 2/TP 3.”

Figure 5-63 Return loss limit for 100GBASE-KR4 Front Board test card at TP 2/TP 3

Requirements

REQ 5.113 The return loss (RL) of the 100GBASE-KR4 Front Board test card at TP 2/TP 3, with connectors removed, shall meet the return loss limit, RLmin, as defined by Equation 78 and Table 5-23.

5.6.3.5 Common mode return loss at TP A

¶ 288 The common mode return loss (CMRL) of the 100GBASE-KR4 Front Board test card at TP A, with connectors removed, is defined by Equation 79 and Table 5-24.

Equation 79.

CMRL > CMRLmin = m1 f + b1 for all frequencies between f1 and f2


Table 5-23 Parameters for 100GBASE-KR4 Front Board test card return loss at TP 2/TP 3


m1 -1.50E-09 f1 (Hz) 1.00E+07

b1 22.015 f2 (Hz) 6.00E+09

m2 -1.05E-10 f3 (Hz) 2.50E+10

b2 13.632

140 PICMG 3.1 R3.0, May 5, 2016


¶ 289 The CMRL limit is shown in Figure 5-64, “Common mode return loss limit for 100GBASE-KR4 Front Board test card at TP A.”

Figure 5-64 Common mode return loss limit for 100GBASE-KR4 Front Board test card at TP A

Requirements

REQ 5.114 The common mode return loss (CMRL) of the 100GBASE-KR4 Front Board test card at TP A, with connectors removed, shall meet the common mode return loss limit, CMRLmin, as defined by Equation 79 and Table 5-24.

5.6.3.6 Common mode return loss at TP 2/TP 3

¶ 290 The common mode return loss (CMRL) of the 100GBASE-KR4 Front Board test card at TP 2/TP 3, with connectors removed, is defined by Equation 80 and Table 5-25.

Equation 80.



Table 5-24 Parameters for 100GBASE-KR4 Front Board test card common mode return loss at TP A


m1 -9.30E-10 f1 (Hz) 1.00E+07

b1 12.009 f2 (Hz) 7.00E+09

m2 -2.31E-10 f3 (Hz) 2.00E+10

b2 7.115

PICMG 3.1 R3.0, May 5, 2016 141


¶ 291 The CMRL limit is shown in Figure 5-65, “Common mode return loss limit for 100GBASE-KR4 Front Board test card at TP 2/TP 3.”

Figure 5-65 Common mode return loss limit for 100GBASE-KR4 Front Board test card at TP 2/TP 3

Requirements

REQ 5.115 The common mode return loss (CMRL) of the 100GBASE-KR4 Front Board test card at TP 2/TP 3, with connectors removed, shall meet the common mode return loss limit, CMRLmin, as defined by Equation 80 and Table 5-25.

5.6.3.7 Common mode conversion loss TP 2/TP 3 to TP A

¶ 292 The common mode conversion loss (CMCL) of the 100GBASE-KR4 Front Board test card from TP 2/TP 3 to TP A, with connectors removed, is defined by Equation 81 and Table 5-26.

Equation 81.

CMCL > CMCLmin = m1 f + b1 for all frequencies between f1 and f2


Table 5-25 Parameters for 100GBASE-KR4 Front Board test card common mode return loss at TP 2/TP 3


m1 -5.72E-10 f1 (Hz) 1.00E+07

b1 11.006 f2 (Hz) 7.00E+09

m2 0.00E+00 f3 (Hz) 2.50E+10

b2 7.000

142 PICMG 3.1 R3.0, May 5, 2016


¶ 293 The CMCL limit is shown in Figure 5-66, “Common mode conversion loss limit for the 100GBASE-KR4 Front Board test card (TP 2/TP 3 to TP A).”

Figure 5-66 Common mode conversion loss limit for the 100GBASE-KR4 Front Board test card (TP 2/TP 3 to TP A)

Requirements

REQ 5.116 The common mode conversion loss (CMCL) of the 100GBASE-KR4 Front Board test card from TP 2/TP 3 to TP A, with connectors removed, shall meet the common mode conversion loss limit, CMCLmin, as defined by Equation 81 and Table 5-26.

5.6.3.8 Common mode conversion loss TP A to TP 2/TP 3

¶ 294 The common mode to differential mode conversion loss (CMCL or Sdc21) of the 100GBASE-KR4 Front Board test card from TP A to TP 2/TP 3, with connectors removed, is defined by Equation 82 and Table 5-27.

Equation 82.


Table 5-26 Parameters for 100GBASE-KR4 Front Board test card common mode conversion loss from TP 2/TP3 to TP A


m1 -1.36E-09 f1 (Hz) 1.00E+07

b1 30.014 f2 (Hz) 1.10E+10

m2 -7.14E-11 f3 (Hz) 2.50E+10

b2 15.786

PICMG 3.1 R3.0, May 5, 2016 143



¶ 295 The CMCL limit is shown in Figure 5-67, “Common mode conversion loss limit for 100GBASE-KR4 Front Board test card (TP A to TP 2/TP 3).”

Figure 5-67 Common mode conversion loss limit for 100GBASE-KR4 Front Board test card (TP A to TP 2/TP 3)

Requirements

REQ 5.117 The common mode conversion loss (CMCL or Sdc21) of the 100GBASE-KR4 Front Board test card from TP A to TP 2/TP 3, with connectors removed, shall meet the common mode conversion loss limit, CMCLmin, as defined by Equation 82 and Table 5-27.


¶ 296 The worst case insertion loss to crosstalk ratio (ICR) within the 100GBASE-KR4 Front Board test card with connectors removed is defined by Equation 83, Equation 84, and Table 5-28.

Table 5-27 Parameters for 100GBASE-KR4 Front Board test card common mode conversion loss from TP A to TP 2/TP 3


m1 -1.18E-09 f1 (Hz) 1.00E+07

b1 30.012 f2 (Hz) 1.10E+10

m2 0.00E+00 f3 (Hz) 2.50E+10

b2 17.000

144 PICMG 3.1 R3.0, May 5, 2016


Equation 83.



Equation 84.

ICR < ICRmax = m2 LOG10(f) + b2;


¶ 297 The ICR limits are shown in Figure 5-68, “Insertion loss to crosstalk ratio limits for 100GBASE-KR4 Front Board test card.”

Figure 5-68 Insertion loss to crosstalk ratio limits for 100GBASE-KR4 Front Board test card

Requirements

REQ 5.118 The worst case insertion loss to crosstalk ratio (ICR) within the 100GBASE-KR4 Front Board test card measured at TP A and TP 2/ TP 3, with connectors removed, shall meet the insertion loss to crosstalk ratio limits, ICRmax and ICRmin, as defined by Equation 83, Equation 84, and Table 5-28.

Note: The following crosstalk aggressors are defined for this measurement.

Table 5-28 Parameters for 100GBASE-KR4 Front Board test card insertion loss to crosstalk ratio


m1 2.19E+01 f1 (Hz) 5.00E+08

b1 248.143 f2 (Hz) 1.25E+10

m2 2.08E+01

b2 254.821

PICMG 3.1 R3.0, May 5, 2016 145


Case 1:Victim: AB2 at the TP 2/TP 3 testpoint side of the test card.FEXT: AB1 and AB3 at the TP A testpoint side of the test card.

Case 2:Victim: CD2 at the TP A testpoint side of the test card.FEXT: CD1 and CD3 at the TP 2/TP 3 testpoint side of the test card.NEXT: AB1, EF1, AB2, EF2, AB3, EF3 at the TP A testpoint side of the test card.

Case 3:Victim: EF2 at the TP 2/TP 3 testpoint side of the test card.FEXT: EF1 and EF3 at the TP A testpoint side of the test card.

Case 4:Victim: GH2 at the TP A testpoint side of the test card.FEXT: GH1 and GH3 at the TP 2/TP 3 testpoint side of the test card.NEXT: EF1, EF2, EF3 at the TP A testpoint side of the test card.

5.6.4 100GBASE-KR4 Backplane test paddle card requirements

¶ 298 The PICMG 3.1 100GBASE-KR4 Backplane test paddle card is used in conjunction with a 100GBASE-KR4 Backplane test assembly in order to perform validation of PICMG 3.1-compliant Boards. In addition, 100GBASE-KR4 Backplane test paddle cards are used to validate PICMG 3.1-compliant Backplanes. The 100GBASE-KR4 Backplane test paddle card contains one ADF++ Board connector connected by differential signals to several connectors/probe points. The 100GBASE-KR4 Backplane test paddle card provides a controlled reference by which Board measurements can be made. A representative 100GBASE-KR4 Backplane test paddle card is shown in Figure 5-69, “Example 100GBASE-KR4 Backplane test paddle card.” Although RP-SMA connectors are shown in this figure, the actual connector/probe point design is not dictated by this specification.

Figure 5-69 Example 100GBASE-KR4 Backplane test paddle card

¶ 299 Due to the high speed nature of 100GBASE-KR4 signals, industry best practices will need to be applied to the implementation of the 100GBASE-KR4 Backplane test paddle card. In particular, care will need to be taken to minimize the number of vias and length of via stubs in order to meet the requirements outlined in this section.

146 PICMG 3.1 R3.0, May 5, 2016


¶ 300 In order to avoid over-specification and promote vendor differentiation, the majority of the 100GBASE-KR4 Backplane test paddle card requirements are given as electrical values. Exact implementation, including mechanical and material options, is not dictated by this specification.

¶ 301 Figure 5-70, “Test Point locations for the 100GBASE-KR4 Backplane test paddle card ” shows the defined test point locations used for the 100GBASE-KR4 Backplane paddle card. The test points are described in Table 5-29, “Description of the 100GBASE-KR4 Backplane test paddle card test points.” Unless otherwise specified, all 100GBASE-KR4 Backplane paddle cards are defined between TP1/TP4 and TPB.

Figure 5-70 Test Point locations for the 100GBASE-KR4 Backplane test paddle card

Table 5-29 Description of the 100GBASE-KR4 Backplane test paddle card test points


TP 1/TP 4A test point located between the SMA (or equivalent) connector and the test equipment. TP1 refers to transmit connections, TP4 corresponds to receive.

TP B

A test point located between the mated ADF++ connector and the test equipment. The test point is located at the position where the ADF++ connector pin would come in contact with the top surface of a PCB if it was installed in a PCB.

TP 1/TP 4 to TP B

The 100GBASE-KR4 Backplane Paddle Card Channel segment defined by PICMG 3.1. This Channel segment extends from the SMA (or equivalent connectors) through to the mated ADF++ connector pair.

PICMG 3.1 R3.0, May 5, 2016 147


¶ 302 In the interest of testability, it can be useful to make measurements between TP 1 and TP 4 using a loopback connection as shown in Figure 5-71, “Possible loopback measurement configuration for 100GBASE-KR4 Backplane test paddle card .” As long as the Channel from TP 1 to TP B and TP 4 to TP B are symmetrical, measurements can be divided by two to compute the values from TP 1 or TP 4 to TP B.

Figure 5-71 Possible loopback measurement configuration for 100GBASE-KR4 Backplane test paddle card

Requirements

REQ 5.119 The differential impedance of the 100GBASE-KR4 Backplane test paddle card shall be 100 Ohms +/-5 Ohms.

REQ 5.120 The 100GBASE-KR4 Backplane test paddle card shall terminate at an ADF++ connector at one end of the signal paths.

REQ 5.121 The 100GBASE-KR4 Backplane test paddle card shall implement the manufacturer’s recommended footprint for the ADF++ connector.

REQ 5.122 The 100GBASE-KR4 Backplane test paddle card shall include at least two wafers of differential signals to the ADF++ connector for a total of at least eight differential pairs of signal connections.

REQ 5.122.1The differential signal pairs on the 100GBASE-KR4 Backplane test paddle card shall reside on adjacent wafers.

REQ 5.122.2The 100GBASE-KR4 Backplane test paddle card differential signal path lengths shall compensate for propagation time differences within the ADF++ connector.

REQ 5.123 In order to meet the stringent skew requirements of 100GBASE-KR4, Backplane test paddle card differential skew shall be less than 6 ps. This figure includes connector, signal path length, manufacturing and materials variations.


148 PICMG 3.1 R3.0, May 5, 2016


REQ 5.124 100GBASE-KR4 Backplane test paddle card signal paths shall have no vias except those terminating at the connectors.


¶ 303 The fitted attenuation for each signal path within the 100GBASE-KR4 Backplane test paddle card, including the mated ADF++ connector, is defined by Equation 85, Equation 86, and Table 5-30. This applies to measurements from TP 1/TP 4 to TP B as well as from TP B to TP 1/TP 4.

Equation 85.



Equation 86.



¶ 304 The fitted attenuation limits for the Backplane test paddle card are shown in Figure 5-72, “Fitted attenuation limits for the 100GBASE-KR4 Backplane test paddle card.”

Table 5-30 Parameters for 100GBASE-KR4 Backplane test paddle card fitted attenuation


m1 5.922E-10 f1 (Hz) 1.00E+09

b1 0.134 f2 (Hz) 1.50E+10

m2 7.663E-10

b2 1.225

PICMG 3.1 R3.0, May 5, 2016 149


Figure 5-72 Fitted attenuation limits for the 100GBASE-KR4 Backplane test paddle card

Requirements

REQ 5.125 The fitted attenuation for each signal path within the 100GBASE-KR4 Backplane test paddle card, including the mated ADF++ connector, shall meet the limits Amin and Amax as defined by Equation 85, Equation 86, and Table 5-30 when measured from TP 1/TP 4 to TP B and when measured from TP B to TP 1/TP 4.


¶ 305 The insertion loss deviation (ILD) response for each signal path within the 100GBASE-KR4 Backplane test paddle card, including the mated ADF++ connector, is defined by Equation 87, Equation 88, and Table 5-31. This applies to measurements from TP 1/TP 4 to TP B as well as from TP B to TP 1/TP 4.

Equation 87.



Equation 88.



150 PICMG 3.1 R3.0, May 5, 2016


¶ 306 The maximum ILD limits for the 100GBASE-KR4 Backplane test paddle card are shown in Figure 5-73, “Insertion loss deviation limits for 100GBASE-KR4 Backplane test paddle card.”

Figure 5-73 Insertion loss deviation limits for 100GBASE-KR4 Backplane test paddle card

Requirements

REQ 5.126 The insertion loss deviation (ILD) response for each signal path within the 100GBASE-KR4 Backplane test paddle card, including the mated ADF++ connector, shall fall between the worst-case insertion loss deviation limits, ILDmax+ and ILDmax-, as defined by Equation 87, Equation 88, and Table 5-31. This applies to measurements from TP 1/TP 4 to TP B as well as from TP B to TP 1/TP 4.

5.6.4.3 Return loss at TP B

¶ 307 The return loss (RL) of the 100GBASE-KR4 Backplane test paddle card, including the mated ADF++ connector, at TP B is defined by Equation 89 and Table 5-32.

Equation 89.


Table 5-31 Parameters for 100GBASE-KR4 Backplane test paddle card insertion loss deviation


m1 -2.515E-11 f1 (Hz) 1.00E+09

b1 -1.034 f2 (Hz) 1.50E+10

m2 2.515E-11

b2 1.034

PICMG 3.1 R3.0, May 5, 2016 151



¶ 308 The RL limit is shown in Figure 5-74, “Return loss limits for the 100GBASE-KR4 Backplane test paddle card at TP B.”

Figure 5-74 Return loss limits for the 100GBASE-KR4 Backplane test paddle card at TP B

Requirements

REQ 5.127 The return loss (RL) of the 100GBASE-KR4 Backplane test paddle card, including the mated ADF++ connector, measured at TP B shall meet the return loss limit, RLmin as defined by Equation 89 and Table 5-32.

5.6.4.4 Return loss at TP 1/TP 4

¶ 309 The return loss (RL) of the 100GBASE-KR4 Backplane test paddle card, including the mated ADF++ connector, measured at TP 1/TP 4 is defined by Equation 90 and Table 5-33.

Equation 90.



Table 5-32 Parameters for 100GBASE-KR4 Backplane test paddle card return loss at TP B


m1 -1.836E-09 f1 (Hz) 1.00E+07

b1 21.018 f2 (Hz) 6.00E+09

m2 -6.071E-10 f3 (Hz) 2.00E+10

b2 13.643

152 PICMG 3.1 R3.0, May 5, 2016


¶ 310 The RL limit is shown in Figure 5-75, “Return loss limits for 100GBASE-KR4 Backplane test paddle card at TP 1/TP 4.”

Figure 5-75 Return loss limits for 100GBASE-KR4 Backplane test paddle card at TP 1/TP 4

Requirements

REQ 5.128 The return loss (RL) of the 100GBASE-KR4 Backplane test paddle card, including the mated ADF++ connector, measured at TP 1/TP 4 shall meet the return loss limit, RLmin as defined by Equation 90 and Table 5-33.

5.6.4.5 Common mode return loss at TP B

¶ 311 The common mode return loss (CMRL) of the 100GBASE-KR4 Backplane test paddle card at TP B, including the mated ADF++ connector, is defined by Equation 91 and Table 5-34.

Equation 91.



Table 5-33 Parameters for 100GBASE-KR4 Backplane test paddle card return loss at TP 1/TP 4


m1 -1.253E-09 f1 (Hz) 1.00E+07

b1 21.013 f2 (Hz) 4.00E+09

m2 0.000E+00 f3 (Hz) 2.00E+10

b2 16.000

PICMG 3.1 R3.0, May 5, 2016 153


¶ 312 The CMRL limit is shown in Figure 5-76, “Common mode return loss limit for 100GBASE-KR4 Backplane test paddle card at TP B.”

Figure 5-76 Common mode return loss limit for 100GBASE-KR4 Backplane test paddle card at TP B

Requirements

REQ 5.129 The common mode return loss (CMRL) of the 100GBASE-KR4 Backplane test paddle card at TP B, including the mated ADF++ connector, shall meet the common mode return loss limit, CMRLmin, as defined by Equation 91 and Table 5-34.

5.6.4.6 Common mode return loss at TP 1/TP 4

¶ 313 The common mode return loss (CMRL) of the 100GBASE-KR4 Backplane test paddle card at TP 1/TP 4, including the mated ADF++ connector, is defined by Equation 92 and Table 5-35.

Equation 92.


Table 5-34 Parameters for 100GBASE-KR4 Backplane test paddle card common mode return loss at TP B


m1 -6.006E-10 f1 (Hz) 1.00E+07

b1 8.006 f2 (Hz) 1.00E+10

m2 -1.095E-10 f3 (Hz) 2.00E+10

b2 3.095

154 PICMG 3.1 R3.0, May 5, 2016


¶ 314 The CMRL limit is shown in Figure 5-77, “Common mode return loss limit for 100GBASE-KR4 Backplane test paddle card at TP 1/TP 4.”

Figure 5-77 Common mode return loss limit for 100GBASE-KR4 Backplane test paddle card at TP 1/TP 4

Requirements

REQ 5.130 The common mode return loss (CMRL) of the 100GBASE-KR4 Backplane test paddle card at TP 1/TP 4, including the mated ADF++ connector, shall meet the common mode return loss limit, CMRLmin, as defined by Equation 92 and Table 5-35.

5.6.4.7 Common mode conversion loss at TP 1/TP 4 to TP B

¶ 315 The common mode conversion loss (CMCL or Sdc21) of the 100GBASE-KR4 Backplane test paddle card, including the mated ADF++ connector, from TP 1/TP 4 to TP B is defined by Equation 93 and Table 5-36.

Equation 93.



Table 5-35 Parameters for 100GBASE-KR4 Backplane test paddle card common mode return loss at TP 1/TP 4


m1 0.000E+00 f1 (Hz) 1.00E+07

b1 8.000 f2 (Hz) 2.00E+10

PICMG 3.1 R3.0, May 5, 2016 155


¶ 316 The CMCL limit is shown in Figure 5-78, “Common mode conversion loss limit for the 100GBASE-KR4 Backplane test paddle card from TP 1/TP 4 to TP B.”

Figure 5-78 Common mode conversion loss limit for the 100GBASE-KR4 Backplane test paddle card from TP 1/TP 4 to TP B

Requirements

REQ 5.131 The common mode conversion loss (CMCL) of the 100GBASE-KR4 Backplane test paddle card, including the mated ADF++ connector, shall meet the common mode conversion loss limit, CMCLmin, as defined by Equation 93 and Table 5-36.

5.6.4.8 Common mode conversion loss TP B to TP 1/TP4

¶ 317 The common mode to differential mode conversion loss (CMCL or Sdc21) of the 100GBASE-KR4 Backplane test paddle card, including the mated ADF++ connector, from TP B to TP 1/TP 4 is defined by Equation 94 and Table 5-37.

Equation 94.


Table 5-36 Parameters for 100GBASE-KR4 Backplane test paddle card common mode conversion loss from TP 1/TP4 to TP B


m1 -3.076E-09 f1 (Hz) 1.00E+07

b1 40.031 f2 (Hz) 7.00E+09

m2 0.000E+00 f3 (Hz) 2.50E+10

b2 18.500

156 PICMG 3.1 R3.0, May 5, 2016



¶ 318 The CMCL limit is shown in Figure 5-79, “Common mode conversion loss limit for 100GBASE-KR4 Backplane test paddle card from TPB to TP 1/TP 4.”

Figure 5-79 Common mode conversion loss limit for 100GBASE-KR4 Backplane test paddle card from TPB to TP 1/TP 4

Requirement

REQ 5.132 The common mode conversion loss (CMCL or Sdc21)) of the 100GBASE-KR4 Backplane test paddle card from TO B to TP 1/TP 4, including the mated ADF++ connector, shall meet the common mode conversion loss limit, CMCLmin, as defined by Equation 94 and Table 5-37.


¶ 319 The worst case insertion loss to crosstalk ratio (ICR) within the 100GBASE-KR4 Backplane test paddle card, including the mated ADF++ connector, is defined by Equation 95, Equation 96, and Table 5-38.

Table 5-37 Parameters for 100GBASE-KR4 Backplane test paddle card common mode conversion loss from TP B to TP 1/TP4


m1 -3.076E-09 f1 (Hz) 1.00E+07

b1 40.031 f2 (Hz) 7.00E+09

m2 0.000E+00 f3 (Hz) 2.50E+10

b2 18.500

PICMG 3.1 R3.0, May 5, 2016 157


Equation 95.



Equation 96.

ICR < ICRmax = m2 LOG10(f) + b2


¶ 320 The ICR limits are shown in Figure 5-80, “Insertion loss to crosstalk ratio limits for the 100GBASE-KR4 Backplane test paddle card.”

Figure 5-80 Insertion loss to crosstalk ratio limits for the 100GBASE-KR4 Backplane test paddle card

Requirements

REQ 5.133 The worst case insertion loss to crosstalk ratio (ICR) within the Backplane test paddle card, including the mated ADF++ connector, shall meet the insertion loss to crosstalk ratio limits, ICRmax and ICRmin, as defined by Equation 95, Equation 96 and Table 5-38.

Table 5-38 Parameters for 100GBASE-KR4 Backplane test paddle card insertion loss to crosstalk ratio


m1 -1.228E+01 f1 (Hz) 5.00E+08

b1 153.767 f2 (Hz) 1.25E+10

m2 -2.278E+01

b2 270.151

158 PICMG 3.1 R3.0, May 5, 2016


Note: The following crosstalk aggressors are defined for this measurement.Case 1:

Victim: AB2 at the TP B testpoint side of the test card.FEXT: AB1 and AB3 at the TP 1/TP4 testpoint side of the test card.

Case 2:Victim: CD2 at the TP 1/TP 4 testpoint side of the test card.FEXT: CD1 and CD3 at the TP B testpoint side of the test card.NEXT: AB1, EF1, AB2, EF2, AB3, EF3 at the TP 1/TP4 testpoint side of the test card.

Case 3:Victim: EF2 at the TP B testpoint side of the test card.FEXT: EF1 and EF3 at the TP 1/TP 4 testpoint side of the test card.

Case 4:Victim: GH2 at the TP 1/TP 4 testpoint side of the test card.FEXT: GH1 and GH3 at the TP B testpoint side of the test card.NEXT: EF1, EF2, EF3 at the TP 1/TP 4 testpoint side of the test card.

5.6.5 Front Board Channel requirements

¶ 321 This section describes tests and requirements for PICMG 3.1 compliant Front Boards. These requirements are specific to signal paths that support 100GBASE-KR4 signaling (LCLASS 0100b). Channel requirements for signal paths of other signaling classes are governed by the PICMG 3.0 specification and other sections of this document.

¶ 322 Not all signal paths within a Front Board must comply with the specifications defined in this section; however, any LCLASS 0100b signal paths must meet all of the requirements given.

¶ 323 Due to the high speed nature of 100GBASE-KR4 signals, industry best practices will need to be applied to the implementation. In particular, care will need to be taken to minimize the number of vias and length of via stubs in order to meet the requirements outlined in this section.

¶ 324 In order to avoid over-specification and promote vendor differentiation, the majority of the Front Board requirements are given as electrical values. Exact implementation, including mechanical and material options, is not dictated by this specification.

Requirements

REQ 5.134 Each implemented LCLASS 0100b signal path shall be terminated with an IEEE compliant 100GBASE-KR4 transceiver.

REQ 5.135 The differential impedance of LCLASS 0100b signal paths within the Front Board shall be 100 Ohms +/- 10 Ohms.

REQ 5.136 LCLASS 0100b signal paths within a Front Board shall terminate at an ADF++ connector.

REQ 5.137 LCLASS 0100b differential signal path lengths shall compensate for propagation time differences within the ADF++ connector.

REQ 5.138 In order to meet the stringent skew requirements of 10GBASE-KR and 100GBASE-KR4, Front Board LCLASS 0100b differential skew shall be less than 6 ps. This figure includes connector, signal path length, manufacturing and materials variations.

PICMG 3.1 R3.0, May 5, 2016 159




¶ 325 The fitted attenuation for each LCLASS 0100b signal path within the Front Board, including mated ADF++ connectors, is defined by Equation 97 and Table 5-39, as specified from the transmitter pad to the Backplane side of the mated ADF++ connector pin.

Equation 97.



¶ 326 The fitted attenuation limit for the Front Board is shown in Figure 5-81, “Fitted attenuation limit for LCLASS 0100b signal paths in Front Board.”

Figure 5-81 Fitted attenuation limit for LCLASS 0100b signal paths in Front Board

Requirements

REQ 5.139 The Front Board fitted attenuation for each LCLASS 0100b signal path, including mated ADF++ connectors, shall meet the limits Amax as defined by Equation 97 and Table 5-39, as specified from the transmitter pad to the Backplane side of the mated ADF connector pin.

Table 5-39 Parameters for 100GBASE-KR4 Front Board fitted attenuation


m1 8.50E-10 f1 (Hz) 1.00E+09

b1 0.449 f2 (Hz) 1.50E+10

160 PICMG 3.1 R3.0, May 5, 2016


REQ 5.139.1Compliance to REQ 5.139 might be difficult to establish by direct measurement. For this reason, suppliers may ensure REQ 5.139 is met by simulation or design.

5.6.5.2 S-Parameter and jitter testing and requirements

¶ 327 Front Board S-parameter and jitter measurements are made using a PICMG 3.1 100GBASE-KR4 Front Board test card. The unit under test is inserted into the ADF++ connector on the test card and test equipment is connected to the Front Board test card. A representative unit under test and test card are shown in Figure 5-82, “Front Board Inserted into the 100GBASE-KR4 Front Board test card.” The tester will also need to provide power to the unit under test.

Figure 5-82 Front Board Inserted into the 100GBASE-KR4 Front Board test card

¶ 328 The recommended test setup for Front Board S-parameter and jitter tests is shown in Figure 5-83, “Recommended test setup for Front Board S-parameter and jitter tests.”

PICMG 3.1 R3.0, May 5, 2016 161


Figure 5-83 Recommended test setup for Front Board S-parameter and jitter tests

5.6.5.3 Return loss

¶ 329 The Return Loss (RL) for each Front Board LCLASS 0100b signal is defined by Equation 98 and Table 5-40, when measured at TP 2 and TP 3 of the 100GBASE-KR4 Front Board test card.

Equation 98.



¶ 330 The RL limit is shown in Figure 5-84, “Return loss limits for LCLASS 0100b signal paths in Front Board.”

Table 5-40 Parameters for 100GBASE-KR4 Front Board return loss


m1 -8.35E-10 f1 (Hz) 1.00E+07

b1 15.008 f2 (Hz) 6.00E+09

m2 -1.05E-10 f3 (Hz) 2.50E+10

b2 10.632

162 PICMG 3.1 R3.0, May 5, 2016


Figure 5-84 Return loss limits for LCLASS 0100b signal paths in Front Board

Requirements

REQ 5.140 The Return Loss (RL) for each Front Board LCLASS 0100b signal shall meet the return loss requirement given in Equation 98 and Table 5-40, when measured at TP 2 and TP 3 of the 100GBASE-KR4 Front Board test card.


¶ 331 The transmitter’s Common Mode Return Loss (CMRL) for each Front Board LCLASS 0100b Signal is defined in Equation 99 and Table 5-41, when measured at TP 2 of the Front Board test card.

Equation 99.



¶ 332 The CMRL limit is shown in Figure 5-85, “Common mode return loss limits for LCLASS 0100b signal paths in a Front Board.”

Table 5-41 Parameters for 100GBASE-KR4 Front Board common mode return loss


m1 -4.45E-10 f1 (Hz) 1.00E+07

b1 8.004 f2 (Hz) 4.50E+09

m2 0.00E+00 f3 (Hz) 2.50E+10

b2 6.000

PICMG 3.1 R3.0, May 5, 2016 163


Figure 5-85 Common mode return loss limits for LCLASS 0100b signal paths in a Front Board

Requirements

REQ 5.141 The transmitter’s Common Mode Return Loss (CMRL) for each Front Board LCLASS 0100b signal shall meet the transmitter’s common mode return loss requirements given in Equation 99 and Table 5-41, when measured at TP 2 of the 100GBASE-KR4 Front Board test card.

REQ 5.142 The maximum random jitter of any Front Board LCLASS 0100b signal shall be no more than 0.18 unit intervals (UI) when measured at TP 2 of the Front Board test card.

REQ 5.143 The maximum Duty Cycle Distortion (DCD) of any Front Board LCLASS 0100b signal shall be no more than 0.1 unit intervals (UI) when measured at TP 2 of the 100GBASE-KR4 Front Board test card or electrical equivalent.

REQ 5.144 The maximum total jitter excluding data dependent jitter (DDJ) of any Front Board LCLASS 0100b Link shall be no more than 0.035 unit intervals (UI) when measured at TP 2 of the 100GBASE-KR4 Front Board test card.

REQ 5.145 The signaling rate shall be in a range of 25.78125 +/- 100 ppm Gbd when measured at TP 2 of the 100GBASE-KR4 Front Board test card or electrical equivalent.

REQ 5.146 The Transmitter DC amplitude shall be greater than 0.3 V and less than or equal to 0.6 V when measured at TP 2 of the 100GBASE-KR4 Front Board test card or electrical equivalent.

REQ 5.147 The peak of the linear fit pulse response shall be greater than 0.71 × DC amplitude when measured at TP 2 of the 100GBASE-KR4 Front Board test card or electrical equivalent using the procedure of IEEE 802.3bj-2014.

5.6.5.5 Crosstalk and error rate testing and requirements

¶ 333 Crosstalk and bit error rate testing of Front Boards requires two fixture configurations to emulate the different Backplane environments into which the Board might be inserted.

164 PICMG 3.1 R3.0, May 5, 2016


¶ 334 The short Channel test fixture (or equivalent) is used to test Front Board behavior as it drives signals through a Channel that is similar to a short Backplane signal path. The short Channel test fixture consists of a 100GBASE-KR4 Backplane test paddle card inserted into a short 100GBASE-KR4 Backplane test assembly as shown in Figure 5-86, “Front Board transmit/receive setup with short 100GBASE-KR4 Backplane test assembly.”

Figure 5-86 Front Board transmit/receive setup with short 100GBASE-KR4 Backplane test assembly

¶ 335 The long Channel test fixture (or equivalent) is used to test Front Board behavior as it drives signals through a Channel that is similar to a long Backplane signal path. The long Channel test fixture consists of a 100GBASE-KR4 Backplane test paddle card inserted into a long 100GBASE-KR4 Backplane test assembly.

¶ 336 In the case of both the short and the long test fixtures, the unit under test is inserted into the empty ADF++ connector on the Backplane test assembly and a 100GBASE-KR4 Backplane test paddle card is inserted into the other connector. Test equipment is connected to the 100GBASE-KR4 Backplane test paddle card.

¶ 337 Some test fixtures may be capable of emulating the S-parameter characteristics of part or all of the above test fixtures. Alternatively the effects of test fixtures may be added to direct measurements through post-measurement computations. Either of these methods is allowed so long as the characteristics of the emulated/computed fixtures match the requirements found within this specification.

¶ 338 A recommended test setup for measurement of bit error rates is shown in Figure 5-87, “Recommended test setup for Front Board bit error rate testing.” This setup is based on the test setup defined in IEEE 802.3-2008. Alternate test setups may be required due to availability and maturity of test equipment, and the instrumentation of the receiver on the unit under test.

PICMG 3.1 R3.0, May 5, 2016 165


Figure 5-87 Recommended test setup for Front Board bit error rate testing

Requirements

REQ 5.148 Front Boards shall obtain a bit error rate of 10-12 or better when tested with a PICMG 3.1 100GBASE-KR4 Channel test fixture.

REQ 5.148.1Compliance to REQ 5.148 might be difficult to establish by direct measurement due to the maturity of test equipment. For this reason, suppliers may ensure REQ 5.148 is met by simulation.

REQ 5.149 Front Boards shall obtain a bit error rate of 10-12 or better when tested with a PICMG 3.1 long 100GBASE-KR4 Channel test fixture.

REQ 5.149.1Compliance to REQ 5.149 might be difficult to establish by direct measurement due to the maturity of test equipment. For this reason, suppliers may ensure REQ 5.149 is met by simulation.

5.6.5.6 Front Board Channel Operating Margin

¶ 339 IEEE 802.3BJ™ defines measurement and calculation methods to compute the Channel Operating Margin (COM) for compliant 100GBASE-KR4 Channels. PICMG 3.1 100GBASE-KR4 Boards must guarantee their operation within the normative IEEE COM limits, however, direct measurement over the full range of Backplane environments and companion Front Boards is not feasible. To facilitate validation, PICMG has made available simulation models for this purpose.

Requirements

REQ 5.150 LCLASS 0100b signal paths within the Front board shall have 3dB or more of Channel Operating Margin with any PICMG 3.1 compliant LCLASS 0100b Backplane signal paths and any PICMG 3.1 compliant LCLASS 0100b signal paths on a terminating Front Board as validated by simulation.

166 PICMG 3.1 R3.0, May 5, 2016


5.6.6 Backplane Channel requirements

¶ 340 This section describes tests and requirements for PICMG 3.1 compliant Backplanes. These requirements are specific to signal paths that support 100GBASE-KR4 signaling (LCLASS 0100b). Channel requirements for signal paths of other signaling classes are governed by the PICMG 3.0 or relevant subsidiary specification requirements.

¶ 341 Not all signal paths within a Backplane must comply with the specifications defined in this section, however, any LCLASS 0100b signal paths must meet all of the requirements given.

¶ 342 Due to the high speed nature of 100GBASE-KR4 signals, industry best practices will need to be applied to the implementation. In particular, care will need to be taken to minimize the number of vias and length of via stubs in order to meet the requirements outlined in this section.

¶ 343 In order to avoid over-specification and promote vendor differentiation, the majority of the Backplane Channel requirements are given as electrical values. Exact implementation, including mechanical and material options, is not dictated by this specification.

Figure 5-88 Test point locations for Backplane testing

¶ 344 The test setup includes a 100GBASE-KR4 Backplane test paddle card installed into the Backplane’s Zone 2 Connectors at each end of the Channel under test as shown in Figure 5-89, “Backplane test setup with two 100GBASE-KR4 Backplane test paddle cards.” Test equipment is connected directly to each of the 100GBASE-KR4 Backplane test paddle cards in order to make measurements.

¶ 345 Some test equipment may be capable of emulating the S-parameter characteristics of part or all of the mated paddle card assembly. Alternatively the effects of test fixtures may be added to direct measurements through post-measurement computations. Either of these methods is allowed so long as the characteristics of the emulated/computed fixtures match the test fixture characteristics found within this specification.

PICMG 3.1 R3.0, May 5, 2016 167


Figure 5-89 Backplane test setup with two 100GBASE-KR4 Backplane test paddle cards

Requirements

REQ 5.151 The differential impedance of LCLASS 0100b signal paths within the Backplane shall be 100 Ohms +/- 10 Ohms.

REQ 5.152 In order to meet the stringent skew requirements of 100GBASE-KR4, LCLASS 0100b Backplane signal path differential skew shall be less than 6 ps. This figure includes signal path length, manufacturing and materials variations.


REQ 5.153 LCLASS 0100b Backplane signal path S-parameter and crosstalk measurements shall be made between TP 1 and TP 4 of a connected 100GBASE-KR4 Backplane test paddle cards, or their electrical or computational equivalent, as defined in Figure 5-88, “Test point locations for Backplane testing.”

REQ 5.154 LCLASS 0100b signal paths for the entire Channel (including Backplane test paddle cards and Backplane) should meet or exceed insertion loss recommendations found in IEEE 802.3bj-2014, Section 93.9.2 (Insertion Loss).

REQ 5.155 LCLASS 0100b signal paths for the entire Channel (including Backplane test paddle cards and Backplane) should meet or exceed return loss recommendations found in IEEE 802.3bj-2014, Section 93.9.3 (Return Loss).

5.6.6.1 Backplane Channel Operating Margin

¶ 346 IEEE 802.3BJ™ defines measurement and calculation methods to compute the Channel Operating Margin (COM) for compliant 100GBASE-KR4 Channels. PICMG 3.1 100GBASE-KR4 Boards must guarantee their operation within the normative IEEE COM limits, however, direct measurement over the full range of Backplane environments and companion Front Boards is not feasible. To facilitate validation, PICMG has made available simulation models for this purpose.

168 PICMG 3.1 R3.0, May 5, 2016


Requirements

REQ 5.156 LCLASS 0100b signal paths within the Backplane shall have 3dB or more of Channel operating margin with any PICMG 3.1 compliant LCLASS 0100b signal paths on terminating Front Boards as validated by simulation.

PICMG 3.1 R3.0, May 5, 2016 169


170 PICMG 3.1 R3.0, May 5, 2016

Advanced Differential Fabric connector generation 2 Definition - ADFplus (normative)

Advanced Differential Fabric connector generation 2 Definition - ADFplus (normative) A

A.1 General data

¶ 347 This appendix specifies the second generation of the AdvancedTCA Zone 2 Connector to the fullest extent possible without infringing on intellectual property that is not available for license under reasonable and non-discriminatory terms in accordance with PICMG policy. In PICMG 3.0, Section 2, REQ 2.302 refers to the whole of PICMG 3.0 Appendix A. REQ 2.2 on page 9 of this specification refers to the whole of this appendix. Therefore, the information provided in this appendix is normative for the design of the Zone 2 ADFplus Connector for the PICMG 3.1 specification.

A.1.1 Objective of this Appendix

¶ 348 The objective of this appendix is to provide information to be used to specify the Advanced Differential Fabric connector generation 2 (ADFplus) for PICMG applications that are intermatable with ADF connectors.

A.1.2 Scope

¶ 349 This appendix’s structure is modeled after the structure of PICMG 3.0 Appendix A in order to allow for easiest handling. Therefore, this appendix covers both the Backplane connector and the Front Board connector. As there is only a Front Board connector available as an ADFplus connector, refer to Appendix A in PICMG 3.0 for definitions of the Backplane connector.

¶ 350 This appendix provides information regarding the design requirements for compatible applications and mechanical and electrical performance requirements. The appendix is meant to be a general design guide for product intermatability and performance. The approach is to define the true position of the contacts and blades in the header, the aperture in the Front Board connector, the mating condition, the PCB layout patterns and the electrical performance requirements. The design of a compliant connector and the additional information required will be the responsibility of the connector manufacturer. Because some characteristics of the connector system are dependent on design it is desirable that a given Front Board be assembled with connectors of only one design. The same advice ought to be followed for populating a single Slot in a Backplane. This will ensure the most uniformity in performance be achieved. The electrical requirements set forth in Section 8, “Zone 2 electrical design guidelines” of PICMG 3.0 and the mechanical requirements set forth in Section 2, “Mechanical” of PICMG 3.0 must serve as the overall requirements for functionality. Requirements for testing are set forth in this appendix. In the event additional information is required, it will be the responsibility of the connector manufacturer and can be determined by agreement between the manufacturer and the user.

PICMG 3.1 R3.0, May 5, 2016 171


¶ 351 The ADFplus connector is fully mating compatible with the ADF connector. There is no Backplane version of the ADFplus connector available. Backplanes – even those with capabilities exceeding LCLASS = 0000b – are populated with ADF connector headers.

¶ 352 The Front Board connector features a new, different printed wiring board footprint. Through this optimized footprint the mated connector’s greatly improved performance has been achieved.

A.1.3 Intended method of mounting

¶ 353 Refer to the respective subsection of PICMG 3.0 Appendix A for the relevant information.

A.1.4 Ratings and characteristics


A.1.5 Normative references


A.1.6 Markings


A.2 Technical information

A.2.1 Definitions

¶ 357 For definitions, refer to section Section 1.8, “Acronyms and definitions” on page 6.

A.2.1.1 Contacts and terminations


A.2.1.2 Complete connectors (pairs)


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A.3 Dimensional information

A.3.1 General isometric view and common features

Figure A-1 View of Zone 2 Connectors with common features

A.3.2 Engagement information

¶ 360 The ADFplus connector is fully mating compatible with the ADF connector. Refer to the respective subsection of PICMG 3.0 Appendix A for the relevant information.

A.3.3 Backplane connectors

¶ 361 There is no Backplane version of the ADFplus connector available. Backplanes – even those with capabilities exceeding LCLASS = 0000b – are populated with ADF connector headers.

¶ 362 For all information on the ADF connector header for Backplanes, refer to PICMG 3.0 Appendix A.

PICMG 3.1 R3.0, May 5, 2016 173


A.3.4 Front Board connectors

A.3.4.1 Dimensions

Requirements

REQ A.1 As ADFplus connectors have a different footprint than ADF connectors, the dimensional information in PICMG 3.0 Figure 2-6 is not accurate for systems using ADFplus connectors. When ADFplus connectors are used, the dimensions shown in Figure A-2, “Dimensional drawing for ADFplus connectors” shall be used in place of the dimensions shown in PICMG 3.0 Figure 2-6.

174 PICMG 3.1 R3.0, May 5, 2016


Figure A-2 Dimensional drawing for ADFplus connectors

PICMG 3.1 R3.0, May 5, 2016 175


Figure A-3 Dimensional drawing of ADFplus Front Board connectors

A.3.4.2 Terminations

Requirements

REQ A.2 The current standard pressfit terminal length for the Front Board connectors shall be 1.7 mm.

A.3.5 Mounting information for Backplane connectors


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A.3.6 Mounting information for ADFplus Front Board connectors

Figure A-4 Front Board connector mounting

A.4 Characteristics

¶ 364 Connectors must meet the performance requirements outlined in the following subsections.

A.4.1 Climatic category

Requirements

REQ A.3 ADFplus connectors shall be tested against requirements valid for the ADF connectors. For all information on ADFplus environmental testing refer the relevant section of PICMG 3.0 Appendix A.

PICMG 3.1 R3.0, May 5, 2016 177


A.4.2 Electrical characteristics

Table A-1 Electrical characteristics

A.4.2.1 Impedance

Requirements

REQ A.4 Impedance shall be measured differentially with a TDR on fully mated connector pairs comprised of one ADF Backplane connector and one ADFplus Front Board connector at edge rates specified in Table A-1, “Electrical characteristics” item 1.

REQ A.5 All directly neighboring signal pairs to a pair under test – either in the same wafer or in neighboring wafers (up to eight pairs depending on signal pair location) – shall be terminated with 50 Ohms to GND at both ends (16 terminators on each end).

REQ A.6 The transmission path relevant for specified impedance values stretches from the Front Board’s top surface to the Backplane’s top surface in either direction. Measured impedance values shall be within limits specified in Table A-1, “Electrical characteristics” for the relevant transmission path.

Figure A-5 Pair under test (shaded light yellow) with 8 neighboring pairs

\

ITEM Characteristic and Condition Specification

Impedance (differential pairs ab, cd, ef, gh)

1 50 ps Edge Rate (20-80%) 100 8%

Crosstalk Noise

2 NEN - Worst-Case Multi-Aggressor < 2.75% @ 50 ps

3 FEN - Worst-Case Multi-Aggressor < 2.50% @ 50 ps

4 Insertion Loss < 3dB @ 10 GHz and below

178 PICMG 3.1 R3.0, May 5, 2016


A.4.2.2 Crosstalk

¶ 365 The crosstalk percentage is calculated as follows: crosstalk peak-to-peak voltage/stimulation signal peak-to-peak voltage * 100 in percent.

Requirements

REQ A.7 Crosstalk shall be measured differentially in time-domain on fully mated connector pairs comprised of one ADF Backplane connector and one ADFplus Front Board connector at edge rate specified in Table A-1, “Electrical characteristics” items 2 and 3.

REQ A.8 All directly neighboring signal pairs (aggressor pairs) to a pair under test (victim) – either in the same wafer or in neighboring wafers (up to eight pairs) – shall be terminated with 50 Ohms to GND on both ends.

REQ A.9 All aggressors shall be stimulated with the same signal amplitude.

REQ A.10 Stimulation of aggressor pairs shall be in a way that obtains worst-case multi-aggressor crosstalk amplitude.

REQ A.11 The result values for near-end and far-end crosstalk shall be within limits specified in Table A-1, “Electrical characteristics”.

Figure A-6 Victim pair (shaded light yellow) with surrounding aggressors

A.4.2.3 Insertion loss

Requirements

REQ A.12 Insertion loss shall be measured differentially on fully mated connector pairs consisting of one ADF Backplane connector and one ADFplus Front Board connector from Backplane top surface plane to Front Board top surface plane or vice versa.

REQ A.13 All directly neighbored signal pairs to a pair under test – either in the same wafer or in neighbored wafers (up to eight pairs) – shall be terminated with 50 Ohms against GND on both ends.

REQ A.14 Measured insertion loss values shall be within limits specified in Table A-1, “Electrical characteristics” for the relevant transmission path.

PICMG 3.1 R3.0, May 5, 2016 179


A.4.2.4 Intra-pair skew (differential skew)

¶ 366 The transmission path relevant for specified differential skew stretches from the Front Board’s top surface to the Backplane’s top surface in either direction.

Table A-2 Intra-pair skew

Requirements

REQ A.15 Intra-pair skew shall be measured differentially on fully mated connector pairs comprised of one ADF Backplane connector and one ADFplus Front Board connector at an edge rate of 50 ps.

REQ A.16 All directly neighboring signal pairs to a pair under test – either in the same wafer or in neighboring wafers (up to eight pairs depending from signal pair location) – shall be terminated with 50 Ohms to GND at both ends (16 terminators on each end).

REQ A.17 Measured skew values shall be within the limits specified in Table A-2, “Intra-pair skew” for the relevant transmission path.

Figure A-7 Pair under test (shaded light yellow) with 8 neighboring pairs

Item Circuit ID (pair) Skew

1 AB Pair ≤ 5 ps

2 CD Pair ≤ 5 ps

3 EF pair ≤ 5 ps

4 GH pair ≤ 5 ps

180 PICMG 3.1 R3.0, May 5, 2016

Advanced Differential Fabric connector generation 3 Definition - ADF++ (normative)

Advanced Differential Fabric connector generation 3 Definition - ADF++ (normative) B

B.1 General data

¶ 367 This appendix specifies the third generation of the AdvancedTCA Zone 2 Connector to the fullest extent possible without infringing on intellectual property right that is not available for license under reasonable and non-discriminatory terms in accordance with PICMG policy. In PICMG 3.0, Section 2, REQ 2.302 refers to the whole of PICMG 3.0 Appendix A. REQ 2.2 on page 9 of this specification refers to the whole of this appendix. Therefore, the information provided in this appendix is normative for the design of the Zone 2 ADF++ Connector for the PICMG 3.1 specification.

B.1.1 Objective of this Appendix

¶ 368 The objective of this appendix is to provide information to be used to specify the Advanced Differential Fabric connector generation 3 (ADF++) for PICMG applications that are intermateable with ADF connectors and ADFplus connectors.

B.1.2 Scope

¶ 369 This appendix’s structure is modeled after the structure of PICMG 3.0 Appendix A in order to allow for easiest handling. Therefore, this appendix covers both the Backplane connector and the Front Board connector. There is a Front Board connector and a Backplane connector available as an ADF++ connector.

¶ 370 This appendix provides information regarding the design requirements for compatible applications and mechanical and electrical performance requirements. The appendix is meant to be a general design guide for product intermateability and performance. The approach is to define the true position of the contacts and blades in the header, the aperture in the Front Board connector, the mating condition, the PCB layout patterns and the electrical performance requirements. The design of a compliant connector and the additional information required is the responsibility of the connector manufacturer. Because some characteristics of the connector system are dependent on design, it is desirable that a given Front Board be assembled with connectors of only one design. The same advice ought to be followed for populating a single Slot in a Backplane. This will ensure the most uniformity in performance be achieved.

¶ 371 The electrical requirements set forth in Section 8, “Zone 2 electrical design guidelines” of PICMG 3.0 and the mechanical requirements set forth in Section 2, “Mechanical” of PICMG 3.0 must serve as the overall requirements for functionality. Requirements for testing are set forth in this appendix. In the event additional information is required, it will be the responsibility of the connector manufacturer and can be determined by agreement between the manufacturer and the user.

PICMG 3.1 R3.0, May 5, 2016 181


¶ 372 The ADF++ connector is fully mating compatible with both the ADF connector and the ADFplus connectors.

¶ 373 The Front Board and Backplane connector features a new, different printed wiring Board footprint. Through this optimized footprint the mated connector’s greatly improved performance has been achieved. The electrical requirements laid down in Section 5, “Backplane physical layer interfaces” on page 63 of this specification (PICMG 3.1 Rev 3.0) serve as overall guidelines beyond PICMG 3.0 for Channel functionality and defines electrical requirements for both Front Boards and Backplanes.

¶ 374 On compliance:

• Compliant ADF++ connectors from different vendors are allowed to have their own specific PCB footprint layouts and respective termination arrangements. However, to be compliant they physically must be fully backward and cross-compatible, must respect the outer contours defined with ADF and ADFplus, and electrically must comply with the limits and margins of this specification.

• One result of this is that ADF++ connectors from different manufacturers may not be able to replace each other on the manufacturing floor and in repair operations.

• Connector positions on Front Boards and Backplanes are solely described and specified by the nominal position of a virtual pin B1, which is identical to the nominal position of an ADF connector’s pin B1.

• Customers are asked to request drawings from connector manufacturers that show a virtual pin B1 position or relative positional information.

B.1.3 Intended method of mounting


B.1.4 Ratings and characteristics

¶ 376 Refer to the respective subsection of PICMG 3.0 Appendix A for the relevant information that is not provided within the contents of this appendix.

B.1.5 Normative references


B.1.6 Markings

¶ 378 For ADFplus connectors there are no binding requirements for markings on the connectors. Connector manufacturers, however, are free to apply markings for certain pins, pin rows or pin columns as long as these are not in contradiction to requirements set forth in any revision of PICMG 3.0, PICMG 3.1, or their respective appendices related to ADF and ADFplus connectors.

182 PICMG 3.1 R3.0, May 5, 2016


B.2 Technical information

B.2.1 Definitions

¶ 379 For definitions, refer to section Section 1.8, “Acronyms and definitions” on page 6.

B.2.1.1 Contacts and terminations


B.2.1.2 Complete connectors (pairs)


B.3 Dimensional information

B.3.1 General isometric view and common features

¶ 382 This section has been included solely to retain the same structure as Appendix A. This section has been intentionally left blank.

B.3.2 Engagement information

¶ 383 The ADF++ connector is fully mating compatible with the ADF and the ADFplus connectors. Refer to the respective subsection of PICMG 3.0 Appendix A for ADF and this document’s Appendix A, “Advanced Differential Fabric connector generation 2 Definition - ADFplus (normative)” for ADFplus in order to find the relevant information.

¶ 384 However, in order to enable their superior performance, ADF++ connectors feature reduced pin lengths and shields are allowed to deviate from the L-shape as long as safe mating and cross-mating can be guaranteed by a manufacturer.

B.3.2.1 Electrical engagement length

¶ 385 Front Board connectors according to this appendix are required to have the same mechanical contact point position as specified for ADF and ADFplus connector in above-mentioned specification. The spectrum of pin lengths offered by a manufacturer under the scope of this appendix is solely at the discretion of a manufacturer.

¶ 386 Users of ADF++ connectors are therefore asked to carefully check with the respective manufacturers to check if the chosen Backplane connector’s pin lengths, first contact points, and wipe lengths can serve the purpose of their ATCA Shelf from a mechanical and electrical mating perspective.

B.3.2.2 First contact point

¶ 387 Not defined for ADF++ connectors - refer to the information provided in the above sections.

PICMG 3.1 R3.0, May 5, 2016 183


B.3.2.3 Perpendicular to engagement direction


B.3.2.4 Inclination


B.3.3 Backplane connectors

¶ 390 There is an ADF++ connector existing for Backplanes that comply with PICMG 3.1 Rev.3.0. Also refer to explanations above.

¶ 391 Requirements for the ADF++ Backplane connectors are defined in the following subsections.

B.3.3.1 Dimensions

¶ 392 For any dimensional information of the header’s mating face or the outer contour refer to PICMG 3.0 Appendix A.

B.3.3.2 Contacts

¶ 393 Refer to the respective subsection of PICMG3.0 Appendix A for information about contacts. Also note the remarks above.

B.3.3.3 Contact tip geometry


B.3.3.4 Terminations

¶ 395 There are no requirements defined in this appendix that specify lengths of terminals or finished hole sizes needed for terminals. Both are to be agreed upon between connector manufacturers and their customers.

B.3.4 Front Board connectors

B.3.4.1 Dimensions

¶ 396 Like ADFplus connectors, ADF++ connectors do have a different footprint than ADF connectors, the dimensional information in PICMG 3.0 Figure 2-6 is not accurate for systems using ADF++ connectors. Despite specifying another pin B1 position in a drawing, this appendix follows the concept of a virtual pin B1 as a datum for ADF++ connector placement. Refer to subsection Section B.1.1, “Objective of this Appendix” on page 181 for further information.

¶ 397 For any dimensional information refer to the respective subsection of PICMG 3.0 Appendix A.

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B.3.4.2 Terminations

¶ 398 There are no requirements defined in this appendix that specify lengths of terminals or finished hole sizes needed for terminals. Both are to be agreed upon between connector manufacturers and their customers.

B.3.5 Mounting information for ADF++ Backplane connectors

¶ 399 Compliant ADF++ Backplane connectors from different vendors are allowed to have specific PCB footprint layouts. No information is provided in this appendix, though. This appendix follows the concept of a virtual pin B1 as a datum for ADF++ connector placement.

B.3.6 Mounting information for ADF++ Front Board connectors

¶ 400 Compliant ADF++ Front Board connectors from different vendors are allowed to have specific PCB footprint layouts. No information is provided in this appendix, though. This appendix follows the concept of a virtual pin B1 as a datum for ADF++ connector placement.

B.4 Characteristics

¶ 401 Connectors must meet the performance requirements outlined in the following subsections.

B.4.1 Climatic category

Requirements

REQ B.1 ADF++ connectors shall be type tested against requirements valid for the ADF connectors. For all information on ADF++ environmental testing refer the respective section of PICMG 3.0 Appendix A.

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B.4.2 Electrical characteristics

Table B-1 Electrical characteristics

B.4.2.1 General Remarks

¶ 402 In below illustrations GND pins are shown as one circle filled red. The actual connector may have more than one GND pin in such a location.

Requirements

REQ B.2 All frequency domain measurements shall be taken with reference planes at the top surface of the PCB directly under the connector bodies.

REQ B.3 ADF++ connectors may come from different vendors and may deviate in their PCB footprints. “Mated connector Pairs” in the course of this appendix therefore may not only be comprised from headers and receptacles from one vendor but also include cross-mated combinations with headers and receptacles from different manufacturers.

REQ B.4 Connector vendors shall guarantee that their offerings also meet the requirements set forth in this appendix in header-receptacle combinations where one of the mated components was produced by a third party.

B.4.2.2 Impedance

Requirements

REQ B.5 Impedance shall be measured differentially with a TDR on fully mated connector pairs comprised of one ADF++ Backplane connector and one ADF++ Front Board connector at edge rates specified in Table B-1, “Electrical characteristics” item 1 above.

REQ B.6 All directly neighboring signal pairs to a pair under test – either in the same layer or in neighboring layers (up to eight pairs depending on signal pair location) – shall be terminated with 50 Ohms to GND at both ends (16 terminators on each end).

REQ B.7 The transmission path relevant for specified impedance values stretches from the Front Board’s top surface to the Backplane’s top surface in either direction. Measured

ITEM Characteristic and Condition Specification

Impedance (differential pairs ab, cd, ef, gh)

1 50 ps Edge Rate (20-80%) 100 8%

Crosstalk Noise

2 NEN - Power Sum Multi-Aggressor Section B.4.2.3

3 Insertion Loss Section B.4.2.4

4 Differential Skew Section B.4.2.5

5 Return Loss Section B.4.2.6

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impedance values shall be within limits specified in Table B-1, “Electrical characteristics” for the relevant transmission path.

Figure B-1 Pair under test (shaded light yellow and surrounded) with 8 neighboring pairs

\

B.4.2.3 Crosstalk

¶ 403 Despite previous appendices of PICMG 3.1, this version employs a limit band in frequency domain and has abandoned time domain characteristics for crosstalk. All limits are expressed in dB.

Requirements

REQ B.8 Near-end crosstalk is used as the definitive characteristic to be used for compliance testing. Near-end crosstalk shall be measured differentially in frequency domain on fully mated connector pairs comprised of one ADF++ Backplane connector and one ADF++ Front Board connector between reference planes at the top surfaces of the PCBs directly under the connector bodies.

REQ B.9 All directly neighboring signal pairs (aggressor pairs) to a pair under test (victim pair) - either in the same layer or in the neighboring layers (up to eight pairs) - shall be terminated with 50 Ohms to GND on both ends.

REQ B.10 The power sum of all directly neighboring signal pairs (aggressor pairs) to a pair under test (victim pair) – either in the same layer or in neighboring layers (up to eight pairs) – produces the measurement result. The values of the measurement result shall be below the limit curve for all frequencies. Measurements shall be taken in the frequency range from 10 MHz to 20 GHz in 10 MHz steps.

PICMG 3.1 R3.0, May 5, 2016 187


Figure B-2 Power sum near-end crosstalk

Figure B-3 Victim pair (shaded light yellow and surrounded) with surrounding aggressors

B.4.2.4 Insertion loss

Requirements

REQ B.11 Insertion loss shall be measured differentially on fully mated connector pairs consisting of one ADF++ Backplane connector and one ADF++ Front Board connector from the Backplane top surface plane to Front Board top surface plane or vice versa.

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REQ B.12 All directly neighboring signal pairs to a pair under test – either in the same layer or in neighboring layers (up to eight pairs) – shall be terminated with 50 Ohms against GND on both ends.

REQ B.13 Measured insertion loss values shall be above the limit curve shown in Figure B-4, “Measured insertion loss limits” below for all frequencies for the relevant transmission path.

Figure B-4 Measured insertion loss limits

B.4.2.5 Intra-pair skew (differential skew)

Table B-2 Intra-pair skew

Requirements

REQ B.14 Intra-pair skew shall be measured differentially on fully mated connector pairs comprised of one ADF++ Backplane connector and one ADF++ Front Board connector at an edge rate of 50 ps.

Item Circuit ID (pair) Skew

1 AB Pair -1.2ps…+3ps

2 CD Pair -1.2ps…+3ps

3 EF pair -1.2ps…+3ps

4 GH pair -1.2ps…+3ps

PICMG 3.1 R3.0, May 5, 2016 189


REQ B.15 All directly neighboring signal pairs to a pair under test – either in the same layer or in neighboring layers (up to eight pairs depending from signal pair location) – shall be terminated with 50 Ohms to GND at both ends (16 terminators on each end).

REQ B.16 The transmission path relevant for specified differential skew stretches from the Front Board’s top surface to the Backplane’s top surface in either direction. Measured skew values shall be within the limits specified in Table B-2, “Intra-pair skew” above for the relevant transmission path.


B.4.2.6 Return loss

Requirements

REQ B.17 Return loss shall be measured differentially on fully mated connector pairs consisting of one ADF++ Backplane connector and one ADF++ Front Board connector from the Backplane top surface plane to Front Board top surface plane or vice versa.

REQ B.18 All directly neighboring signal pairs to a pair under test – either in the same layer or in neighboring layers (up to eight pairs) – shall be terminated with 50 Ohms against GND on both ends.

REQ B.19 Measured return loss values shall be below the limit curve shown in Figure B-6, “Measured return loss limits” below for all frequencies for the relevant transmission path.

190 PICMG 3.1 R3.0, May 5, 2016


Figure B-6 Measured return loss limits


PICMG 3.1 R3.0, May 5, 2016 191


192 PICMG 3.1 R3.0, May 5, 2016

Revision History

Revision History C

Date Revision Changes

January 22, 2003 1.0 Initial Release

August 3, 2012 2.0 40GBASE-KR4 support

May 5, 2016 3.0 100GBASE-KR4 and 25GBASE-KR support

PICMG 3.1 R3.0, May 5, 2016 193

Revision History

194 PICMG 3.1 R3.0, May 5, 2016

Documents

PICMG 3.1 R3.0® 3.1 Revision 3.0 Specification Ethernet/Fibre Channel for AdvancedTCA® Systems Revision 3.0 - May 5, 2016Com Express · CompactPCI · Open Standards · Adlink Technology