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Pertemuan 11 General VLSI System Components. Matakuliah: H0362/Very Large Scale Integrated Circuits Tahun: 2005 Versi: versi/01. Learning Outcomes. - PowerPoint PPT Presentation
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1
Pertemuan 11 General VLSI System Components
Matakuliah : H0362/Very Large Scale Integrated CircuitsTahun : 2005Versi : versi/01
2
Learning Outcomes
Pada Akhir pertemuan ini, diharapkan mahasiswa akan dapat menerapkan gerbang logik, switching logik, dan atau struktur deskripsi Verilog untuk membangun rangkaian sederhana dengan level hirarki lebih tinggi dalam CMOS VLSI.
3
Multiplexor
module simple_mux (mux_out, p0, p1, select) ; input p0, p1 ; input select ; output mux_out ; always @ (select) ; case (select) 1’b0: mux_out = p0 ; 1’b1: mux_out = p1 ; endcaseendmodule
Verilog HDL:
n = 2m n: number of inputf : outputm: number select
f = p0 . s + p1 . s
Multiplexor 2:1
p0
p1
f
s
p0
p1
s
f
Gate level multiplexor:
4
Multiplexor
Gate level multiplexor:
p0
p1
f
s
sp1
p0f
s
Multiplexor 2:1Implementasi rangkaian multiplexor 2:1 dapat juga dilakukan dengan rangkain logic switchsehingga Verilog HDL nya juga akan berubah.
Cara lain
5
Multiplexor
Multiplexor 4:1module bigger_mux (out_4, p0, p1, p2, p3, s0, s1) ; input p0, p1, p2, p3 ; input s0, s1 ; output out_4 ; assign out_4 = s1 ? (s0, p3 : p2) : (s0 ? p1 : p0) ;endmodule
Verilog HDL:
f
p0
p1
s0
p2
p3
s0
s10
1 0
0
1
1
Gate level multiplexor:
6
Multiplexor
s0
f0123
p0p1p2p3
s1Gate level multiplexor:
module gate_mux_4 (out_gate, p0, p1, p2, p3, s0, s1) ; input p0, p1, p2, p3 ; input s0, s1 ; wire w1, w2, w3, w4 ; output out_gate_4 ; nand (w1, p_0, ~s1, ~s0), (w2, p_1, ~s1, s0), (w3, p_2, s1, ~s0), (w4, p_3, s1, s0), (out_gate, w1, w2, w3, w4) ;endmodule
Verilog HDL:
p0
p1
s1
f
s0
p2
p3
Multiplexor 4:1Cara lain
f = p0 . s1 . s2 + p1 . s1 . s0 + p2 . s1 . s0 + p3 . s1 . s0
7
Multiplexor
Multiplexor 4:1Cara lain
p1
p0
f
p2
p3
s0 s1 s2 s3
module tg_mux_4 (f, p0, p1, p2, p3, s0, s1) ; input p0, p1, p2, p3 ; input s0, s1 ; wire w0, w1, w2, w3, w_0, w_x ; output f ; nmos (po, w0, ~s1), (w0, w_0, ~s0) ; nmos (p1, w1, ~s1), (w1, w_0, s0) ; nmos (p2, w2, s1), (w2, w_0, s0), nmos (p3, w3, s1), (w3, wp_0, s0) ; not (w_x, w_0), (f, w_x) ;endmodule
Verilog HDL:
Gate level multiplexor:
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Binary Decodersmodule decode_4 (d0, d1, d2, d3, s0, s1) ; input s0, s1 ; ouput d0, d1, d2, d3 ; nor (d3, ~s0, ~s1), (d2, s0, s1), (d1, s0, ~s1), (d0, s0, s1) ;endmodule
Verilog HDL:
2/4 decoder
s1 s0 d0 d1 d3 d4
0 0 1 0 0 00 1 0 1 0 01 0 0 1 0 01 1 0 0 0 1
d0 d1 d2 d3
s0
s1
0 1 2 32/4
do = s1 . s0 = s1 + s0
d1 = s1 . s0 = s1 + s0
d2 = s1 . s0 = s1 + s0d3 = s1 . s0 = s1 + s0
s1 s0
d0d1d2d3
Gate level multiplexor:
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Latchmodule d_latch (q, q_bar, d) ; input d ; ouput q, q_bar ; reg q, q_bar ; always @ (d) ; begin (t_d) q = d ; (t_d) q_bar = ~d ; endendmodule
Verilog HDL:
module d_latch_gates (q, q_bar, d) ; input d ; ouput q, q_bar ; wire not_d ; not (not_d, d) ; nor (t_nor) g1 (q_bar, q, d), (t_nor) g2 (q_bar, not_d) ;endmodule
QDQ
simbol
D
Q
Q
Diagram logik
Gate level latch:VDD
D
Rangkaian CMOS
10
Latch
QD
Q
simbol
En
D
Q
Q
Diagram logik
En
module d_latch (q, q_bar, d, enable) ; input d, enable ; ouput q, q_bar ; reg q, q_bar ; always @ (d and enable) ; begin (t_d) q = d ; (t_d) q_bar = ~d ; endendmodule
Verilog HDL:
Gate level latch:
11
D Flip Flop
Q
QM2
M3M1
M4
Master Slave
D
0 T
tLoadMaster
Transferto slave
1
0
Positiveedge
Master Slave D Flip-FlopPositive-edge
module positive_dff (q, q_bar, d, clk) ; input d, clk ; ouput q, q_bar ; reg q, q_bar ; always @ (posedge clk) ; begin q = d ; q_bar = ~d ; endendmodule
Verilog HDL:
Gate level:
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RESUME
• Multiplexor.• Binary Decoders.• Latch.• D Flip Flop
