High-Speed VLSI Interconnections · 5.5 Failure Analysis of VLSI Interconnection Components 344 5.5.1 Reduction of Components into Straight Segments 344 5.5.2 Calculation of MTF and

High-Speed VLSIInterconnectionsSecond Edition

Ashok K. GoelDepartment of Electrical EngineeringMichigan Technological University

WILEY-INTERSCIENCE

A JOHN WILEY & SONS, INC., PUBLICATION

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High-Speed VLSIInterconnections

High-Speed VLSIInterconnectionsSecond Edition

Ashok K. GoelDepartment of Electrical EngineeringMichigan Technological University

WILEY-INTERSCIENCE

A JOHN WILEY & SONS, INC., PUBLICATION

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Library of Congress Cataloging-in-Publication Data:

Goel, Ashok K., 1953-

High-speed VLSI interconnections / by Ashok K. Goel. – 2nd ed.

p. cm.

Includes bibliographical references.

ISBN 978-0-471-78046-5 (cloth)

1. Very high speed integrated circuits–Mathematical models. 2. Very high

speed integrated circuits–Defects–Mathematical models. 3. Integrated

circuits–Very large scale integration–Computer simulation. 4. Semiconductors–

Junctions. I. Title.

TK7874.7.G63 2007

621.3905–dc222007001710

Printed in the United States of America

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In loving memory of my father

Shri D. N. Goel

Contents

PREFACE xv

1 Preliminary Concepts and More 1

1.1 Interconnections for VLSI Applications 2

1.1.1 Metallic Interconnections: Multilevel, Multilayer,

and Multipath Configurations 2

1.1.2 Optical Interconnections 5

1.1.3 Superconducting Interconnections 5

1.2 Copper Interconnections 5

1.2.1 Advantages of Copper Interconnects 6

1.2.2 Challenges Posed by Copper Interconnects 6

1.2.3 Fabrication Processes for Copper Interconnects 7

1.2.4 Damascene Processing of Copper Interconnects 9

1.3 Method of Images 10

1.4 Method of Moments 15

1.5 Even- and Odd-Mode Capacitances 17

1.5.1 Two Coupled Conductors 17

1.5.2 Three Coupled Conductors 19

1.6 Transmission Line Equations 21

1.7 Miller’s Theorem 23

1.8 Inverse Laplace Transformation 25

1.9 Resistive Interconnection as Ladder Network 27

1.9.1 Open-Circuit Interconnection 27

vii

1.9.2 Short-Circuited Interconnection 29

1.9.3 Application of Ladder Approximation to

Multipath Interconnection 31

1.10 Propagation Modes in Microstrip Interconnection 31

1.11 Slow-Wave Mode Propagation 32

1.11.1 Quasi-TEM Analysis 33

1.11.2 Comparison with Experimental Results 37

1.12 Propagation Delays 41

Exercises 41

References 42

2 Parasitic Resistances, Capacitances, and Inductances 46

2.1 Parasitic Resistances: General Considerations 47

2.2 Parasitic Capacitances: General Considerations 50

2.2.1 Parallel-Plate Capacitance 51

2.2.2 Fringing Capacitances 51

2.2.3 Coupling Capacitances 52

2.3 Parasitic Inductances: General Considerations 52

2.3.1 Self and Mutual Inductances 53

2.3.2 Partial Inductances 55

2.3.3 Methods for Inductance Extraction 55

2.3.4 Effect of Inductances on Interconnection Delays 57

2.4 Approximate Formulas for Capacitances 57

2.4.1 Single Line on a Ground Plane 58

2.4.2 Two Lines on a Ground Plane 58

2.4.3 Three Lines on a Ground Plane 59

2.4.4 Single Plate with Finite Dimensions

on a Ground Plane 59

2.5 Green’s Function Method: Using Method of Images 60

2.5.1 Green’s Function Matrix for Interconnections

Printed on Substrate 60

2.5.2 Green’s Function Matrix for Interconnections

Embedded in Substrate 67

2.5.3 Application of Method of Moments 72

2.5.4 Even- and Odd-Mode Capacitances 73

2.5.5 Ground and Coupling Capacitances 76

viii CONTENTS

2.5.6 The Program IPCSGV 76

2.5.7 Parametric Dependence of Interconnection Capacitances 77

2.6 Green’s Function Method: Fourier Integral Approach 84

2.6.1 Green’s Function for Multilevel Interconnections 84

2.6.2 Multiconductor Interconnection Capacitances 87

2.6.3 Piecewise Linear Charge Distribution Function 89

2.6.4 Calculation of Interconnection Capacitances 90

2.7 Network Analog Method 91

2.7.1 Representation of Subregions by Network Analogs 92

2.7.2 Diagonalized System for Single-Level

Interconnections 93

2.7.3 Diagonalized System for Multilevel Interconnections 97

2.7.4 Interconnection Capacitances and Inductances 97

2.7.5 The Program ICIMPGV 99

2.7.6 Parametric Dependence of Interconnection Capacitances 99

2.7.7 Parametric Dependence of Interconnection Inductances 104

2.8 Simplified Formulas for Interconnection Capacitances

and Inductances on Silicon and GaAs Substrates 109

2.8.1 Line Capacitances and Inductances 112

2.8.2 Coupling Capacitances and Inductances 113

2.9 Inductance Extraction Using FastHenry 114

2.9.1 The Program FastHenry 115

2.9.2 Extraction Results Using FastHenry 116

2.10 Copper Interconnections: Resistance Modeling 119

2.10.1 Effect of Surface/Interface Scattering

on Interconnection Resistivity 120

2.10.2 Effect of Diffusion Barrier on Interconnection

Resistivity 121

2.11 Electrode Capacitances in GaAs MESFET:

Application of Program IPCSGV 122

2.11.1 Ground and Coupling Capacitances 122

2.11.2 The Program EPCSGM 123

2.11.3 Dependence on MESFET Dimensions 127

2.11.4 Comparison with Internal MESFET

Capacitances 132

Exercises 132

References 133

CONTENTS ix

3 Interconnection Delays 136

3.1 Metal–Insulator–Semiconductor Microstripline

Model of an Interconnection 138

3.1.1 The Model 138

3.1.2 Simulation Results 140

3.2 Transmission Line Analysis of Single-Level

Interconnections 145

3.2.1 The Model 145

3.2.2 The Program PDSIGV 150

3.2.3 Dependence on Interconnection Parameters 150

3.3 Transmission Line Analysis of Parallel Multilevel


3.3.1 The Model 154

3.3.2 Numerical Simulation Results 158

3.4 Analysis of Crossing Interconnections 168

3.4.1 Simplified Analysis of Crossing Interconnections 169

3.4.2 Comprehensive Analysis of Crossing


3.4.3 The Program SPBIGV 178

3.4.4 Simulation Results Using SPBIGV 178

3.5 Parallel Interconnections Modeled as Multiple

Coupled Microstrips 190

3.5.1 The Model 190


3.6 Modeling of Lossy Parallel and Crossing

Interconnections as Coupled Lumped Distributed Systems 195

3.6.1 The Model 195


3.7 Very High Frequency Losses in Microstrip Interconnection 203

3.7.1 The Model 203


3.7.3 Interconnection Delays with High-Frequency Effects 213

3.8 Compact Expressions for Interconnection Delays 216

3.8.1 The RC Interconnection Model 217

3.8.2 The RLC Interconnection Model: Single Semi-Infinite Line 219

3.8.3 The RLC Interconnection Model: Single Finite Line 221

x CONTENTS

3.8.4 Single RLC Interconnection: Delay Time 223

3.8.5 Two and Three Coupled RLC Interconnections:

Delay Times 224

3.9 Interconnection Delays in Multilayer Integrated Circuits 226

3.9.1 The Simplified Model 226

3.9.2 Simulation Results and Discussion 228

3.10 Active Interconnections 230

3.10.1 Interconnection Delay Model 230

3.10.2 Active Interconnection Driven by Minimum-Size

Inverters 231

3.10.3 Active Interconnection Driven by Optimum-Size

Inverters 232

3.10.4 Active Interconnection Driven by Cascaded Inverters 234

3.10.5 Dependence of Propagation Time

on Interconnection Driving Mechanism 235

Exercises 236

References 237

4 Crosstalk Analysis 242

4.1 Lumped-Capacitance Approximation 243

4.2 Coupled Multiconductor MIS Microstripline Model

of Single-Level Interconnections 245

4.2.1 The Model 245

4.2.2 Numerical Simulations 248

4.2.3 Crosstalk Reduction 251

4.3 Frequency-Domain Modal Analysis of Single-Level


4.3.1 General Technique 254

4.3.2 Two-Line System 255

4.3.3 Three-Line System 257

4.3.4 Four-Line System 258


4.4 Transmission Line Analysis of Parallel Multilevel


4.4.1 The Model 264

4.4.2 The Program DCMPVI 268

4.4.3 Numerical Simulations Using DCMPVI 268

CONTENTS xi

4.5 Analysis of Crossing Interconnections 280

4.5.1 Mathematical Analysis 280


4.6 Compact Expressions for Crosstalk Analysis 293

4.6.1 Distributed RC Model for Two

Coupled Interconnections 294

4.6.2 Distributed RLC Model for Two Coupled


4.6.3 Distributed RLC Model for Three Coupled


4.7 Multiconductor Buses in GaAs High-Speed

Logic Circuits 302

4.7.1 The Model 303

4.7.2 Lossless MBUS with Cyclic Boundary Conditions 305


Exercises 309

References 310

5 Electromigration-Induced Failure Analysis 313

5.1 Electromigration in VLSI Interconnection

Metallizations: Overview 314

5.1.1 Problems Caused by Electromigration 314

5.1.2 Electromigration Mechanism and Factors 315

5.1.3 Electromigration Under Pulsed DC and AC Conditions 323

5.1.4 Testing and Monitoring of Electromigration 323

5.1.5 General Guidelines for Testing Electromigration 325

5.1.6 Reduction of Electromigration 327

5.2 Models of IC Reliability 328

5.2.1 Arrhenius Model 329

5.2.2 Mil-Hdbk-217D Model 329

5.2.3 Series Model 330

5.2.4 Series–Parallel Model 330

5.3 Modeling of Electromigration Due to Repetitive

Pulsed Currents 331

5.3.1 Modeling of Physical Processes 332

5.3.2 First-Order Model Development 333

5.3.3 Modeling Results for Direct Currents 337

5.3.4 Modeling Results for Pulsed Currents 340

xii CONTENTS

5.4 Electromigration in Copper Interconnections 341

5.4.1 Electromigration under DC Conditions 341

5.4.2 Electromigration under Pulsed DC Condition 342

5.4.3 Electromigration under Bipolar AC Conditions 342

5.5 Failure Analysis of VLSI Interconnection Components 344

5.5.1 Reduction of Components into Straight Segments 344

5.5.2 Calculation of MTF and Lognormal Standard Deviation 348

5.5.3 The Program EMVIC 349

5.5.4 Simulation Results Using EMVIC 350

5.6 Computer-Aided Failure Analysis 356

5.6.1 RELIANT for Reliability of VLSI Interconnections 357

5.6.2 SPIDER for Checking Current Density and Voltage

Drops in Interconnection Metallizations 358

Exercises 360

References 362

6 Future Interconnections 371

6.1 Optical Interconnections 371

6.1.1 Advantages of Optical Interconnections 372

6.1.2 Systems Issues and Challenges 373

6.1.3 Material Processing Issues and Challenges 374

6.1.4 Design Issues and Challenges 374

6.2 Transmission Line Models of Lossy Optical

Waveguide Interconnections 375

6.2.1 Lossy Waveguide with Single Propagating Wave 375

6.2.2 Equivalent Circuits for Waveguide Drivers and Loads 378

6.2.3 Lossy Waveguide in Inhomogenous Medium 379

6.3 Superconducting Interconnections 386

6.3.1 Advantages of Superconducting Interconnections 386

6.3.2 Propagation Characteristics of Superconducting


6.3.3 Comparison with Normal Metal Interconnections 388

6.4 Nanotechnology Circuit Interconnections: Potential Technologies 390

6.4.1 Silicon Nanowires and Metallic Interconnections 391

6.4.2 Nanotube Interconnections 392

6.4.3 Quantum-Cell-Based Wireless Interconnections 399

Exercises 400

References 400

CONTENTS xiii

APPENDICES (ftp://ftp.wiley.com/public/sci_tech_med/high_speed_VLSI)

Appendix 2.1 The Program IPCSGV for Calculating the Parasitic

Capacitances for Single-Level Interconnections on

GaAs-Based Using the Green’s Function Method

Appendix 2.2 The Program ICIMPGV for Calculating the ParasiticCapacitances and Inductances for MultilevelInterconnections on GaAs-Based (ftp://ftp.wiley.com/public/sci_tech_med/high_speed_VLSI) Using the NetworkAnalog Method

Appendix 2.3 The Program EPCSGM for Calculating the ElectrodeParasitic Capacitances in a Single-Gate GaAs MESFET

Appendix 3.1 The Program PDSIGV for Calculating the PropagationDelays in the Single-Level Interconnections on GaAs-Based(ftp://ftp.wiley.com/public/sci_tech_med/high_speed_VLSI)

Appendix 3.2 The Program IPDMSR for Calculating the PropagationDelays in an Interconnection Driven by Minimum-SizeRepeaters

Appendix 3.3 The Program IPDOSR for Calculating the PropagationDelays in an Interconnection Driven by Optimum-SizeRepeaters

Appendix 3.4 The Program IPDCR for Calculating the PropagationDelays in an Interconnection Driven by Cascaded Repeaters

Appendix 4.1 The Program DCMPVI for Delay and Crosstalk Analysisof Multilevel Parallel (ftp://ftp.wiley.com/public/sci_tech_med/high_speed_VLSI) Interconnections

Appendix 4.2 The Program SPBIGV for Signal Propagation Analysisof Bilevel Crossing Interconnections on GaAs-Based(ftp://ftp.wiley.com/public/sci_tech_med/high_speed_VLSI)

Appendix 5.1 The Program EMVIC for Electromigration-InducedFailure Analysis of (ftp://ftp.wiley.com/public/sci_tech_med/high_speed_VLSI) Interconnection Components

INDEX 405

xiv CONTENTS

Preface

Continuous advances in very large scale integrated (VLSI) circuit technology have

resulted in complex chips that have millions of interconnections that integrate the

components on the integrated circuit (IC) chip. Customer demand for higher speeds

and smaller chips has led to the use of interconnections in multilevel and multilayer

configurations. At present, the interconnections play the most significant role in

determining the size, power consumption, and clock frequency of a digital system.

Parasitic capacitances, resistances, and inductances and their effects on the crosstalk

and propagation delays associated with interconnections in high-density environ-

ments have become the major factors in the evolution of very high speed IC

technology.

It has been over 10 years since the first edition of this book was published. During

this period, several developments have taken place in the field of VLSI

interconnections such as the introduction of copper interconnections for VLSI

applications, realization of the importance of including inductances in the delay and

crosstalk models for very high speed circuits, further research on optical

interconnections, and the possibility of realizing nanotechnology ICs using

nanowires, nanotubes, and wireless interconnections. An attempt has been made

to include these developments in the present second edition.

This book focuses on the various issues associated with VLSI interconnections

used for high-speed applications. These include parasitic capacitances and

inductances, propagation delays, crosstalk, and electromigration-induced failure.

It has been written as a textbook for a graduate-level course and as a reference book

for practicing professionals who want to gain a better understanding of the several

factors associated with high-speed interconnections. The reader is expected to have a

basic understanding of electromagnetic wave propagation.

The chapters in this book are designed such that they can be read independently

of one another while, at the same time, being parts of one coherent unit. To maintain

independence among the chapters, some material has been intentionally repeated.

Several appropriate exercises are provided at the end of each chapter which are

designed to be challenging as well as help the student gain further insight into the

xv

contents of the chapter. The six chapters in this book can be described briefly as

follows.

In Chapter 1, a few basic techniques and some advanced concepts regarding wave

propagation in an interconnection are presented. Various types of interconnections

employed in VLSI applications, including multilevel, multilayer, and multipath

interconnections, are discussed. Advantages of copper interconnections and their

fabrication techniques are reviewed. The method of images used to find the Green’s

function matrix is presented, and the method of moments, which can be used to

determine the interconnection capacitances, is discussed. The even- and odd-mode

capacitances for two and three coupled conductors are discussed, and the

transmission line equations are derived. Miller’s theorem, which can be used to

uncouple the coupled interconnections, is presented. An efficient numerical inverse

Laplace transformation technique is described. A resistive interconnection has been

modeled as a ladder network. The various modes that can exist in a microstrip

interconnection are described, and a quasi–transverse electromagnetic (TEM)

analysis of slow-wave mode propagation in the interconnections is presented. The

various measures of propagation delays, including delay time and rise time, are

defined.

In Chapter 2, numerical techniques that can be used to determine the

interconnection resistances, capacitances, and inductances on a high-density

VLSI chip are discussed as well as the dependence of these parasitic elements on

the various interconnection design parameters. Approximate formulas for

calculating the parasitic capacitances for a few interconnection structures are

presented. An algorithm to obtain the interconnection capacitances by the Green’s

function method, where the Green’s function is calculated using the method of

images, is presented. The Green’s function is also calculated by using the Fourier

integral approach, and a numerical technique to determine the capacitances for

a multilevel interconnection structure in the Si–SiO2 composite is presented.

An improved network analog method to determine the parasitic capacitances

and inductances associated with the high-density multilevel interconnections

on the GaAs-based ICs is presented. Simplified formulas for the interconnection

capacitances and inductances on the oxide-passivated silicon and semi-insulating

gallium arsenide substrates are provided. A program called FastHenry, which

can be used to determine the inductances associated with an interconnection

structure, is described. A model for understanding the resistances for copper

interconnections is presented. Source codes of a few computer programs to

compute the parasitic capacitances and inductances are given in the appendices on

the accompanying Ftp site. One of these programs has been extended to determine

the electrode parasitic capacitances in a GaAs metal–semiconductor field effect

transistor (MESFET).

In Chapter 3, numerical algorithms that can be used to calculate the propagation

delays in the single and multilevel parallel and crossing interconnections are

presented, and the dependence of the interconnection delays on the various

interconnection design parameters is discussed. An analysis of interconnection

xvi PREFACE

delays on very high speed VLSI chips using a metal–insulator–semiconductor

microstripline model is presented. A computer-efficient model based on the

transmission line analysis of the high-density single-level interconnections on

GaAs-based ICs is presented. The signal propagation in the single-, bi-, and trilevel

high-density interconnections on GaAs-based ICs is studied, and a computer-

efficient model of the propagation delays in the bilevel parallel and crossing

interconnections on GaAs-based ICs is presented. A SPICE model for the lossless

parallel interconnections modeled as multiple coupled microstrips is presented,

and this model is extended to include lossy parallel and crossing interconnections.

The high-frequency effects such as conductor loss, dielectric loss, skin effect, and

frequency-dependent effective dielectric constant are studied for a microstrip

interconnection. Compact expressions of propagation delays for the single and

coupled interconnections modeled as RC and RLC circuits are provided. The active

interconnections driven by several mechanisms are analyzed and a simplified

model of the interconnection delays in multilayer ICs is presented. The source

codes of a few computer programs used to determine the propagation delays in the

normal and active interconnections are included in the appendices.

In Chapter 4, the mathematical algorithms which can be used to study the crosstalk

effects in the single and multilevel parallel and crossing interconnections are

discussed and the dependence of the crosstalk effects on the various interconnection

design parameters is studied. Crosstalk among neighboring interconnections is

calculated by using a lumped-capacitance approximation. Crosstalk in very high

speed VLSI circuits is analyzed by using a coupled multiconductor metal–insulator–

semiconductor microstripline model for the interconnections. Single-level inter-

connections are investigated by the frequency-domain modal analysis, and a

transmission line model of the crosstalk effects in the single-, bi-, and trilevel high-

density interconnections on the GaAs-based ICs is presented. This is followed by an

analysis of the crossing bilevel interconnections on the GaAs-based ICs. Compact

expressions for studying the crosstalk effects in the interconnections modeled as RC

and RLC circuits are provided. The crosstalk effects in the multiconductor buses in

the high-speed GaAs logic circuits are analyzed. The source codes of a few computer

programs used to analyze the crosstalk effects are included in the appendices.

In Chapter 5, the degradation of the reliability of an interconnection due to

electromigration is discussed. First, several factors related to electromigration in the

VLSI interconnections are reviewed. The basic problems that cause electromigration

are outlined, the mechanisms and dependence of electromigration on several factors

are discussed, testing and monitoring techniques and guidelines are presented, and

the methods of reducing electromigration in the VLSI interconnections are briefly

discussed. Electromigration in copper interconnections is studied. The various

models of IC reliability including the series model of failure mechanism in the VLSI

interconnections are presented. A model of electromigration due to repetitive

pulsed currents is developed. The series model has been used to analyze the

electromigration-induced failure in the several VLSI interconnection components.

The several computer programs available for studying electromigration in VLSI

PREFACE xvii

interconnections are discussed briefly. The source code of a computer program used

to study electromigration-induced failure effects in the various interconnection

components is included as an appendix.

In Chapter 6, a few interconnection technologies that seem promising for future

ICs are discussed. The advantages, issues, and challenges associated with the optical

interconnections are discussed and a lossy waveguide interconnection is modeled as

a transmission line. The propagation characteristics and the comparison of

superconducting interconnections with the normal metal interconnections are

presented. Various technologies that seem promising for nanotechnology circuits,

including nanowires, nanotubes, and quantum-cell-based wireless interconnections,

are briefly discussed.

The appendices for this book containing source codes can be found at:

ftp://ftp.wiley.com/public/sci_tech_med/high_speed_VLSI.

It should be noted that the various computer models presented in this book

may not have been validated by experimental measurements and therefore

should be used in computer-aided design programs with caution. In addition, the

computer programs provided in the appendices are written for different

computer systems and may need modifications to become suitable for the user’s

system. Finally, in the Internet-based information age, it is necessary to give

references to certain websites. Though these websites were active at the time of

preparation of this manuscript, it is possible that they may become inactive in

the future.

ACKNOWLEDGMENTS

I would like to thank several individuals for their help and encouragement

during the preparation of this book. I am grateful to Professor Kai Chang of

Texas A&M University and editor of Microwave and Optical Technology Letters

for inviting me to write this book. I am also thankful to Professor Martha Sloan

of Michigan Technological University for her support. I also would like to thank

my graduate students Yiren R. Huang, P. Joy Prabhakaran, Manish K. Mathur,

Wei Xu, Matthew M. Leipnitz, and Jaikumar K. Parambil for their assistance

with developing the computer programs and for obtaining the simulation

results presented at several instances in this book. I am thankful to the Institute

of Electrical and Electronics Engineers (United States) and the Institution of

Electrical Engineers (United Kingdom) for their permission to use copyrighted

material from over 30 papers published in IEEE Transactions, IEE Proceedings,

and their other publications and I would like to take this opportunity to thank the

authors of these papers whose work has been showcased in this book. I also owe

special thanks to my wife, Sangita, for her constant love and encouragement.

Finally, I express my deep appreciation to my son, Sumeet, and daughter,

Rachna, for their patience and understanding during the preparation of this

book.

xviii PREFACE

DISCLAIMER

The information presented in this book is believed to be accurate and great care has

been taken to ensure its accuracy. However, no responsibility is assumed by the

author for its use and for any infringement of patents or other rights of third parties

that may result from its use. Further, no license is granted by implication or

otherwise under any patent, patent rights, or other rights.

A. K. G.

Houghton, Michigan

PREFACE xix

CHAPTER ONE

Preliminary Concepts and More

In this chapter, some of the basic concepts and techniques used in this book are

presented. The chapter is organized as follows:

� Various types of interconnections employed in very large scale integration(VLSI) applications are discussed in Section 1.1.

� Advantages and challenges posed by the copper interconnections and thetechniques used for their fabrication are presented in Section 1.2.

� Method of images used to find the Green’s function matrix in Chapter 2 ispresented in Section 1.3.

� Method of moments used to determine the various interconnection capaci-tances in Chapter 2 is discussed in Section 1.4.

� Even- and odd-mode capacitances for two and three coupled conductors arediscussed in Section 1.5.

� Transmission line equations are derived and coupled transmission lines arediscussed in Section 1.6.

� Miller’s theorem used to uncouple the coupled interconnections in Chapter 3is presented in Section 1.7.

� A computer-efficient numerical inverse Laplace transformation techniqueused at several instances in this book is described in Section 1.8.

� A resistive interconnection has been modeled as a ladder network inSection 1.9.

� Various propagation modes that can exist in a microstrip interconnection aredescribed in Section 1.10.

� A quasi–transverse electromagnetic (TEM) analysis of slow-wave modepropagation in interconnections is presented in Section 1.11.

High-Speed VLSI Interconnections, Second Edition By Ashok K. Goel

Copyright # 2007 John Wiley & Sons, Inc.

1

� Definitions of propagation delays used in the literature, including delay timeand rise time, are presented in Section 1.12.

1.1 INTERCONNECTIONS FOR VLSI APPLICATIONS

Continuous advances in integrated circuit (IC) technology have resulted

in smaller device dimensions, larger chip sizes, and increased complexity.

There is an increasing demand for circuits with higher speeds and higher

component densities. In recent years, growth of GaAs on silicon (Si) substrate

has met with a great deal of interest because of its potential application in

new hybrid technologies [1–11]. GaAs-on-Si unites the high-speed and

optoelectronic capability of GaAs circuits with the low material cost and superior

mechanical properties of the Si substrate. The heat sinking of such devices is

better since the thermal conductivity of Si is three times more than that of GaAs.

This technology is expanding rapidly from research to device and circuit

development [12–15].

So far, the various IC technologies have employed metallic interconnections,

and there is a possibility of using optical interconnections in the near future.

Recently, the possibility of using superconducting interconnections is also

being explored. Optical and superconducting interconnections are discussed in

Chapter 6.

1.1.1 Metallic Interconnections: Multilevel, Multilayer,and Multipath Configurations

The VLSI chips require millions of closely spaced interconnection lines that

integrate the components on a chip. As VLSI technology advanced to meet the needs

of customers, it became necessary to use multilayer interconnections in two or more

levels to achieve higher packing densities, shorter transit delays, and smaller chips.

In this book, the term level will be used to describe conductors which are separated

by an insulator and the term layer to describe different conductors tiered together in

one level of interconnection, as shown in Fig. 1.1.1. In most cases, because of its low

resistivity and silicon compatibility as shown in Table 1.1.1 [16], aluminum has been

used to form metal interconnections. However, as device dimensions are decreased,

current density increases, resulting in decreased reliability due to electromigration

and hillock formation causing electrical shorts between successive levels of Al

[17–20]. Tungsten has also been used for interconnects [21–23] and, sometimes,

Al/Cu is used to solve problems characteristic of pure Al [1.24] though this choice

has not been without problems [25, 26]. There have been several studies [27–34]

aimed at reducing electromigration. All these studies have used layers of two or

more metals in the same level of the interconnection. Some of the multilayer

structures studied so far have been Al/Ti/Cu [28], Al/Ta/Al [30], Al/Ni [31], Al/Cr

[32], Al/Mg [33], and Al/Ti/Si [34]. Coevaporation of Al–Cu–Ti, Al–Cu–Ti,

Al–Cu–Co, and Al–Co has also been shown to decrease electromigration [27]. There

2 PRELIMINARY CONCEPTS AND MORE

have been many studies on the problem of hillock formation as well [16, 35–44].

One method of reducing these hillocks on silicon-based circuits has been to deposit a

film of WSi [36] or MoSi between Al and the silicon substrate. Complete elimination

of hillocks is reported in studies where the VLSI interconnections were fabricated by

layering alternately Al and a refractory metal (Ti or W) [16, 42–44].

Recently, in an attempt to solve the ‘‘interconnect problem,’’ that is, the problem

of unprecedented high density of interconnections operating at extremely high

speeds and carrying high current densities, a modified version of the traditional

metallic interconnection called the ‘‘multipath interconnect’’ has been proposed

[45]. The modified interconnection consists of using the concept of parallel

processing by providing two or more paths between the driving gate and the loading

FIGURE 1.1.1 Schematic of layered interconnection structures using (a) Ti layer used tomatch aluminum and silicon expansion coefficients; (b) Ti or W layer on top of aluminum to

constrain hillocks; (c, d) multiple layers of Ti or W alternated with aluminum.

INTERCONNECTIONS FOR VLSI APPLICATIONS 3

gate. A schematic of a three-section multipath interconnect (side view) connecting

the driver and the load is shown in Fig. 1.1.2. These paths are stacked vertically

isolated from one another by insulating layers between any two consecutive

paths thereby taking the same area on the chip as a single-path interconnect.

Depending on the number of paths, an array of such multipath interconnects could

carry much higher currents on the chip. Furthermore, this interconnect structure

could be built by an extension of the available microelectronics fabrication

techniques.

TABLE 1.1.1 Resistivity and Expansion Coefficients

Resistivity Thermal Expansion Melting

Material (m� �cm) Coefficient (�C�1) Point (�C)

Pure aluminum (bulk) 2.65 25.0 � 10�6 660Sputtered Al and Al/Si 2.9–3.4 25.0 � 10�6 660Sputtered Al/2% Cu/1% Si 3.9 25.0 � 10�6 660LPCVD aluminum 3.4 25.0 � 10�6 660Pure tungsten (bulk) 5.65 4.5 � 10�6 3410CVD tungsten 7–15 4.5 � 10�6 3410Evaporated/sputtered tungsten 14–20 4.5 � 10�6 3410Ti (bulk) 42.0 8.5 � 10�6 1660TiAl3 (bulk) 17–22 — 1340

CuAl2 (bulk–y phase) 5–6 — 591WAl12 — — 647

Si — 3.3 � 10�6 —SiO2 — 0.5 � 10�6 —

Source: From [16]. # 1985, by IEEE.

FIGURE 1.1.2 Schematic of three-path multipath interconnection (side view) connectingdriver and load on (a) semi-insulating substrate such as GaAs and (b) silicon substrate.


1.1.2 Optical Interconnections

As an alternative to electrical interconnections, optical interconnections have

emerged in recent years which offer fast, reliable, and noise-free data transmission

[46–50]. So far, they have been used for computer-to-computer communications and

processor-to-processor interconnections. At this time, however, their applicability at

lower levels of the packaging hierarchy, such as for module-to-module connections

at the board level, chip-to-chip connections at the module level, and gate-to-gate

connections at the chip level, is still under investigation. The principal advantages of

optical interconnections over electrical connections are higher bandwidth, lower

dispersion, and lower attenuation. Some of the problems with optical interconnec-

tions under investigation are size incompatibility with ICs, high power consumption,

and tight alignment requirements.

1.1.3 Superconducting Interconnections

In recent years, the advent of high-critical-temperature superconductors has opened

up the possibility of realizing high-density and very fast interconnections on silicon-

as well as GaAs-based high-performance ICs. The major advantages of super-

conducting interconnections over normal metal interconnections can be summarized

as follows: (a) Signal propagation time on a superconducting interconnection will be

much smaller as compared to that on a normal metal interconnection, (b) the packing

density of the IC can be increased without suffering from the high losses associated

with high-density normal metal interconnections, and (c) there is virtually no signal

dispersion on superconducting interconnections for frequencies up to several tens of

gigahertz.

1.2 COPPER INTERCONNECTIONS

To be able to produce high-speed ICs, it is always desirable to use interconnections

that would allow rapid transmission of information, that is, signals among the

various components on the chip. For the last 40 years, aluminum has been used

almost exclusively to make metallic interconnection lines on ICs. More recently,

aluminum–copper alloys have been used because they have been shown to provide

better reliability than pure aluminum. In December 1997, in order to lower the

resistance of metallic interconnections, IBM announced plans to replace aluminum

with copper, a metal with lower resistivity of less than 2 m� � cm compared to that ofabout 3 m� � cm for aluminum. It is worth mentioning that while copperinterconnections have been a hot topic in the semiconductor industry since the

IBM announcement, the race to improve the aluminum interconnect technology has

not slowed down. In fact, semiconductor companies are exploring new technologies

for aluminum-based interconnections. These include ionized plasma deposition, hot

aluminum physical vapor deposition (PVD), and aluminum damascene structures. It

is expected that while advanced microprocessors and fast memory circuits may

COPPER INTERCONNECTIONS 5

switch to copper interconnections, aluminum-based interconnections deposited by

using the latest techniques will continue to coexist at least in the near future.

While the semiconductor industry has known the potential advantages of using

copper interconnects since the 1960s, it took over 30 years for it to overcome the

associated challenges until it was announced in a paper on the complementary

metal–oxide–semiconductor (CMOS) 7S technology presented at the Institute of

Electrical and Electronics Engineers’ IEDM conference by IBM in December 1997.

Following is a summary of the advantages of copper interconnects and the

challenges in implementing this technology:

1.2.1 Advantages of Copper Interconnects

1. An obvious advantage of copper is its lower electrical resistivity compared

with aluminum. In fact, copper interconnects offer 40% less resistance to

electrical conduction than the corresponding aluminum interconnects, which

results in speed advantages of as much as 15% in microprocessor circuits

employing copper interconnects.

2. The phenomenon of electromigration that results in the movement of atoms

and molecules in the interconnects under high-stress conditions of high

temperatures and high current densities causing open- and short-circuit

failures of interconnects through the formation of voids and hillocks is

known to occur much less frequently in copper interconnects than in

aluminum interconnects. That is why aluminum–copper alloys have been

preferred over pure aluminum as the interconnect material.

3. Copper interconnects can be fabricated with widths in the range of 0.2 mmwhile it has been difficult to reduce dimensions below 0.35 mm withaluminum interconnects. This reduction in interconnection dimensions

allows much higher packing densities of the order of 200 million transistors

per chip.

4. It has been claimed that the deposition of copper interconnects can be

achieved with a potential cost saving of up to 30%, which translates into a

saving of about 10–15% for the full wafer [51].

1.2.2 Challenges Posed by Copper Interconnects

In the United States, a consortium of 10 leading chip-making semiconductor

companies known as SEMATECH (Semiconductor Manufacturing Technology) has

worked hard to overcome the challenges posed by the replacement of aluminum

interconnects by copper interconnects. Following is a list of technical challenges that

must be addressed and met within acceptable standards to fabricate copper-based IC

chips [52]:

1. Copper is considered poisonous for silicon-based circuits. It diffuses rapidly

into the active source, drain, and gate regions of transistors built on the silicon


substrate and alters their electrical properties affecting the functionality of the

transistors.

2. In order to meet the above challenge alone, an entirely new fabrication

process is required for implementation of copper interconnects.

3. Fabrication of copper interconnects requires the production and use of a large

amount of ultrapure water, which is rather expensive.

4. The release of waste discharges containing copper to the environment must be

handled very carefully.

1.2.3 Fabrication Processes for Copper Interconnects

As shown in Fig. 1.2.1, a conventional photolithographic process for depositing

aluminum interconnects on the silicon substrate involves the following steps:

1. Deposit a layer of silicon dioxide insulator on the silicon wafer.

2. Deposit a layer of metal on the silicon dioxide layer.

3. Cover the metal layer by depositing a layer of photoresist on it.

4. Project a shadow of the interconnect pattern (drawn on a reticle) on the

photoresist layer by using ultraviolet rays and an optical projection system.

5. Develop the photoresist that was exposed to the ultraviolet light.

FIGURE 1.2.1 Conventional photolithographic process steps for depositing aluminummetallization on silicon substrate.

COPPER INTERCONNECTIONS 7

6. Using proper chemicals, etch away parts of the metal layer that are not

covered by the hardened photoresist.

7. Finally, remove the hardened photoresist, leaving the interconnect metal in

the desired pattern on the silicon dioxide layer.

Since copper can contaminate the silicon substrate and the silicon dioxide

dielectric layer of an IC resulting in increased junction leakages and threshold

voltage instabilities, barrier layers are required to isolate the copper interconnects

from the substrate and the dielectric layer. The barrier layer, usually made from

tungsten or titanium nitride, should be as thin as possible to minimize the resistance

and to maximize the reliability of the copper interconnects. It is applied after the

interconnect channels have been etched out in the dielectric layer by photolitho-

graphy. The barrier layer is covered by a microscopic seed layer of copper to ease

further deposition of copper on the entire wafer by electroplating. Finally, the excess

copper is removed by a chemical–mechanical polishing process leaving the desired

pattern of copper interconnects on the wafer. The various steps are shown in

Fig. 1.2.2.

Various techniques have been studied for deposition of copper interconnects on

silicon-based circuits. These include chemical vapor deposition (CVD), electroless

plating, and electrolytic plating [51]. In each case, the objective was to deposit very

thin and even layers of copper interconnects in the horizontal direction and vias in

FIGURE 1.2.2 Various steps involved in depositing copper metallizations.


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