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PERFORMANCE OPTIMIZATION OF SINGLE-PHASE LEVEL-SENSITIVE CIRCUITS
BARIS TASKIN AND IVAN S. KOURTEV
UNIVERSITY OF PITTSBURGH DEPARTMENT OF ELECTRICAL ENGINEERING
Outline
• Introduction
• Timing Constraints
• LP Model Formulation
• Experimental Results
• Conclusions
Introduction
• Large-scale SOC
• Time borrowing (cycle stealing)
• Clock skew scheduling
• Clock/Timing schedule
• Minimum clock period
• Local data path
• Graph
Background
D Q D Q
CLOCKi CLOCKf
DataI n
DataOut
Registeri
COMBI NATIONALLOGIC
Registerf
CLK CLK
R1 R2
R4
R3R1 R2 R3
R4
Latch Operation
Positive level-sensitive
CLK
DATAIN
DATAOUT
Time Borrowing
CLK1
CLK2
CLK3
CLK1
CLK2
CLK3
Flip-Flop based Latch based
Higher Operating Frequency!
0.5 T Data Propagation
T 0.5 T Data Propagation
1.5 T
Clock Skew
Tskew(i,f) = ti - tf
Clock signal
delay at the
initial register
Clock signal
delay at the
final register
D Q D Q
CLOCKi CLOCKf
DataI n
DataOut
Registeri
COMBI NATIONALLOGIC
Registerf
CLK CLK
CLKsource
CLKi
CLKf
ti
tf
Tskew(i,f)
CLK1
CLK2
CLK3
CLK1
CLK2
CLK3
Clock Skew Scheduling
Zero clock skew
Non-zero clock skew
Higher Operating Frequency!
0.5 T Data
Propagation
T0.5 T + TSKEW
Data
Propagation
T +TSKEW
CLK1
CLK2
CLK3
CLK1
CLK2
CLK3
Optimization Problem
•Flip-flop-based
•Zero clock skew
•Latch-based
• Non-zero clock skew
Time borrowing+
Clock skew scheduling
0.5 T Data Propagation
T0.5 T + TSKEW
Data
Propagation
1.5 T +TSKEW
Arrival timeAi
di Di
ai
T
Departuretime
CLK at Ri
CWL
Timing Parameters
Outline
• Introduction
•Timing Constraints
• LP Model Formulation
• Experimental Results
• Conclusions
Constraints
1. Latching
2. Synchronization
3. Propagation
5. Skew
CLOCKSKEW
Constant
or
Variable? 4. Validity
CLK
DATA IN
DATA OUT
DCQ DDQ
SetupHold
On time CWL
CLOCK PERIOD T
t1 t2 t9t8t7t6t5t4t3
Latching Constraints
af Af
ff
ff
STA
aH
Synchronization Constraints
Departuretime
Arrival timeAi
di Di
ai
k-th CLOCK CYCLE
CLK at Ri
Synchronization Constraints
CLK at Ri Departure
time
Arrival timeAi
di Di
ai
k-th CLOCK CYCLE
( )( )
M
iCQ
LW
iDQii
m
iCQ
LW
iDQii
DCTDAD
DCTDad
M
m
+,+max=
+,+max=
-
-
Max!
Fan-in 1 Arrival time
Fan-in 2 Arrival time
Arrival time
Departure time
dfDf
af Af
k-th CLOCK CYCLE
CLK at Rf
Propagation ConstraintsMin
!Max
!
fiTDDA
fiTDda
skewifPMi
if
skewifPmiif
,max
,min
Outline
• Introduction
• Timing Constraints
•LP Model Formulation
• Experimental Results
• Conclusions
Problem Formulation
Timing
constraint
s
NLP
problem
Equivalent
LP model
Modified big M Method
Modified big M (MBM) Method
min Z min (Z+Ma)
a=max (b,c) a ba c
min Z min (Z-Ma)
a=min (b,c) a ba c
MBM Method Example
Obj: Min Z= 5a+4b
s.t.
c
C1 : c=max(a,b)
C2 : a=3
C3 : b=7
NON-LINEAR
a b c
M
c
C1a: ca
C1b: cb
+1000c
LINEAR
LP Model Formulation
( )m
iCQ
LW
iDQii DCTDad
m+,+max= -
iCQ
LWi
iDQii
m
m
DCTd
Dad
-
[Synchronization Constraint-I]
jjdMTmin
Implementation and Model Highlights
• C++ implementation
• Off-shelf optimizer (CPLEX)
• Provide stand-alone model
– Robust, fast
– Sensitivity analysis
Outline
• Introduction
• Timing Constraints
• LP Model Formulation
•Experimental Results
• Conclusions
Timing Analysis
CIRCUIT
TOPOLOGY
CLOCKING
METHODOLOGY
MAX OP. FREQUENCY
TIMING SCHEDULE
CLOCKING SCHEDULE
SENSITIVITY*
INPUT OUTPUT
Example
CLK at R1
CLK at R3
CLK at R2
(k-1)T+0
time (tglobal)
3.8
1.3 3.35 5.4 7.45 9.5 11.55
t1= 3.8
t2= 1.3
5.35 7.9 9.95 12 14.05
8.65 12.75
(k-1)T+4.1 (k-1)T+8.2 (k-1)T+16.4(k-1)T+12.3
k-th cycle (k+1)-th cycle (k+2)-th cycle
k-th cycle (k+1)-th cycle (k+2)-th cycle
k-th cycle (k+1)-th cycle (k+2)-th cycle
R1 R2
R3
a1=0.75 d1=2.05A1=2.05 D1=2.05
t1 = 3.8
a2=2.05 d2=2.05A2=2.05 D2=2.05
t2 = 1.3
a3=0 d3=2.05A3=0 D3=2.05
t3 = 0
[1.6]
[6.6]
13.6
R1
R3
R2
R4
R5
Circuit C
Clock Pin
...
Additional Constraints
tR1 = tR4 = c
c:constant
Clock signal delays
at R1 and R4
GLOBALCLOCKSIGNAL
ISCAS’89 Benchmark ResultsCIRCUIT INFORMATION
NON-ZERO SKEW SCHEDULING
CONSTRAINED CIRCUIT
CircuitNo of
registersNo of data
pathsTime I3 I4
s27 3 3 0.02s 38% 38%
s444 16 113 0.07s 41% 41%
s1196 18 20 0.03s 63% 23%
s38417 1636 28082 603s 39% 39%
s38584 1452 15545 321s 31% 31%
Average - - - 27% 24%
TIME BORROWING 15%
CLOCK SKEW SCHEDULING 14%
SIMULTANEOUS 27%
Outline
• Introduction
• Timing Constraints
• LP Model Formulation
• Experimental Results
•Conclusions
Conclusions
Increased performance
• Time borrowing
• Clock skew scheduling
Complete framework for timing
analysis
• Multi-phase synchronization
PERFORMANCE OPTIMIZATION OF
SINGLE-PHASE LEVEL-SENSITIVE CIRCUITS
BARIS TASKIN AND IVAN S. KOURTEV
QUESTIONS
UNIVERSITY OF PITTSBURGH DEPARTMENT OF ELECTRICAL ENGINEERING
