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POWER OPTIMIZATION STRATEGIESIN VLSI ARCHITECTURE DESIGN

ANINDYA SUNDAR DHAR

Dept. of E&ECE

IIT Kharagpur

Basic Design Flow

SYSTEM SPECIFICATION

ARCHITECTURAL DESIGN

LOGIC DESIGN

CIRCUIT DESIGN

DEVICE DESIGN

LAYOUT

..

(Algorithmic Level)

(Register Transfer Level)

(Gate Level)

(Transistor Level)

- - - - - - - - - - - - - - - - - -

Physical Design

Optimization is possible at every level

ALGORITHMIC LEVEL

ARCHITECTURAL LEVEL

LOGIC LEVEL

CIRCUIT LEVEL

DEVICE LEVEL

..

SPEEDSPEED

POWERPOWER

AREAAREA

Major Issues

Must satisfy the throughput

requirement

Power consumption should be

within prescribed limit

Should occupy minimum

possible silicon area

The actual cost function involving these factors depends on specific application.

To design Low Power Architectures efficiently,

knowledge in the digital logic is not sufficient.

To design Low Power Architectures efficiently,

the designer must have a good understanding

of analog circuits as well.

VDD VDD

A

A

YY

A

B

B

CL CL

CMOS INVERTER CMOS 2 INPUT NAND GATE

A Y

A Y

0

0

1

1How much power

does it consume ?

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SOURCES OF POWER DISSIPATION

1. DYNAMIC SWITCHING POWER

2. SHORT-CIRCUIT CURRENT POWER

3. LEAKAGE CURRENT POWER

VDD VDD

A

A

YY

A

B

B

CL CL

CMOS INVERTER CMOS 2 INPUT NAND GATE

VDD VDD

A

A

YY

A

B

B

CL CL

CMOS INVERTER CMOS 2 INPUT NAND GATE

VDD VDD

A

A

YY

A

B

B

CL CL

CMOS INVERTER CMOS 2 INPUT NAND GATE

PSwitching = fClkCLVDD2

PSwitching = fClkCLVDD2

Various Possibilities

Reduction of the clock frequency

Reduction of switching activities

Reduction of node capacitances

Reduction of the supply voltageTime

Normalizedresistance

Short circuit current

VDD

A Y

CL

Transition begins

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Supply voltage (VDD)

Propagationdelay(td

)

Propagation Delay vs. Supply Voltage

PSwitching = fClkCLVDD2

Processor

Processor

ProcessorINPUT OUTPUT

INPUT OUTPUT

PARALLEL PROCESSINGAT LOWER SUPPLY VOLTAGE

100 MSPS

10 nS

5 V

16 mW

50 MSPS

20 nS2.5 V

2 mW

50 MSPS

20 nS

2.5 V

2 mW

100 MSPS

10 nS

2.5 V

4 mW

PSwitching = fClkCLVDD2

Processor

Processor

ProcessorINPUT OUTPUT

INPUT OUTPUT

Achievement: LOW POWER CONSUMPTION

Disadvantage: OCCUPIES MORE AREA

PARALLEL PROCESSINGAT LOWER SUPPLY VOLTAGE An Example

DCBA

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

D

C

B

A

D

C

B

A

Y

Y

Proper ordering of the inputs can reduce

the switching power consumption

Memory

Sense Amplifier

Address Core Memory

(Bit cells)

VDD

Data

Can work

in thePOWERDOWN

mode !

Leakage current is significant

Memory

Sense Amplifier

Power Management Block

00 01

10 11

Address

2 MSbits

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BINARY

COUNTER

GRAY

COUNTER

R A M

.

.

.

f(0)

f(1)

f(2)

f(3)0010

0001

0011

0000

Reduction in the number of transitions in the Address Bus

Binary0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Gray0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Number of transitions

Binary GrayBits

4 30 16

8 510 256

16 131070 65536

Conclusion

Power consumption can be decreased by

reducing the unnecessary switching

Other methods include reduction of

the power supply voltage and

minimizing the node capacitances

Understanding analog electronics is essential

for designing low power circuits efficiently

Quantum devices will possibly take over

in near future