Passive reference-sharing SAR ADC

Enrique Alvarez-Fontecilla n, Angel AbuslemeDepartment of Electrical Engineering, Pontificia Universidad Católica de Chile, Av. Vicuña Mackenna 4860, Macul, Santiago, Chile

a r t i c l e i n f o

Article history:Received 9 May 2014Received in revised form22 January 2015Accepted 5 June 2015Available online 29 June 2015

Keywords:Analog-to-digital converter (ADC)Passive charge-sharing (PCS)Passive reference-sharing (PRS)Successive approximation register (SAR)

a b s t r a c t

Charge-redistribution successive approximation register (SAR) analog-to-digital converters (ADCs) arewidely used for their simple architecture, inherent low-power consumption and small footprint. Severaltechniques aiming to reduce the power consumption, to increase the speed, and to reduce thecapacitance spread have been developed, such as splitting the digital-to-analog converter (DAC)capacitor array, and charging and discharging the DAC capacitors in multiple steps. In this paper, a fullydifferential, low-power, passive reference voltage sharing SAR ADC architecture is presented, along withits theoretical analysis and test results. In this architecture, suitable for low sampling rate and low-resolution applications, the reference voltage is scaled down by successively connecting equally sizedcapacitors in parallel, allowing the use of small capacitor for its implementation. The implemented 6-bitADC is one of the smallest ADCs reported in a 180-nm technology, and features a FoM between 30.8 and39.3 fJ per conversion step without considering the clock generator power consumption.

& 2015 Elsevier Ltd. All rights reserved.

1. Introduction

SAR ADCs have gained significant popularity since the intro-duction of the charge redistribution analog-to-digital conversiontechniques [1]. This widespread use is mainly due to their inherentlow-power consumption, small footprint and simple architecture,which make them suitable for low-power, medium-resolutionapplications such as wireless sensor networks (WSNs) and medicalmonitoring [2,3].

Several techniques to reduce the power consumption, to reducethe capacitance spread,1 and to increase the sampling rate of SAR-based ADC architectures have been developed, such as splittingthe DAC capacitor array [4], charging and discharging the DACcapacitors in multiple steps [5], using a comparator-based asyn-chronous binary-search technique [6], programming the compara-tor threshold at runtime to approximate the input signal via binarysearch [7], using a charge-recycling scheme [8], and carrying outthe successive approximation algorithm by means of a passivecharge-sharing (PCS) process [9].

Commonly, an ADC performance is assessed through the Waldenfigure of merit (FoM) given by P= 2ENOB � f s

� �(measured in fJ per

conversion-step), where P is the power consumption, ENOB is theeffective number of bits and fs corresponds to the sampling frequency.

Nowadays, medium-resolution (8–10 bits) SAR ADCs have achievedsampling rates of tens of MS/s with power consumptions of only tensof fJ per conversion step [2,3,5,9–15].

When designing ADCs for low sampling rate and low-resolution applications, however, trying to achieve increasingsampling rates is not always mandatory or not even necessary(e.g., when the measured variables are varying slowly, which is thecase for atmospheric variables), but die area and power consump-tion must always be taken into account. Additionally, in most casesthe aforementioned FoM is reported without considering thepower consumption of the reference drivers, a variable that cannotbe left out in the context of low-power applications.

In all SAR ADCs reported in the literature a considerablefraction of the die area is occupied by the DAC capacitor array[14], and the large capacitance is a limiting factor when trying toreduce the power consumption [11] and increase the conversionrate. In this work we present a fully differential, passivereference-sharing (PRS) SAR ADC based on the PCS ADC of [9],which allows the use of small, equally sized capacitors, andminimizes the power taken from the reference voltages. Ananalysis is presented in order to explore the design space ofthe PRS architecture, and determine both its sensitivity tovariations of different parameters and the factors that limit itsresolution. Additionally, a 6-bit PRS ADC implemented in a 180-nm technology is presented, and the test results are shown.The implemented ADC measures 0:0168 mm2, and features apower consumption of 2:07 μW (without considering the powerconsumption of the clock generator) for f s ¼ 1:5625 MS=s andVDD ¼ 1:8 V.

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journal homepage: www.elsevier.com/locate/mejo

Microelectronics Journal

http://dx.doi.org/10.1016/j.mejo.2015.06.0050026-2692/& 2015 Elsevier Ltd. All rights reserved.

n Corresponding author.E-mail addresses: enrique@ing.puc.cl (E. Alvarez-Fontecilla),

angel@ing.puc.cl (A. Abusleme).1 The capacitance spread is defined as the ratio between the maximum

capacitance and the minimum capacitance.

Microelectronics Journal 46 (2015) 750–757

2. The passive reference-sharing algorithm

To perform the successive approximation algorithm in the PCSADC introduced in [9], an array of binary-weighted capacitors ischarged with a reference voltage while the analog signal issampled. Then, based upon the previous decision of the compara-tor, the next capacitor is connected to the comparator input insuch a way that the comparator differential input voltage con-verges to zero as the conversion progresses. The comparatordecisions that lead to this result represent the ADC digital output,from MSB to LSB. The PCS process itself can also be used to scalethe reference voltage at the terminals of each capacitor in a binaryprogression, so that the capacitors can be sized equally and thechip area can be reduced considerably.

The PRS algorithm consists of two concurrent processes: thereference-sharing (RS) process and the successive approximation(SA) process. While the analog signal is sampled, only twocapacitors are charged with the differential reference voltage.Then, as the SA process progresses, the capacitors that are stilldisconnected from the comparator input successively share theircharge with the remaining uncharged capacitors. At every step ofthe RS process the charge of one capacitor is shared with anothercapacitor with the same capacitance, hence its charge is split inequal parts and the voltage at its terminals is halved. Through thisprocess, the initial reference charge is propagated through the DACarray, so the reference voltages at the terminals of the capacitorsend up scaled in a binary progression.

Fig. 1 shows a simplified schematic of a B-bit PRS ADC, whereall capacitors are sized equally, voltages vp and vm are the inputsignals, and Vrp, Vrm and Vrcm are the reference voltages. Fig. 2illustrates the step-by-step operation of a 4-bit PRS ADC. Con-sidering vid ¼ vp�vm and Vref ¼ 2ðVrp�VrmÞ, the converter worksas follows: at the track-and-hold step (step 0), only the reset signalR is high, so CB�1 is charged to vid, CB�2 and CB�3 are charged toVref =2 and the remaining capacitors are short-circuited to Vrcm. Atthe first conversion step (step 1), R turns low and the MSB (D1) isdetermined. Signals SB�4, eB�3 and eB�4 turn high and CB�3 sharesits charge with CB�4, leaving a voltage of Vref =4 at both capacitors.At the i-th step (for iZ2), SB� i turns high and CB� i, holding areference voltage of Vref =2

i�1, is connected either directly orinversely between nodes vþ and v� (signal eB� i turns high ifDi�1 ¼ 0, or signal gB� i turns high if Di�1 ¼ 1). At the same step,SB�ðiþ2Þ turns low, signals SB�ðiþ3Þ and eB�ðiþ3Þ turn high andCB�ðiþ2Þ shares its charge with CB�ðiþ3Þ, leaving a voltage ofVref =2

iþ1 at both capacitors. This process continues until the LSB(DB) is determined, after which the state machine returns to step0. Capacitor Cx is never connected between nodes vþ and v� , sinceits only function is to halve the reference voltage of C0.

The maximum clock rate is limited by the on resistance ron ofthe switches and the DAC array capacitance. In turn, the minimumvalue of ron is limited by the maximum size of the switches. Largerswitches imply larger parasitic capacitances, which degrade thecharge-sharing process due to the capacitive voltage divider

composed by the array capacitances and the gate-to-source/draincapacitances of the transistors.

Neglecting the parasitic capacitances and assuming perfectmatching between the capacitors of the array, the comparatordifferential input voltage at the i-th step of conversionvPRSin ðiÞ ¼ vPRSðiÞþVOS can be computed as (1). For the PCS ADC [9],vPCSin ðiÞ ¼ vPCSðiÞþVOS can be computed as (2). In both equations, VOS

represents the comparator input-referred offset voltage:

vPRSin ðiÞ ¼ 1i

vid7Vref

27⋯7

Vref

2i�1

� �þVOS ð1Þ

vPCSin ðiÞ ¼ 1

2� 2

2i

vid7Vref

27⋯7

Vref

2i�1

� �þVOS: ð2Þ

Eqs. (1) and (2) reveal the main drawback of these architec-tures, which is their sensitivity to VOS [16]. It can be seen thatVOS=vPCSðiÞ doubles after a few conversion steps, whereasVOS=vPRSðiÞ increases proportionally with the conversion step. Thislimits the maximum resolution achievable by the PRS ADC, unlessoffset calibration techniques are implemented.

The energy consumed by the PRS ADC from the referencepower supply EPRSref can be computed as (3), whereas EPCSref can becomputed as (4). In both equations, Ctot represents the totalcapacitance of the capacitor array:

EPRSref ¼ 12ðBþ1ÞCtotV

2ref ð3Þ

EPCSref ¼ CtotV2ref : ð4Þ

For a given Ctot , EPRSref is lower than EPCSref by a factor of 2ðBþ1Þ.Additionally, considering that CPRS

tot ¼ ðBþ1ÞC and CPCStot ¼ 2B�1

� �C,

where C represents the smallest capacitance of the capacitor array,without taking into account the consumption of the digital circuitsand the comparator consumption, and omitting noise considera-tions, the energy consumed by the PRS ADC does not depend on B,and it is lower than that of the PCS ADC by a factor of 2 2B�1

� �.

3. Non-idealities due to parasitic capacitances

The circuit schematic for the parasitic capacitances analysis isdepicted in Fig. 3. Subscript t stands for top, b for bottom, m formiddle, l for left, and r for right. Therefore, Cr is the capacitorconnected to the comparator input, Ctr and Cbr represent the topand bottom parasitic capacitances to ground at nodes vtr and vbr ,respectively, Cl is the next capacitor to be connected to the comparatorinput, and Ctl and Cbl represent its parasitic capacitances to groundfrom top and bottom terminals, respectively. Capacitors Ctt , Ctb, Cbt

and Cbb, namely parasitic cross capacitances, model the parasiticcapacitances due to factors that depend on the layout.

When connecting Cl and Cr directly (tl to tr and bl to br), Ctt andCbb are short-circuited and capacitances Ctb and Cbt are added to

Fig. 1. Simplified schematic of a B-bit passive reference-sharing SAR ADC.

E. Alvarez-Fontecilla, A. Abusleme / Microelectronics Journal 46 (2015) 750–757 751

the total capacitance at the comparator input (Cm in Fig. 3). Whenconnecting Cl and Cr inversely (tl to br and bl to tr), Ctb and Cbt areshort-circuited and capacitances Ctt and Cbb are added to Cm. Asshown in Fig. 3, the analysis can be split into two steps. Assumingthat Cl and Cr are connected directly, the first step consists ofconnecting, separately, capacitors Ctl and Ctr , capacitors Cl, Cr , Ctb

and Cbt , and capacitors Cbl and Cbr . Thus, Ct, Cm and Cb can be

readily computed as

Ct ¼ CtlþCtr ð5Þ

Cm ¼ ClþCrþCtbþCbt ð6Þ

Cb ¼ CblþCbr ð7Þ

and voltages v0t , v0m and v0b can be computed as

v0t ¼CtlvtlþCtrvtr

Ctð8Þ

v0m ¼ ClvmlþCrvmrþCtbvtl;brþCbtvtr;blCm

ð9Þ

v0b ¼CblvblþCbrvbr

Cbð10Þ

where va;b9va�vb. In the second step, Ct, Cm and Cb are connectedand the node voltages can be computed according to the excessvoltage of the previous step Δ¼ v0bþv0m�v0t and the effect of thecapacitor voltage divider of the resulting circuit on Δ as follows:

vt ¼ v0tþΔCm JCb

Cm JCbþCtð11Þ

vp

vm

v+

v-

Vrp

Vrm

vidVref2

Vrp

Vrm

Vref2

00

VrcmVrcm

Vrcm Vrcm

vidVref

2Vref

4D0 1 (MSB)Vref

4

Vref4

D2Vref

8

D3

D4 (LSB)

Vref8

D1=0D1=1

Vref8

Vref8

D1=0D1=1

D2=0D2=1

Vref8

D1=0D1=1

D2=0D2=1

D3=0D3=1

C3C2C1C0Cx

C3C2C1C0Cx

C3C2C1C0Cx

C3C2C1C0Cx

Step 0:

Step 1:

Step 2:

Step 3:

Step 4:

C1 C2 C3C0Cx

v-

v+

v-

v+

v-

v+

v-

v+

Fig. 2. Illustration of the step-by-step operation of a B ¼ 4-bit passive reference-sharing SAR ADC.

CrCl

vtr

vbr

vtl

vbl

+

-

+

-

CtrCtl

Cbl Cbr

Ctt

Cbb

Ctb Cbt

Cr

vt

vb

-

Ctr

Cbr

-

+

-

+

vmCm

+

-

Ct

Cb

-

+

-

+

vm'

vt'

vb'

vmrvml

Ctl

Cl

Cbl

Step 1 Step 2

CbtCtb

+

Fig. 3. Circuit schematic for parasitic capacitances analysis.

E. Alvarez-Fontecilla, A. Abusleme / Microelectronics Journal 46 (2015) 750–757752

vm ¼ v0m�ΔCt JCb

Ct JCbþCmð12Þ

vb ¼ v0b�ΔCm JCt

Cm JCtþCbð13Þ

where xJy9xy=ðxþyÞ. In order to compute the node voltageswhen the comparator decision leads to an inverse connection of Cl

and Cr , subscripts tl and bl must be swapped, and Ctt and Cbb mustbe used instead of Cbt and Ctb, respectively.

Taking into account that the capacitance of each individualcapacitor in the array is C, let us assume that parasitic capacitancesto ground of each capacitor are symmetrical and can be modeledas αC; and that parasitic cross capacitances are equal and can bemodeled as γC. Considering these assumptions, Cr and Ctr (equal toCbr) at the i-th step of the conversion (for iZ2) can be expressedas

Cr ¼ Cði�1Þþ2γCði�2Þ ð14Þ

Ctr ¼ αCði�1Þ ð15Þand the results shown in (11)–(13) along with the excess voltage Δcan be written as

Δ¼ vml1þγ

iþ2γði�1Þ�1i

� �

þvmr1i� 1þγiþ2γði�1Þ

� �ð16Þ

vt ¼1ivtlþ 1�1

i

� �vtrþΔ

1

2þ iαiþ2γði�1Þ

ð17Þ

vm ¼ vml1þγ

iþ2γði�1Þ

� �

þvmr 1� 1þγiþ2γði�1Þ

� �

�Δ1

1þ2iþ4γði�1Þiα

ð18Þ

vb ¼1ivblþ 1�1

i

� �vbr�Δ

1

2þ iαiþ2γði�1Þ

: ð19Þ

To compute the node voltages when connecting Cl and Cr

inversely, subscripts tl and bl must be swapped and vml must bereplaced by �vml.

Assuming α¼ 0 and γ ¼ 0, the results shown in (16)–(19) canbe further simplified to

Δideal ¼ 0 ð20Þ

videalt ¼ 1ivtlþ 1�1

i

� �vtr ð21Þ

videalm ¼ 1ivmlþ 1�1

i

� �vmr ð22Þ

videalb ¼ 1ivblþ 1�1

i

� �vbr : ð23Þ

Based on the comparison between (16)–(19) and (20)–(23),several conclusions can be drawn. As seen in (16), Δ is a non-ideality produced by the parasitic cross capacitances when theparasitic capacitances to ground are symmetrical. Moreover, sym-metrical parasitic capacitances to ground do not affect the idealperformance of the circuit when γ � 0. Fig. 4 shows the maximumtolerable value of γ as a function of α for different values of B. To

obtain these curves, behavioral simulations were run sweeping γfor fixed values of α. The selected values of γ are the ones forwhich there were no lost codes in the converter transfer function.It can be observed that large parasitic capacitances to ground(α⪢γ) help to mitigate the effect of γ without affecting theconverter performance. When increasing γ for a fixed value of α,the end-point codes are susceptible to move out of the full-scaleinput range. Therefore the parasitic cross capacitances effectresults in a resolution reduction, since there are fewer codes torepresent the whole input voltage range.

4. Noise analysis

Given that the operation of the PRS ADC requires a largenumber of switching steps, the contribution of the kT/C noiseposes a limit on the resolution of this architecture. After the track-and-hold step, each capacitor holds a voltage noise power of kT/C.Then the RS process makes the capacitors share their initial noisecontributions, adding another kT/C contribution to every capacitorthat shares its charge. At the end of the RS process, each capacitorholds the effects of fractions of different noise processes, which arecorrelated to fractions of the noise held by other capacitors in thearray. Let us call ðkT=CÞi the total integrated noise at the capacitorCi after the track-and-hold step, and ðkT=CÞi;i�1 the noise con-tribution added to capacitors Ci and Ci�1 after Ci shares its chargeto Ci�1. Then, after the RS process finishes, the worst-case totalintegrated noise NCi

at each capacitor (see Fig. 1) can be computedas

NCB� 1 ¼kTC

� �B�1

ð24Þ

NCB� 2 ¼kTC

� �B�2

ð25Þ

NCB� 3 ¼14

kTC

� �B�3

þ14

kTC

� �B�4

þ kTC

� �B�3;B�4

ð26Þ

NCB� 4 ¼14NCB� 3 þ

14

kTC

� �B�5

þ kTC

� �B�4;B�5

ð27Þ

and so on. For the worst-case scenario, and considering that kT/Ccontributions with the same subscript are correlated and must beadded as signals, the input-referred noise due to the RS process asa function of the number of bits NRSðBÞ can be computed as

NRSðBÞ ¼XB�1

i ¼ 0

NCi: ð28Þ

Fig. 4. Maximum tolerable value of γ vs. α for different values of B.

E. Alvarez-Fontecilla, A. Abusleme / Microelectronics Journal 46 (2015) 750–757 753

The SA process also contributes to the ADC noise, and it can beshown by using the equipartition theorem that is given byNSAðBÞ ¼ ð1�1=BÞðkT=CÞSA. Therefore, the total input-referred noisevariance as a function of the number of bits NðBÞ can be computedas

NðBÞ ¼XB�1

i ¼ 0

NCiþB2 1�1

B

� �kTC

� �SAþV2

n;comp

� �

NðBÞ ¼XB�1

i ¼ 0

NCiþBðB�1Þ kT

C

� �SAþB2V2

n;comp ð29Þ

where factor B2 is due to the attenuation of the signal at thecomparator input evidenced in (1), and V2

n;comp is the input-referred noise voltage of the comparator. Table 1 shows theinput-referred noise variance as a function of the number of bitsB, normalized to kT/C, computed using (29) and omitting thecontribution of V2

n;comp. These factors are also depicted in Fig. 5.For instance, for a B-bit converter in a 180-nm technology using

Vref ¼ 1:8 V, the minimum value of C could be determined accord-ing to the design consideration NðBÞr ðLSB=2Þ2, which leads toCZ0:95 fF for B¼ 6, CZ27:1 fF for B¼ 8, and CZ136:4 fF forB¼ 9 for T ¼ 300 K. Of course, these results do not take intoaccount the noise contribution of the comparator nor mismatchconsiderations.

5. Other considerations

Other design aspects of the PRS ADC have also been analyzed,such as the input common-mode voltage effects on the ADCperformance, the minimum capacitance, charge injection effects

of the switches, and the control signals timing considerations.Each one of these topics is detailed below.

5.1. Input common-mode voltage Vccm

To avoid fluctuations of Vccm throughout a conversion, whichmay affect the comparator performance, parasitic capacitances toground must be well matched. Since Vccm is sensitive to therelative difference between the parasitic capacitances, large valuesof α help to mitigate this problemwithout degrading the converterperformance. Assuming perfect matching between the parasiticcapacitances to ground and neglecting the cross capacitances, Vccm

at the i-th step of the conversion can be expressed as

VccmðiÞ ¼ ð1�2� iÞVrcmþ2� ivicm ð30Þso the signal input common-mode voltage vicm and the referencecommon-mode voltage Vrcm should be equal in order to reduce thefluctuations of Vccm.

5.2. Minimum capacitance

The DAC capacitors minimum size is limited either by processmismatch considerations, by the sensitivity of the ADC transfercharacteristics to systematic cross capacitances, or by noise con-siderations. When the resolution is low enough so that noiseconstrains can be neglected, the process mismatch should beconsidered to compute the capacitors minimum size, which canbe determined through Monte Carlo behavioral simulations usingthe Pelgrommismatch coefficients [17]. To determine the effects ofthe cross capacitances, behavioral simulations shall be used. Fig. 6shows the simulated DNL and INL of a 6-bit PRS ADC considering aunit capacitance mismatch of σ ¼ 1:31%. A total of 1000 simula-tions were run, producing a yield of 99.6%.2 It can be observed thatthe mid-range code INL is 0 in all simulations due to thesymmetrical characteristics of this converter architecture.

5.3. Charge injection

During the RS process, when a switch opens, it injects chargethat alters the common-mode reference voltage Vrefcm and thedifferential reference voltage Vrefdif [18]. Assuming that charges Qt

and Qb are injected at the top and bottom nodes of capacitor C, andassuming symmetrical parasitic capacitances to ground equal to

Table 1Input-referred noise variance as a function of thenumber of bits B normalized to kT/C.

B NðBÞ

1 1 � kT=C2 4 � kT=C3 9:5 � kT=C4 18:6 � kT=C5 30:7 � kT=C6 45:1 � kT=C7 61:9 � kT=C8 80:8 � kT=C9 101:7 � kT=C10 124:7 � kT=C11 149:7 � kT=C12 176:7 � kT=C

Fig. 5. Input-referred noise variance as a function of the number of bits Bnormalized to kT/C.

Fig. 6. Simulated DNL and INL of a 6-bit PRS ADC for 1000 realizations and a unitcapacitance mismatch of σ ¼ 1.31%.

2 Only 0.4% of the realizations presented missing codes.

E. Alvarez-Fontecilla, A. Abusleme / Microelectronics Journal 46 (2015) 750–757754

αC, then Vrefcm and Vrefdif can be computed as

Vrefcm ¼ Videalrefcmþ 1

αCðQtþQbÞ

2ð31Þ

Vrefdif ¼ Videalrefdif þ

1ð2þαÞCðQt�QbÞ ð32Þ

where Videalrefcm ¼ Vrcm and Videal

refdif ¼ Vref =2, Vref =4, Vref =8, and so on.Large values of α help to mitigate the effects of the chargeinjection. CMOS switches shall be used to reduce Qt and Qb, andbootstrap techniques can be used to reduce jQt�Qb j . Also, inorder to reduce Qt and Qb, smaller switches shall be used, resultingin an increase of the dominant time constant and compromisingthe ADC maximum sampling rate.

5.4. Timing considerations

In ordinary SAR ADCs the charge in the input nodes of thecomparator does not change during the conversion, whereas inPCS-based SAR ADCs, the charge changes at every step of theconversion and it is not possible to pull back a decision. Because ofthis, some of the control signals of the PRS ADC must be handledcarefully (see Fig. 1):

� in order to avoid short circuits between Vrcm, Vrp, Vrm, vp andvm, control signals Sið8 iÞ and R should be non-overlapped;

� when sharing the reference voltage, control signals SB� i andSB�ðiþ1Þð8 iZ4Þ should be non-overlapped; and

� in order to avoid the unwanted discharge of the capacitors,control signals ei and gi ð8 iÞ should be non-overlapped.

6. Test results

A 6-bit PRS SAR ADC was designed and fabricated as a proof ofconcept in a 180-nm technology using minimum-size CMOSswitches, custom 100-fF metal-oxide-metal (MOM) capacitorsand the comparator topology of [19]. Fig. 7 shows the layout anda die micrograph of the 6-bit PRS ADC implemented. The PRS ADCis composed by four different parts: a finite-state machine (FSM),which controls the ADC operation; a non-overlapping double-phase clock generator; a DAC array, which includes seven identical100-fF MOM capacitor structures along with their respectiveswitches networks; and a latched comparator with the offlineoffset calibration technique shown in [20]. This converter featuresan area of only 0.0168 mm2, making it the smallest ADC among thedifferent ADCs reported in a 180-nm technology [14].

The custom 100-fF MOM capacitor structure shown in Fig. 8 iscomposed of two comb-shaped multi-layer metal structures inparallel, and was designed in order to obtain large and symme-trical parasitic capacitances to ground of 20 fF. This was achievedby surrounding the parallel metal structures with metal connectedto ground. The structure capacitance (100 fF) and the parasiticcapacitances to ground (20 fF) were extracted using a 3D electro-magnetic solver [21].

For the IC tests, the supply voltage was set at 1.8 V, thereference voltages were set at Vrp ¼ 1:2 V, Vrm ¼ 0:6 V andVrcm ¼ 0:9 V, and the clock frequency was set at f clk ¼ 12:5 MHz.Fig. 9 shows the measured DNL and INL after calibration of thecomparator offset voltage. Considering the mismatch of thecapacitor array and of the parasitic capacitors to ground, a totalmismatch of 26% for the custom 100-fF MOM capacitors wasestimated, which is responsible for the relatively large values ofDNL and INL that can be observed in Fig. 9. Also, it can be observedthat the measured INL is not symmetrical as expected, which isdue to layout asymmetries. In order to improve the PRS ADCperformance, larger capacitors should be used, so that the mis-match is reduced.

At an operation frequency of f s ¼ 1:5625 MS=s, a power con-sumption of P ¼ 2:07 μW was measured without considering thedouble-phase clock generator consumption.3 The double-phaseclock generator alone consumes 29 μW. The measured ENOB andsignal-to-noise-and-distortion ratio (SNDR) for different inputfrequencies is shown in Fig. 10, where it can be seen an ENOB of5.17 bits for a Nyquist input at 780 kHz. According to the valuesshown for the ENOB, and using the FoM for ADCs given byP= 2ENOB � f s

� �, the implemented 6-bit PRS ADC consumes between

30.8 and 39.3 fJ/conv-step. Also, the effective resolution band-width (ERBW) is practically Nyquist (i.e. 780 kHz). Fig. 11 showsthe output spectrum of the implemented PRS ADC for an inputvoltage signal at 700 kHz, where it can be seen that the spurious-free dynamic range (SFDR) is 45 dBc. Table 2 summarizes themeasured results.

Fig. 12, which was taken and edited from [14], shows theimplemented 6-bit PRS ADC compared to different ADCs presentedat the ISSCC and VLSI conferences in terms of energy. In the figure,P is the power consumed and f snyq is the Nyquist sampling rate. Itcan be seen that the PRS topology is a competitive alternative forlow-resolution ADCs.

Fig. 8. Custom 100-fF MOM capacitor layout (a) and micrograph (b). Dimensions:14:265 μm� 14:18 μm¼ 202:3 μm2.

DAC array Comparator

FSM

Double-phaseclock generator

DAC array

FSMDouble-phaseclock generator

Comparator

Fig. 7. Implemented 6-bit PRS ADC layout (a) and die micrograph (b). Dimensions:210 μm�; 80 μm¼ 0:0168 mm2.

3 The power taken from the reference voltage power supplies was estimatedusing (3), and it is equal to 0:12 μW.

E. Alvarez-Fontecilla, A. Abusleme / Microelectronics Journal 46 (2015) 750–757 755

7. Conclusion

A fully differential passive reference-sharing SAR ADC techni-que has been presented, along with its theoretical analysis and testresults. The analysis developed reveals that this technique isapplicable for low-rate, low-resolution ADCs, since noise, offsetand parasitic capacitances limit the design space. The converterimplemented features a capacitance spread of one, a die area of0:0168 mm2 and a low-power consumption of 2:07 μW. Thedetailed analysis shows that the parasitic capacitances to groundmust be well matched, the cross parasitic capacitances betweenadjacent capacitors in the array must be minimized, and that boththe comparator input-referred offset and noise limit the converterresolution.

Acknowledgements

This work was supported by the National Commission forScientific and Technological Research (CONICYT) of Chile, underGrant FONDECYT 11110165.

The authors would like to thank SYNOPSYS for their academicagreement program and Delft University for providing a freelicense of Space 3D.

The authors would also like to thank the reviewers for theirvaluable comments and observations during the review process ofthis paper.

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