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Feng-Xiang Huang M•CORE Architecture implements Real-Time Debug Port based on Nexus Consortium Specification David Ruimy Gonzales Senior Member of Technical Staff Motorola M•CORE TM Technology Center Austin, Texas [email protected] 111/06/27

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Paper Report. M•CORE Architecture implements Real-Time Debug Port based on Nexus Consortium Specification. Feng-Xiang Huang. David Ruimy Gonzales Senior Member of Technical Staff Motorola M•CORE TM Technology Center Austin, Texas [email protected]. My Research Tree. - PowerPoint PPT Presentation

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Page 1: Paper  Report

Feng-Xiang Huang

M•CORE Architecture implements Real-Time Debug Port based on NexusConsortium Specification

David Ruimy GonzalesSenior Member of Technical StaffMotorola M•CORETM Technology Center Austin, [email protected]

112/04/21

Page 2: Paper  Report

Combining Scan and Trace Buffers for Enhancing

Real-time Observability in Post-Silicon Debugging

2010

Combining Scan and Trace Buffers for Enhancing

Real-time Observability in Post-Silicon Debugging

2010

A Scan Cell Design for Scan-Based

Debugging of an SoC With Multiple Clock

Domains2010

A Scan Cell Design for Scan-Based

Debugging of an SoC With Multiple Clock

Domains2010

NIFD: Non-Intrusive FPGA Debugger

Debugging FPGA ‘Threads’ for Rapid HW/SW Systems

Prototyping 2010

NIFD: Non-Intrusive FPGA Debugger

Debugging FPGA ‘Threads’ for Rapid HW/SW Systems

Prototyping 2010

A Design-for-Debug(DfD) for NoC-based SoC Debugging via NoC

2008

A Design-for-Debug(DfD) for NoC-based SoC Debugging via NoC

2008

A Low-Cost SOC Debug Platform Based on On-Chip Test Architectures

2009

A Low-Cost SOC Debug Platform Based on On-Chip Test Architectures

2009

A High-Level Debug Environment for

Communication-Centric Debug2009

A High-Level Debug Environment for

Communication-Centric Debug2009

Exploiting an I-IP for both Test and silicon Debug of

Microprocessor Cores2005

Exploiting an I-IP for both Test and silicon Debug of

Microprocessor Cores2005

Scan application Debug IP HW/SW

IEEE 1149.1 JTAGIEEE 1149.1 JTAG

Nexus 5001 ForumTMNexus 5001 ForumTM

Standard

Page 3: Paper  Report

For Tool Vendors

Highly integratedHighly integrated

How Programs flowHow Programs flow

Tradeoff between Performance & VisibilityTradeoff between Performance & Visibility

Difficult Offer consistent functionality across architecture to tool venders

Difficult Offer consistent functionality across architecture to tool venders

Page 4: Paper  Report

What’s Nexus Nexus is standard, real-time interface for embedded process.

。 On-chip debug features

。 Protocols

。 Pin

。 Interface to externals tool

Companies: Motorola, Siemens, Hitachi, …,24 companies anticipated.

Nexus provides a toolbox of features for processor debug Support existing debug interface JTAG Auxiliary trace debug interface Simple packet based message protocol Define classed for standard with increasingly complex implement

Page 5: Paper  Report

Real-time informationReal-time information

Variable LevelsVariable Levels

Static debugStatic debug

Dynamic debugDynamic debug

Page 6: Paper  Report

A Scalable Port

EVTI: Nexus Event Input

EVTO: Nexus Event Output

MSEO: Nexus Message Start/End Output

MCKO: Nexus Message Clock Output

MDO: Nexus Message Data Output

RDY: Nexus Ready Output

Page 7: Paper  Report

Half duplexHalf duplex

Full duplexFull duplex

More Complexity More Complexity

High Performance High Performance

Class 1: Compliancy JTAG Basic Run-Control

Class 1: Compliancy JTAG Basic Run-Control

Class 2,3,4: Auxiliary debug interface

Class 2,3,4: Auxiliary debug interface

Static debug features Static debug features

dynamic debug features dynamic debug features

Variable Message-basedSimple trace compress

Variable Message-basedSimple trace compress

Page 8: Paper  Report

Packet-based data Monitoring Program Flow

。Ownership Message: process identification。Branch Trace Message: program counter’s change of flow。Watchpoint Message:

Data Trace Messages。Reporting real-time specific data accesses to memory location

Memory substitution Messages。Emulate a bus where opcodes and data may be accessed.

Auxiliary Access Messages。Read/Write auxiliary control and status registers.

Page 9: Paper  Report

The first implementation of this proposed standard

Low pin count

Low power consumption

OnCETM

debug block JTAG protocol Limited observation of real-time program flow

Page 10: Paper  Report

Auxiliary interfaceAuxiliary interface

JTAG interfaceJTAG interface

16 Deep FIFOReal-time Message

16 Deep FIFOReal-time Message

Class 1Class 1

Page 11: Paper  Report

Class levels classified a scalable debug needs for specific debug stages

Standardize on a set of features, protocols…, etc. Rapid development of real-time microcontroller based products.

。Time to Market It is Benefit of tool Vendors, providing an standardized on a set of features.

Page 12: Paper  Report

It is benefit not only tool vendors, but designer.

It emphasizes the message of Nexus defined, not talks more detail about protocol of Auxiliary interface. FIFO design of control protocol is key using by auxiliary port, Message format also is.