pALPIDEfs Digital periphery

Alberto Collu

University and INFN of Cagliari

Scheme of pALPIDEfs

Region0

(16 doublecolumns)

Region1

(16 doublecolumns)

Region30

(16 doublecolumns)

Region31

(16 doublecolumns)

512rows

1024 columns

Digital Periphery

ANALOG BIAS

Power, Analog Pads, Digital Pads

RO logic 0

RO logic 1

ANALOG BIASRO logic

30RO logic

31

Alberto Collu

Main operating modes

• Configuration mode Full access to the registers (hamming code, triple voting) and memories Self Test: automatic test that - identifies double columns where there are faulty pixels - identifies faulty memory locations (containing at least one bit stuck at 0 or 1)

• Readout Mode Matrix readout at trigger arrival 2 types: Readout mode A , Readout mode B Features: clustering, on the fly double column disabling

• Pattern Generator Pattern loaded in the data RAMs in config mode The loaded pattern is sent out throught the data port once Pattern

Generator mode starts Previously thought to be used to test the serializer, it may be useful to

test the periphery sequentialization logic (SEU measurements?)

Alberto Collu

• Allows read and write access to: Periphery Registers (for debug and configuration) Memory locations (no access during readout)

• Fully synchronous protocol (10 MHz clock max in pALPIDEfs)

• Pads: TCK : JTAG clock TMS : JTAG SM control signal TDI : serial input TDO : serial output

• Possibility to configure chips in a daisy chain TDI[i] -> TDO[i+1] TDO[i-1] -> TDI[i] common TCK and TMS

• JTAG operation time duration < 5 us @ 10MHz: Total time to write all the registers < 1 ms at 10 MHz Total time to write all the registers/memory locations < 45 ms

JTAG Port

Alberto Collu

Configuration mode

• Bias 6 voltages , one hot encoding (8 bits) 5 currents, thermometer encoding (8 bits) DACMONV and DACMONI pad functionalities

Monitoring Override (internally generated voltages and currents can be overriden)

• Matrix readout disabling Region readout disabling Double column readout disabling

• In-pixel registers Mask registers Pulse registers State registers

• Read and write of DPRAM memories 32 DPRAM 16x16 (used in readout mode to store the length of each event in

each region) 32 DPRAM 256x16 (used to store the pixel data in each event and in each

region) Alberto Collu

Readout modes

Alberto Collu

• Readout mode A In-pixel status registers continuously enabled Latch on hit

• Readout mode B In-pixel status registers enabled at trigger arrival for a fixed time

duration Latch on trigger

7Alberto Collu

Periphery readout architecture

• Columns belonging to a region are read in sequence by the same logic at trigger arrival

• Data read in each region is written into a memory

• The 32 memories are read sequentially by the same logic

MEM 0

MEM 31

32 regions of 16 double columns each

Event Data Port

0 310 15 0 15

The readout of each reagion is done independently due to the presence of data memories (one per region)

Each memory acts as a derandomizing buffer, being written at the trigger arrival and read in a sequence

Region Readout

512rows

Dou

ble

Colu

mn

0

Dou

ble

Colu

mn

1

Dou

ble

Colu

mn

14

Dou

ble

Colu

mn

15

32 columns

Clustering

Data memory

1. Each region contains 16 double columns

2. A priority encoder in each double column gives a readout order to the hit pixels

3. An end of column priority encoder reads in sequence the 16 double columns

4. A clustering algorithm is implemented that reduces the data throughput of the chip

5. The data is written into RAM memories

Alberto Collu

SM

Evt Len memory

Clustering

Cluster size(2 bits)

Double Column (4 bits)

Pixel address (10 bits)

• Not properly a clustering but a data compression algorithm

A hit may be seen as more than one cluster (for example clusters with hit pixels in 2 adjacent double columns)

The amount of data per cluster depends on its position and size

• Encodes in 16 bits the information of up to 4 consecutive hit pixels in a double column:

Pixel address inside of a double column Double column address Cluster size (number of consecutive hit pixels)

Clustering

3 1 3 1 3 1 3 1

2 0 2 0 2 0 2 0

7 5 7 5 7 5 7 5

6 4 6 4 6 4 6 4

11 9 11 9 11 9 11 9

10 8 10 8 10 8 10 8

1115

1113

1115

1113

1115

1113

1115

1113

1114

1112

1114

1112

1114

1112

1114

1112

1119

1117

1119

1117

1119

1117

1119

1117

1118

1116

1118

1116

1118

1116

1118

1116

1023

1021

1023

1021

1023

1021

1023

1021

1022

1020

1022

1020

1022

1020

1022

1020

DoubleColumn 0

DoubleColumn 1

DoubleColumn 14

DoubleColumn 15

Seen as 4separate pixels

Seen as 2 clusters

of 2 pixels each

Seen as a cluster of4 pixels

Alberto Collu

• Parallel port no serializer in this prototype

• Dedicated port output port used to send the event data out of the chip

• Pads:

EVT[7:0] : 8-bit wide data bus EVT VALID : data valid flag READY : data flow control

• Event Data Format (in each region): Header containing the region number and the event

length Data words containing hit pixel data. The number of

data words recorded in an event by a region is given by the event length

Event Data Port

Alberto Collu

Pulse and Mask operations

• Mask operation Used to mask single pixels in the matrix that are stuck at high value Normally performed in configuration mode Not possible to mask automatically faulty pixels during the readout

(entire double columns can be masked automatically) User can mask single pixels, groups of pixels such as rows or columns or

the entire matrix even in readout mode if needed - Could be useful to keep the priority encoders silent while not reading the matrix (coupling analog-digital?)

• Pulse operation Can be used to test single pixels Performed in readout mode Addressing of the pixel to be pulsed via JTAG port The pulse is provided directly through the dedicated PULSE pad The address of pulsed pixels is obtained by triggering the chip via the

STROBE pad

Alberto Collu

Technical difficulties in digital periphery development

Alberto Collu

• Area: Problems with low availability of horizonthal routing channel Use of TJ DPRAM memories (height 265 um) routed in 4 metal

layers does not allow to have a very thin digital periphery (less than 400 um, 450 um in pALPIDEfs).

Could be decreased by using FF based memories (50% less occupancy for the small memories, routing only in 2 metal layers)

Digitalperiphery

height(450 um)

TJ memoryheight

(265 um)

Alberto Collu

• Power Consumption: No low power techniques adopted (clock gating, disabling of

memories) Dominated by:

Switching of the clock tree Internal power consumption in the memory blocks

Estimated to be 300 mW for nominal values Could be decreased significantly (a factor 5 at least) by disabling

the memories when not used and by adopting a clock gating scheme (when possible)

•Timing: Issues in worst cases due to the width of the digital periphery (3

cm) Issues in some half-cycle timing paths (memory side)

Technical difficulties in digital periphery development