Overview of Studies on the SPIROC Chip Characterisation · A schematic view of a single channel of the ASIC chip is given in Fig. 1. 3 Test-Bench Description The characterisation

EUDET-Report-2009-05

Overview of Studies on the SPIROC Chip

Characterisation

R. Fabbri∗, B. Lutz†, W. Shen‡

November 19, 2009

Abstract

The SPIROC chip is a dedicated very front-end electronics for an ILC hadroniccalorimeter technical prototype with Silicon Photomultiplier (or MPPC) readout.This ASIC is due to equip a 2,000-channel demonstrator in 2009. The SPIROCchip is the successor of the ILC SiPM ASIC presently used for the ILC AHCALphysics prototype, incorporating additional features like auto-triggering, pipelines,digitization as well as power pulsing. Realized in 0.35um SiGe technology, it isdesigned in order to fulfil ILC final detector requirements of large dynamic range,low noise, low power consumption, high precision and large number of channels.The SPIROC is a 36-channel chip. Each channel has bi-gain amplification, auto-triggering capability, a 16-bit depth analog memory array and a 12-bit WilkinsonADC. It allows time and charge measurements at the same time with digitiseddata output. The digitization is controlled and read out by the digital part of thechip. After the submission in June 2007, extensive measurements have been carriedout to characterize the chip. The results on the analogue part of the ASIC arepresented in this work. The chip has been proven to be successful in calorimetercalibration as well as real physics experiments.

∗DESY, Hamburg†DESY, Hamburg‡University of Heidelberg

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Contents

1 Introduction 3

2 SPIROC ASIC Description and Properties 3

3 Test-Bench Description 4

4 Electrical Noise Investigation 6

5 ENC and Input Detector Capacitance 8

6 Pedestals Uniformity 11

7 Trigger Discriminator and Efficiency 11

8 Trigger Time Walk and Jitter 14

9 SiPM Voltage Adjustment 17

10 Low Gain - High Gain Coupling 20

11 Cross Talk between Input Channels 21

12 Track and Hold Switch 22

13 Dynamic Range, Linearity, and Gain of the ASIC 23

14 Amplitude Dependence on Shaping Time 25

15 SiPM Single-Pixel Spectra 28

16 Towards Real Data Taking Conditions 33

17 Conclusions 36

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1 Introduction

The requirements imposed by the high precision physics forseen at the InternationalLinear Collider (ILC) set high demands on calorimetry. The ambitious required jetenergy resolution of σE/E ≈ 0.3/

√E [1] could be achieved by combining the potentials

of the particle flow approach [1] with extremely segmented (in both transverse andlongitudinal directions) electro-magnetic (ECAL) and hadronic (HCAL) calorimeters.The ECAL design is based on a Si-W sampling structure with sensitive silicon pads of1 cm2 surface. The prototype will consist of approximately 10000 channels. A group ofthe CALICE collaboration has developed the analog option for the hadronic calorime-ter (AHCAL) based on a sampling structure with scintillating tiles (of smallest size3x3x0.5 cm3) individually readout by Silicon Photo-Multiplier (SiPM) mounted on eachtile.The SiPM is a pixelated avalanche photo-diode operated in limited Geiger mode. Thedetector surface typically of few mm2 is divided into hundreds to thousands pixels. Theanalog output is obtained by adding the response of all pixels firing as independentdigital counters. SiPMs are operated at 2-3 volts overvoltage. Given an internal pixelcapacitance Cpixel of typically 50 fF, the charge collected for one photoelectron signal isapproximately 1.2 pC (equivalent to ≈ 7.5 · 105 electrons). The SiPM offers a very fastresponse with a typical rise time of 3-5 ns. The dynamic range is determined by thefinite number of pixels and reaches ≈ 92 pC.In order to test the feasibility of the particle flow approach prototypes of both ECALand HCAL are being built by the CALICE collaboration and being tested in a combinedtest beam experiment. To meet the needs of the analog HCAL prototype it was decidedto adapt the design developed for the ECAL front-end electronics to read the SiPMsignal. This ILC-SiPM ASIC has been used during the test-beam runs at CERN andFNAL in 2006-07 and 2008-09, respectively. SPIROC is an evolution of the ILC-SiPMto be used for the next generation of ILC AHCAL prototype. In the following the mainfeatures of the new ASIC, version SPIROC 1B, proposed for the readout are describedand its properties analysed. More specificately, the results on the analogue part of thechip are presented in this work. When reading out signals from photon detectors, SiPMsfrom MEPhy/Pulsar, identical to the devices used in the AHCAL test beam operations,were used. These SiPMs have a 1x1 mm2 surface divided into 1156 pixels.The on going investigation of the digital component of the ASIC, implemented in theversion SPIROC 2, will be presented in a separate future note.

2 SPIROC ASIC Description and Properties

The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadroniccalorimeter with silicon photomultiplier readout. This ASIC has been designed anddeveloped by OMEGA at Orsay [2].SPIROC was submitted in Fall 2007 and being tested since then. It embeds cuttingedge features that fulfil ILC final detector requirements. It has been realised using

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Figure 1: SPIROC: one analog channel structure.

AMS 0.35 µm SiGe technology, and developed to match the requirements of large dy-namic range, low noise, low power consumption, high precision and large number ofreadout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC whichallows to measure on each channel the charge from one to 2000 photoelectrons and thesignal timing with a 100 ps accuracy TDC. The integrated ASIC components allow 16selectable pre-amplification gain factors (with output gain values from 3 to 100 mV/pC),and seven CR(RC)2 shaping times from 25 to 175 ns. After shaping, the signal is held atits maximum amplitude with a track and hold method. For each channel, an analogue 16slots memory array is used to store the time information and the charge measurement,and a 12-bit Wilkinson ADC has been embedded to digitise the analogue memory con-tent (time and charge for the two gain modes). The data are then stored in a 4 kbytesRAM. A very complex digital part has been integrated to manage all theses features andto transfer the data to the data acquisition system. An adjustable 8-bit DAC (0-4.5 V)in the ASIC allows individual adjustment of the SiPM forward voltage for each one ofthe 36 channels.A schematic view of a single channel of the ASIC chip is given in Fig. 1.

3 Test-Bench Description

The characterisation measurements of the SPIROC chip were performed at DESY. Thetypical set up of the test bench is shown in Fig. 2. A digital pulse voltage generator(STS DG535) provides a rectangular signal at 10 kHz rate and with variable amplitudeup to 4 V. Additionally, a 20 dB attenuator (10 factor attenuation) is inserted in thesignal line. To simulate a real current signal from SiPMs, the generated squared signal

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hold

ASICpulse generator

50Ω

−20dB

100 pF

STS DG 535

ADC module

CAEN V785N

gategenerator

bufferamplifier1x or 9x

VME CAEN 8002

Figure 2: Typical test bench set up for the commissioning of the SPIROC chip at DESY.

is driven through a coupling capacitor (C = 100 pF) and a resistor (R = 50 Ω) locatedbefore the input channels in the SPIROC board, resulting in a characteristic decay timeτ = 5 ns for the current signal.The signal is then injected in one of the 36 input channels, and the processed outputsignal can be measured either at the oscilloscope (Tektronix TDS 3034B, running at300 MHz bandwidth with 2.5 Gs/s sampling rate) or directly via an external ADCmodule (CAEN V 785N), accommodated in a VME create (CAEN 8002). The dataacquisition is performed via a LINUX machine connected to the VME crate. The pulsegenerator is also connected to the LINUX machine, and is driven by scripts, allowing,together with the acquisition, for automatic, flexible, and systematic measurements in alarge parameters space using SHELL scripts. Via an USB connection the chip is drivenby a LabView user interface running under WINDOWS because the USB driver to steerthe chip is not available for LINUX systems. This restricts the automation and flexibilityof the measurements performing the scan of the ASIC related parameters. The portingof this software to a LINUX platform is ongoing.A buffer amplifier, built at DESY, was often used (before the ADC input channels) to

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improve the precision of the measurement, as in the noise studies.

4 Electrical Noise Investigation

The noise affecting the processed signal out of the board was measured at differentworking conditions of the chip. Additional sources can superimpose to the chip noiseduring the measurement, as the USB-connection to the computer driving the board, theclock on the board which handles the input/output communications with the computer,and the connections to the pulse generator for the input and hold signals.After disconnecting these additional noise source from the board, the noise was measuredas the RMS of the analogue output signal. The dependence of the noise on the variablecapacitance in the preamplifier stage of the chip is shown in Fig. 3, for both high andlow gain operation modes. The expected 1/Cgain dependence in the high gain mode isobserved. The noise reaches its asymptotic value for the largest feedback capacitanceinvestigated value. For the low gain mode, where the amplification is one order smallerthan for the high gain mode, no dependence is visible, being the noise dominated by theeither the chip or the experimental board (the noise from the external ADC module wasmeasured to be up to 0.1 mV).The dependence of the chip noise on the shaping time values is presented in Fig. 4. Analmost linear dependence in the high gain mode is observed, while for the low gain modeno dependence is visible, similarly to what observed for the dependence on the feedbackcapacitance.The uniformity of the noise in the SPIROC 36 input channels was also investigated,and the result of the measurement is presented in Fig. 5, for the chip operating in high

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Figure 3: The chip noise is measured versus the variable capacitance in the preamplifierstage, for 50 ns shaping time.

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Figure 4: The chip noise is measured versus the shaping time for 400 fF variable capac-itance in the preamplifier stage.

gain mode, at 50 ns shaping time, and 400 fF variable capacitance in the pre-amplifierstage. The measured noise is uniform within fractions of millivolts, well enough for thechip purposes. Although the upper half of channels appears to have a higher noise, thisfeature was not furtherly investigated being the effect negligible.The largest effect superimposed to the electrical noise is given by using the track andhold switch to hold the pre-amplified and shaped signal at its peaking amplitude. Anincrease of the noise up to a factor 2-3 is observed in the output signal, Fig. 6. With

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Figure 5: The noise is measured independently for all the 36 input channels of the chipin high gain mode.

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Shaping time: 50 ns

Feedback capacitance: 400 fF

High Gain

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High Gain

Shaping time: 50 ns


With T. & H.: Without T. & H.:

Figure 6: The chip pedestal and noise are measured in high gain mode for 50 ns shap-ing time and 400 fF feedback capacitance. The distributions were obtainedseparately while keeping the track and hold component switched on and off(hatched and filled histograms, separately). The USB connection to the driv-ing PC, and the internal clock were left on during these measurements.

the used setup we could not distinguish between an increase of the noise or of thesensitivity to the noise (due to the increased bandwidth induced by the track and holdswitch). Instead, a negligible effect is observed by the switching on the internal clockfor input/output communication with an external driving interface (via USB port), andby plugging the USB connector into the board, Fig. 7. In normal data taking conditionsthe ASIC is supposed to process the incoming signals via the track and hold componentswitched on. Therefore it is important also to measure its impact on the measured noisedependence on the preamplifier gain, Fig. 8. Consistently with what shown in Fig. 6,an increase of the noise up to approximately a factor 3 is observed at Cgain = 1500 fF.

5 ENC and Input Detector Capacitance

Sofar the electrical noise of the stand-alone ASIC was investigated, without any inputsignal line connected to the board. Connecting a SiPM to the readout system is expectedto increase the noise, depending on the detector capacitance.In principle, a charge-sensitive preamplifier would be favoured [5], providing small sen-sitivity to changes of the parasitic capacitance at its input, as in the case of SiPMswhose capacitance changes with temperature. Nevertheless, in order to cover the largedynamic range of SiPMs, a voltage-sensitive preamplifier was adopted for the chip. Itis crucial therefore to quantify the noise sensitivity to an external variable capacitancecoupled via the connected detector.

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Entries 100003Mean 75.68RMS 0.407

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High Gain

Shaping time: 50 ns


High Gain

Shaping time: 50 ns


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W/O Clock and USB:W/O Clock and W USB:

With Clock and USB:

Figure 7: The chip pedestal and noise are measured while keeping the track and holdcomponent switched off (filled histogram), and in sequence plugging the USBconnector to the board and switching on the internal clock (striped and pointhistograms, separately).

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Figure 8: The chip noise is measured versus the variable capacitance in the preampli-fier stage keeping the track and hold component switched off. The chip wasoperated in high mode at 50 ns shaping time.

Since the signal from the SiPM appears as electric charge, electronic noise will be quan-tified by giving its ’equivalent noise charge’ (ENC), defined as the input charge whichwould be necessary to generate a signal equivalent in amplitude to the measured noiseoutput of the ASIC. This value can be obtained by normalising the noise to a referencesignal. As an example, the signal originating from one photo-electron in the SiPM, and

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Input Coupling Capacitance [pF]0 20 40 60 80 100

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Figure 9: Equivalent noise charge measured while varying the coupling capacitance atthe input signal line.

its corresponding output are considered. Assuming a SiPM gain GSiPM of order 5 · 105

would result in an input charge Qin approximately of GSiPM · e = 80 fC. The corre-sponding output signal Vout for the highest gain was found to be ≈ 7.6 mV (see Sec. 16),obtaining an ENC of order

ENC = VRMS ·Q1pxl

in

V 1pxlout

= VRMS ·80

7.6≈ VRMS · 10.5 [fC · mV −1]. (1)

Here VRMS is the average voltage noise level (in millivolt) appearing at the output.Dividing it by the the electron charge e (in femtocoulomb units) gives the ENC innumber of electrons

ENC = VRMS ·10.5

1.6 · 10−4≈ VRMS · 7 · 104 [electrons · mV −1]. (2)

Using the external pulse generator, the output noise was measured and converted innumber of equivalent electrons following the above formula (2). During the measurement,the coupling capacitance value was varied to simulate the change of the SiPM internalcapacitor. The results of two scans performed in sequence, without any change in thesetup apart replacing the capacitor, are presented in Fig. 9, showing a noise VRMS

increase up to 20% in the range 0-100 pF, from 1.6 to 2.1 mV (corresponding to an ENCvariation from 9·104 to 11.5·104 electrons). According to these measurements, the signalover noise ratio achievable by the SPIROC can be calculated, ranging approximatelybetween 4.7 and 3.6 assuming a SiPM of 5 · 105.To verify that the observed non-reproducibility of the measurements is not given by anyfeature of the ASIC, a series of measurements was taken in sequence at a fixed couplingcapacitance to simulate the detector capacitance. No additional change in the experi-mental apparatus was introduced. The results for two values of the coupling capacitance,

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Output Noise [mV]1.5 1.6 1.7 1.8 1.9 2 2.1 2.2

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High GainInput charge: 0.5 pCShaping time: 50 nsFeedback capacitance: 100 fF




CC: 10 pF: CC: 100 pF:

Figure 10: Distribution of noise measurement performed at two different coupling ca-pacitance values.

Fig. 10, shows a spread in the measurement which is of the order of a fraction of mil-livolt. This is well below the maximum spread observed in the two consecutive scans,thus suggesting a noise source external to the ASIC, possibly due to the experimentalsetup.The measurement of the coupling capacitance dependence of the ENC was performedinjecting 0.5 pC into the ASIC (except for the measurement at zero capacitance, whenthe line was disconnected from the board). To validate the results it should be verifiedthe reasonable assumption that the measured noise is not influenced by the amount ofinjected charge. A measurement of the noise was taken at different values of injectedcharge, and for two values of the coupling capacitance, showing, as expected, no depen-dence, Fig. 11.

6 Pedestals Uniformity

Pedestals were investigated for all the the 36 input channels of the chip, to verify theiruniformity, and are presented in Fig. 12, using the external ADC module. Note thatthe mean values reported here are not the absolute pedestal values, due to an offsetintroduced for convenience in the amplifier before the ADC.The measured spread of pedestals is about 2.3 mV, Fig. 13, a value slightly larger thanwhat reported in [2].

7 Trigger Discriminator and Efficiency

The chip is designed to operate in the so called ’auto-trigger’ mode. The input signalsare first pre-amplified according to both low and high gain line settings. In the highgain section a dedicated 15 ns fast shaping line is also present in parallel to the line tothe analogue memory. There the signal enters a discriminator with a threshold common

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Injected voltage [mV]1 2 3 4 5 6 7 8 9 10

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Shaping time: 50 ns


High Gain

Shaping time: 50 ns


High Gain

Shaping time: 50 ns


CC: 100 pF

CC: 10 pF

Figure 11: The signal noise is measured for different values of the injected voltage fromthe pulse source, and for two extreme values of the coupling capacitance (CC).

to all 36 input lines, and a 120 ns wide trigger is generated whenever the voltage inthe line is above the threshold value set, Fig. 1. The common threshold is tunable bya 10 bits DAC. On top of the common threshold value, each channel threshold can beindividually tuned via a 4-bit DAC.In normal ILC operations the generated trigger is forseen to subsequently hold the pre-amplified signal, processed in the meanwhile by slower shapers, at its amplitude peaking

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Figure 12: Pedestals measured for all the 36 input channels of the chip, using the externalADC module.

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Figure 13: Pedestal distribution for all the 36 input channels.

value. It is therefore crucial to investigate the trigger efficiency and homogeneity for the36 channels.The calibration of the common DAC values was performed, and is shown in Fig. 14. Thethreshold is found to range from 0.35 V up to 2.26 V. The residuals to linearity, foundto be within few millivolts (a fraction of a photon-electron signal), are presented in thesmall insert panel.After having performed the discriminator DAC calibration, the trigger efficiency canbe investigated channel by channel. This is done using a built-in procedure in theLabView user interface. The program increases the threshold level in sequence of DACunits, remains at a fixed DAC value for 200 cycles, and counts the number of triggersgenerated by the pedestal of the investigated channel. It provides thus a measurement

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esid

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Figure 14: The calibration of the common signal threshold 10-bit DAC values into voltunits.

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1205 1210 1215 1220 1225 1230 1235

Figure 15: The trigger efficiency spread for all the 36 input channels in the ASIC, relativeto an injected charge of 100 fC.

of the trigger efficiency, which is presented in Fig. 15 for an injected charge of 100 fC,separately for each of the 36 channels.The increase of the trigger counting is smoothed by the noise amplitude in the line,which was typically found to be around 2-3 mV during that specific measurement, andwas obtained considering the threshold value variation needed to increase the triggerefficiency from 10% to 90%. Also, the maximum efficiency is reached at threshold levelvalues different from channel to channel, with a spread of around 5 mV, resulting ina negligible pedestal spread between all the 36 channels. During forseen data takingoperations, the observed spread can, in principle, be cured tuning the discriminator levelchannel by channel using the forseen 4-bit threshold finer adjustment. At the moment,this feature is not properly working in the released versions of the chip (SPIROC 1 andSPIROC 2), and could not be investigated.

8 Trigger Time Walk and Jitter

As mentioned in Sec. 7, SPIROC is forseen to be used in auto-trigger mode during ILCrunning conditions. It is crucial therefore to investigate the size of the main uncertaintieswhich can affect the trigger timing. Signals with different amplitudes (and same peakingtime) cross the discriminator level at different times, resulting in a time shift (triggerwalk) of the generated processing trigger, left panel of Fig. 16. On top of this uncertainty,the crossing of the discriminator level is varied in time (trigger jitter) by the noise inthe analogue signal, right panel of Fig. 16.The trigger time walk and jitter were investigated injecting a signal from the pulsegenerator, and then measuring at the oscilloscope the timing of the coincidence of thegenerated trigger in the chip with the main pulse generator trigger. Different threshold

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Time jitter

Trigger level

Pedestal

Figure 16: Examples of trigger time walk (left panel) and jitter (right panel).

values for the analogue signals were set (via the LabView interface) at the 10-bit DACdiscriminator (common to the 36 input channels) in the fast shaping line, and differentcharge values were injected, thus allowing for the study of the time walk and jitterdependence on the trigger threshold level and on the amplitude of the input signal. Theshift of the mean and the RMS value of the measured trigger distribution, which isshown for a typical setting in Fig. 17, provide the measurement of the trigger time walkand jitter, respectively. Typical distributions of the trigger timing above described arepresented in Fig. 18.The results of the time walk measurements are shown in Fig. 19, for increasing valuesof the injected charge, from 0.08 up to 1.60 pC (equivalent to one pixel and 20 firing

Figure 17: The trigger signal (light blue) is measured in the oscilloscope in coincidencewith the pulse generator trigger (green). The shift of the mean and the RMSvalue of the trigger distribution provide the measurement of the trigger timewalk and jitter, respectively.

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Figure 18: The trigger timing distribution is presented for the discriminator thresholdvalue set above the pedestal, and for different values of the injected chargein the SPIROC board.

pixels in an AHCAL SiPM, respectively), and of the discriminator threshold level. Thetime walk values are presented with respect to the trigger timing corresponding to thelargest injected charge. When setting the threshold value above the pedestal the timewalk appears to be up to 7 ns only for the first pixel peaks. For a larger number of firingpixels it is within one nanosecond; this feature is observed also for a threshold at abouthalf a mip (SiPMs are configured such that on average 15 pixels should fire due to a mipenergy deposition [3], thus corresponding to 1.2 pC input charge).The trigger jitter dependence on the injected charge, for different values of the discrim-

Discriminator threshold at:

pedestal


0.16 pC


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Injected Charge [pC]

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alk [n

s]

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Figure 19: The trigger time walk is presented for different threshold values of the 10-bitDAC discriminator, and for increasing values of the injected charge in theSPIROC board.

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pedestal


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er Ji

tter [

ns]

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Figure 20: The trigger jitter is presented for different threshold values of the 10-bit DACdiscriminator, and for increasing values of the injected charge in the SPIROCboard.

inator threshold, is presented in Fig. 20. The jitter appears to be up to 1.4 ns, at thesmallest threshold values and for small values of injected charge, while it is within 1.0 nsat a threshold of about half a mip.Concerning the forseen operation of the chip in auto-trigger mode, resolving single-pixelstructure in the SiPM spectra (i.e., in calibration mode) appears to be not infeasible,due to the reasonably small measured trigger jitter and time walk At the moment, theSiPM calibration is expected to be performed via an LED system providing an externaltrigger to the ASIC readout. This issue will be extensively presented in Sec. 15. Instead,the small time walk and jitter values observed at thresholds and input charges abovehalf a mip, should definitely allow the chip to properly operate in the physics mode. Theinfluence of largely varying SiPM gain values, light generation and collection efficiencyhas not been studied in this work.

9 SiPM Voltage Adjustment

The chip is forseen to be connected to an external power supply and to provide a commonhigh voltage bias to all connected 36 SiPMs. Tuning of the applied voltage, channel bychannel, is achieved using an 8-bit DAC HV adjustment dedicated to each detectorpower line, Fig. 21.The calibration of the input HV DAC for all channels is at the moment performed viadedicated LabView interface routines. The applied voltage ranges approximately from0 V to 4.5 V, varying from channel to channel, Fig. 22.The measurements are linearly fitted in the range 10-245 DAC units, and the residualof each measurement to the resulted linear function is calculated. A large channel by

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50

100 nF

Ω10 pF

ASIC

DAC

amplifiershaper

SiPM

cable

100 nF

100k

+HV

Ω

Figure 21: Diagram of the SiPM connection to the ASIC board. The same line is usedfor both power and signal. While a common voltage bias is provided by anexternal power supply to all 36 SiPMs connected to the ASIC, each voltageis tunable via a separate 8-bit DAC HV adjustment.


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Figure 22: Distribution of the minimum applicable voltage via the 8-bit DAC HV ad-justment. Each entry represents the minimum voltage value measured in oneSPIROC channel.

channel variation in the residuals size is observed, and two extreme cases are reportedin Fig. 23.The results show a differential non-linearity on average up to 70 mV, and for somechannels up to 200 mV, Fig. 24, resulting in a relative gain change of approximatively1.8% and 5.2% [4], respectively, and thus providing a potential systematic uncertaintyof similar size to the energy calibration of the detector, in case the observed deviationcannot be systematically reproduced.To investigate the reproducibility of the voltage tuning applied to the ASIC channels,two series of DAC scans (five scan per series) were performed for one channel in separateperiods characterised by a temperature variation of three degrees Celsius. Within eachdata set, the maximum deviation between the measured voltage values was calculated

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1

1.5

2

2.5

3

3.5

4

4.5

5

Channel Nr. 5

0.00138±Offset: 4.49625

0.00001±Slope: -0.01690

Voltage Adjustment Set [DAC]0 50 100 150 200 250

Me

as

ure

d V

olt

ag

e [

V]

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Channel Nr.16

0.00138±Offset: 4.41819

0.00001±Slope: -0.01639

Voltage Adjustment Set [DAC]0 50 100 150 200 250M

ea

su

red

Vo

lta

ge

Re

sid

ua

ls [

mV

]

-100

-80

-60

-40

-20

0

20

40

60

80

100

Channel Nr. 5

Voltage Adjustment Set [DAC]0 50 100 150 200 250M

ea

su

red

Vo

lta

ge

Re

sid

ua

ls [

mV

]

-100

-80

-60

-40

-20

0

20

40

60

80

100

Channel Nr.16

Figure 23: Upper Panels: Calibration of the high voltage DAC adjustment. Lower Pan-els: The residuals of the measurements with respect to the function obtainedby a linear fit.


Max residual per channel [mV]0 20 40 60 80 100 120 140 160 180 200

Yie

ld

0

0.5

1

1.5

2

2.5

3 Entries 36Mean 78.91RMS 39.92

Figure 24: Distribution of the deviation from linearity of the high voltage adjustment.Each entry represents the maximum deviation observed in one channel.

for each DAC value, and is presented in Fig. 25. As expected, for each series of mea-surements the spread increases with the DAC value, i.e. with the amount of current

19


Voltage Adjustment [DAC]0 50 100 150 200 250

Ma

xim

um

Vo

ltag

e D

evi

atio

n [

mV

]

0

2

4

6

8

10

12

CoData taken at T=33CoData taken at T=30

Combined data

Figure 25: The measured maximum deviation of the voltage adjustment applied to theSPIROC channels is presented for two separate DAC scans performed atdifferent temperatures. When combining the measurements of the two datasets the spread increases up to 10 mV.

in the DAC switch, resulting in a maximum systematical deviation up to one millivolt.As a consequence, the observed large differential non-linearity can be corrected via acalibration of channel by channel HV adjustment DAC.Although a negligible deviation is observed among the measurements, when combiningthe two data sets the maximum spread of the measurements increases up to 10 mV.This can be possibly interpreted as due to the large variation of the temperature (upto three Celsius degrees) measured during the systematical studies, resulting in a largerapplied voltage value observed at a lower temperature. In this case, the observed changeof voltage adjustment value could be corrected via a proper calibration. The calibrationmight not be needed in case of small temperature gradient during data taking, since theobserved 10 mV systematical spread is still small compared to the overvoltage of SiPMs,typically of 2-4 V for the devices used in current AHCAL test beam operations [4]. Thus,this spread would correspond to a gain change below 1%.

10 Low Gain - High Gain Coupling

In each input channel of the ASIC the low and high gain paths are electrically coupled,Fig 26. As a result, the charge sharing between the two paths is influenced by thefeedback capacitance value set.In order to estimate the effects of the high-low gain coupling, the output signal in onepath was measured for different capacitance values in the other preamplifier line. Nosignificant effect is observed in the output signal of the high gain line while changingthe amplification in the other line. Instead, a sizable effect (up to 10%) is visible when

20


1.5 pF

Input

15 pF

Slow Shaper

Slow Shaper

50−100 ns

50−100 ns

0.1 − 1.5 pF

0.1 − 1.5 pF

Fast Shaper

15 ns

PreamplifierHigh Gain

Low GainPreamplifier

Figure 26: Electrical diagram of the high gain and low gain paths per single channel inthe ASIC chip.

High Gain Feedback Capacitance [fF]0 100 200 300 400 500 600

Lo

w G

ain

Ou

tpu

t [A

DC

]

40

50

60

70

80 Input charge: 9.6 pC

LG shaping time: 50 ns

LG feedback capacitance: 400 fF










High Gain Feedback Capacitance [fF]0 100 200 300 400 500 600

Lo

w G

ain

Ou

tpu

t [A

DC

]

100

110

120

130

140

150Input charge: 19.1 pC












Figure 27: The output signal (in ADC units) is measured in the low gain path whilechanging the feedback capacitance value for the high gain amplifier. Here pre-sented are two measurements obtained using different values of input chargein the ASIC.

measuring the output signal in physics mode and changing the amplification in the highgain line. An example of the observed correlation is presented in Fig. 27 for different val-ues of the charge injected in the ASIC (using a 6.4 dB attenuator at the pulse generatoroutput).

11 Cross Talk between Input Channels

The chip will handle 36 incoming signal lines. According to previous measurements [2]the estimated cross-talk among the neighbouring channels is below 0.3% for an injectedcharge of 15 pC. The measurement in [2] was presented for few injected charge valuesonly. This investigation of the cross-talk was done performing a wider scan of injected

21


5 10 15 20 25 30 35 40

Sig

na

l ou

tpu

t [m

V]

0

50

100

150

200

Charge injected in channel 5

5 10 15 20 25 30 35 40

Sig

na

l ou

tpu

t [m

V]

-2

-1.5-1

-0.50

0.51

1.52

Injected charge [pC]5 10 15 20 25 30 35 40

Cro

ss

Ta

lk [

%]

-2-1.5

-1-0.5

00.5

11.5

2

channel 4

channel 6

Figure 28: The measurement of the cross-talk is presented for the low gain mode at 50 nsof shaping time, and 400 fF of feedback capacitance.

charge. While increasing the injected charge in steps of 1 pC from one to 40 pC, corre-sponding approximately to the range 1−33 mips, the output signal (pedestal subtracted)was measured in the neighbouring channels. The ASIC was run in low gain mode (physicsmode) at 50 ns of shaping time, and 400 fF of feedback capacitance.An example of the performed measurements is presented in Fig. 28. The output signalin the line where the charge was injected is shown in the upper panel. The reason ofthe observed non-linearity was found in the track and hold switch (see Sec. 12). Inthe neighbouring lines the measured signal is typically within ±0.5 mV in the analysedinput charge range (middle panel), confirming a negligible charge leakage between thechannels. A small trend is visible, within the ±0.5 mV range, moving from small to largeinjected charge. For each charge value the cross-talk (bottom panel) in one channel wascalculated dividing its signal (held at its maximum amplitude) to the correspondingsignal in the line where the charge was injected. As expected by using this method, thecross-talk inflates at small input charge values. At the 15 pC of injected charge, themeasurement is close to what reported in [2].

12 Track and Hold Switch

The chip has to save the amplitude of the pre-amplified and shaped signal at its peakingtime (arrival time of signal maximum). This is achieved using the track and hold switch,Fig. 29, which holds the signal at the amplitude corresponding to a provided holding-trigger arrival, to be tuned to hold the signal at its maximum amplitude.

22


Figure 29: Electrical diagram of the Track and Hold switch.

The peaking time is not expected to depend on the amount of injected charge (mainlydepending instead on the shaper type [6]), and the choice of the holding-trigger shouldhold for all values of input charge. Surprisingly, it was observed that the peaking timevaries with the charge. The signal amplitude was measured with the external ADC whileperforming a scan of the holding-trigger arrival time, in both low and high gain modes,for 50 ns shaping time, and for all possible values of the feedback capacitance. Anexample of these measurements is shown in Fig. 30. In these test-bench measurementsthe hold signal is generated by the external voltage source. Its arrival time can bearbitrarily varied to anticipate or delay it with respect to peaking amplitude of theinjected charge. The measurements show that the peaking time (displayed with a verticalline in each plot) increases with increasing injected charge (while remaining constantonly after reaching saturation), thus suggesting that either the peaking time is chargedependent (contrary to the expectations) or that the track and hold switch somehowinterferes with the signal developing in time.After investigation by the Orsay group, a possible explanation of the observed feature inthe small charge region was proposed [7]. Due to the small bias transistor size in the trackand hold buffer (bottom transistor in Fig. 29) and to the large parasitic capacitance atits output, small input charge will make the buffer enter the non-linear working region.The investigation with simulations is on-going by the Orsay group.

13 Dynamic Range, Linearity, and Gain of the ASIC

During normal AHCAL data taking (low gain) the dynamic range of the ASIC shouldcover the region between one mip and ≈ 77 mips (1156 pixels per SiPM / 15 pixels firingper mip), considering saturation effects in the SiPM due to the limit number of pixels andto the pixel recovery time. Assuming a SiPM gain of the order of 5 · 105 (correspondingto 0.08 pC charge generated per pixel), the covered dynamic mips range corresponds tothe region between 1.2 and 92.5 pC. It should be noted that this upper charge limit

23


0

100

200

300

400

500

0

200

400

600

800

1000

50 100 50 100

Outp

ut Si

gnal

[mV] Qinj : 10 pC

FC: 100 fF

Qinj : 20 pC Q inj : 30 pC

Outp

ut Si

gnal

[mV] Qinj : 40 pC Q inj : 50 pC

Hold Timing [ns]

Qinj : 60 pC

50 100

0

25

50

75

100

125

150

175

200

225

250

0

100

200

300

400

500

600

50 100 50 100

Outp

ut Si

gnal

[mV] Qinj : 10 pC

FC: 300 fF

Qinj : 20 pC Q inj : 30 pC

Outp

ut Si

gnal

[mV] Qinj : 40 pC Q inj : 50 pC

Hold Timing [ns]

Qinj : 60 pC

50 100

Figure 30: The output signal from the ASIC is measured in low gain mode for 50 nsshaping time and for different input charge values, while performing a scanin the hold arrival time. No attenuator on the input line was used.

depends on the specific photodetector gain (MEPhy/Pulsar devices, considered here,have a pixel gain variation between 0.25 · 106 and 1.00 · 106).The chip preamplifier gain should be chosen such to provide a linear response in the wholeenergy range. On this purpose, a scan was performed over all feedback capacitance valuespossible in low gain mode, while increasing the amount of injected charge. For each input

24


charge, it was chosen the hold-trigger timing corresponding to the maximum amplitudefor the output signal measured at the external ADC. This choice was motivated by theimpossibility of performing such a time consuming multi-parameter scan extracting theproper holding-time via the oscilloscope, without an automatised procedure (each singlepoint of the scan was systematically measured several times). Systematic effects arisingby the track and hold switch, as discussed in Sec. 12, might affects the results.The results of this scan, presented in the upper panel of Fig. 31 for 50 ns shaping time,indicate that the minimum feedback capacitance value needed to cover the requiredSiPM dynamic range (77 mips) is 400 fF. Above this value the maximum expected mipsignal can be processed before the ASIC runs into saturation. As a reference, the valuesof the injected charge are also reported in terms of equivalent AHCAL mips values.The sets of data were linearly fit in the range 10-30 pC and the residuals to the linearitywere calculated dividing the deviation of the measured points from the fit results overthe fit values. A non linearity up to 20% is observed with increasing injected charge,bottom panel of Fig. 31. The region where the ASIC saturation appears (anyway notrelevant for the forseen operation of the chip) shows a consistent drop of the residuals.Similar measurements were performed operating the chip in high gain mode, Fig. 32.In this mode, used for calibration, it is preferable to use the largest (smaller) gain(feedback capacitance) to investigate the SiPM single-pixel spectra. The results showthat for 100 fF of feedback capacitance the saturation is reached for values of inputcharge above 10 pC, corresponding to a dynamic range up to ≈ 8 mips, enough forperforming the calibrations. Note that here the linear fit was performed in the range1-3 pC.The observed non linearity is mainly due to the mentioned features of the track and holdswitch, which are under investigation and will be possibly cured in the next generationof the chip. In addition to the observed injected charge dependence of the peaking time,it was also observed that the peaking amplitude obtained via the track and hold switchis typically larger than what observed when the signal is not held.The gain of the chip was calculated out of the same data according to the formulaGASIC = Voutput

Qinput(in mV

pCunits), and is presented in Fig. 33 for different values of the

feedback capacitance CFC in both low and high gain modes at 50 ns shaping time.In the low (high) gain mode the chip amplification factor was measured for 30 pC (3 pC)of injected charge, a value not sizably affected by the non-linearity induced by the trackand hold switch. The expected 1/CFC functional dependence of the gain [5] is observed,quantitatively in agreement with the measurements presented in [2] and [8].

14 Amplitude Dependence on Shaping Time

The effect of the shaping time value on the measured signal peaking amplitude wasinvestigated. The amplitude was measured operating the ASIC in low gain mode fordifferent values of the shaping time and for the feedback capacitance value of 400 fF,Fig. 34. Differently from what presented in Fig. 31, here a 20 dB attenuator was used,

25


FC: 100 fF

FC: 300 fF

FC: 500 fF

FC: 700 fF

FC: 1000 fF

FC: 1500 fF

Shaping time: 50 ns Low Gain


Outp

ut A

SIC

[mV]

Equivalent mips

0

200

400

600

800

1000

0 50 100 150 200 250 300

0 25 50 75 100 125 150 175 200 225 250

FC: 100 fF

FC: 300 fF

FC: 500 fF

FC: 700 fF

FC: 1000 fF

FC: 1500 fF

Shaping time: 50 ns

Low Gain


Resid

uals

to li

near

ity [%

]

Equivalent mips

-60

-40

-20

0

20

40

0 25 50 75 100 125 150 175 200 225 250

0 20 40 60 80 100 120 140 160 180 200

-10

-5

0

5

10

0 20 40

Figure 31: The output signal from the ASIC is measured in low gain mode for 50 nsshaping time and for different input charge values. Upper panel: Resultsobtained using different feedback capacitance values are compared. BottomPanel: Residuals to linearity calculated as described in the text.

to present results at small injected charge in finer binning. Also, results are presentedfor charge values down to 1 pC.The signal peaking amplitude appears to increase with decreasing shaping time, in agree-ment with simulations. The sets of data were linearly fit in the range 1-4 pC and theresiduals to the linearity were calculated dividing the deviation of the measured pointsfrom the fit results over the fit values. A non linearity up to 40% is observed for increas-

26


FC: 100 fF

FC: 300 fF

FC: 500 fF

FC: 700 fF

FC: 1000 fF

FC: 1500 fF

Shaping time: 50 ns High Gain


Outp

ut A

SIC

[mV]

Equivalent mips

0

200

400

600

800

1000

1200

1400

0 10 20 30 40

0 5 10 15 20 25 30 35

FC: 100 fF

FC: 300 fF

FC: 500 fF

FC: 700 fF

FC: 1000 fF

FC: 1500 fF

Shaping time: 50 ns

High Gain


Resid

uals

to li

near

ity [%

]

Equivalent mips

-60

-40

-20

0

20

40

0 5 10 15 20 25 30 35 40 45

0 5 10 15 20 25 30 35

-5

0

5

0 5

Figure 32: The output signal from the ASIC is measured in high gain mode for 50 nsshaping time and for different input charge values. Upper panel: Resultsobtained using different feedback capacitance values are compared. BottomPanel: Residuals to linearity calculated as described in the text. A 20 dBattenuator at the input line was used during these measurements.

ing injected charge, bottom panel of Fig. 34. In this region of injected charge valuesthe non-linearity response (due to the track and hold switch) appears to be weakly de-pendent on the chosen shaping time. Note that a direct comparison with the resultspresented in the bottom panel of Fig. 31 cannot be done, being different both the regionconsidered in the linear fit and the smallest values of injected charge considered in these

27


Shaping time: 50 ns

Low Gain

Qinj: 30 pC

Feedback Capacitance [fF]

Gain

[mV/

pC]

0

2

4

6

8

10

12

14

16

18

20

0 200 400 600 800 1000 1200 1400 1600

Shaping time: 50 ns

High Gain

Qinj: 3 pC

Feedback Capacitance [fF]

Gain

[mV/

pC]

0

20

40

60

80

100

120

0 200 400 600 800 1000 1200 1400 1600

Figure 33: The gain of the ASIC is measured in both low and high gain modes for 50 nsshaping time and for 30 pC and 3 pC of injected charge, respectively.

measurements.

15 SiPM Single-Pixel Spectra

The possibility to operate the ASIC in auto-trigger mode during calibrations was shownto be feasible due to the low trigger jitter time walk, smaller than 1 and 7 ns, respectively(see Sec. 8). That possibility is confirmed by the following measurement of the single-pixel spectrum.A SiPM, flashed by an LED, was connected to the board, and the processed outputsignal was investigated. The device was operated at overvoltage larger (+1.7 V) than the

28


Shaping Time: 50 ns

Shaping Time: 75 ns

Shaping Time: 100 ns


Feedback Capacitance: 400 fF Low Gain


Outp

ut A

SIC

[mV]

Equivalent mips

0

50

100

150

200

250

300

0 5 10 15 20 25 30 35 40

0 5 10 15 20 25 30

Shaping Time: 50 ns

Shaping Time: 75 ns



Feedback Capacitance: 400 fF Low Gain


Resid

uals

to li

near

ity [%

]

Equivalent mips

-100

-80

-60

-40

-20

0

20

40

60

80

100

0 5 10 15 20 25 30 35 40

0 5 10 15 20 25 30

Figure 34: Upper panel: The output signal from the ASIC is measured in low gain modefor 400 fF feedback capacitance, and for different values of injected charge andof shaping time. Bottom Panel: Residuals to linearity calculated as describedin the text. A 20 dB attenuator (10−1X) at the input line was used duringthese measurements.

nominal value, to increase the cross-talk between the pixels (which is, on the other side,not desirable for physics mode operations). The SiPM signal was measured using theauto-trigger mode described in Sec.7. After properly setting a discriminator thresholdvalue, the generated trigger was used to trigger an external pulse generator (HP 8082A).One signal from the pulser was then used to open the gate of the external ADC module,

29


/ ndf 2χ 359.4 / 50Prob 0p0 41.2± 6699 p1 0.0± 12.6 p2 0.013± 2.676 p3 29.2± 3445 p4 0.02± 25.13 p5 0.027± 3.153 p6 18.2± 1497 p7 0.04± 38.03 p8 0.057± 3.545 p9 11.2± 668.5 p10 0.09± 51.16 p11 0.116± 3.733 p12 8.2± 312 p13 0.16± 64.54 p14 0.229± 4.529

Amplitude [mV]0 10 20 30 40 50 60 70 80 90 100

Yiel

d

0

1000

2000

3000

4000

5000

6000

7000 / ndf 2χ 359.4 / 50Prob 0p0 41.2± 6699 p1 0.0± 12.6 p2 0.013± 2.676 p3 29.2± 3445 p4 0.02± 25.13 p5 0.027± 3.153 p6 18.2± 1497 p7 0.04± 38.03 p8 0.057± 3.545 p9 11.2± 668.5 p10 0.09± 51.16 p11 0.116± 3.733 p12 8.2± 312 p13 0.16± 64.54 p14 0.229± 4.529

p.e.0 1 2 3 4 5

SiPM 711

: 12.8 mVp.e.

<gain>

DAC: 565

Voltage Bias: 64.7 V

Figure 35: Single-pixel spectrum for the thermal noise obtained by operating the SiPMin high gain (13 mV per pixel) and for the discriminator threshold level abovethe pedestal. Superimposed is the gaussian fit to the peak structure of thespectrum.

and a second signal was input to the SPIROC board to hold the analogue signal fromthe SiPM at its peaking amplitude.When the discriminator threshold is set above the pedestal the contribution of thethermal noise dominates the measured spectrum, Fig. 35, due to its large rate (typicallyaround MHz).In order to observe the contribution of LED light induced events in the spectrum, thediscriminator threshold was set to 480 DAC units, corresponding to a value approxi-mately above 3 pixels for a measured gain of 13 mV per pixel (operating the SiPM at64.7 V), Fig. 36. Also, the rate of the LED flashes was increased to 30 kHz from theinitial 1 kHz. Although the thermal noise contribution appears to be still sizable inthis experimental configuration (dominating the spectrum first peaks), the LED signalappears in the spectrum at large amplitude values, and is also presented in the zoomedpanel of the picture. The results show the single-pixel structure, and suggest that a fitof the spectrum (either the thermal noise or the signal contribution) might be possible,although its quality cannot be quantified at this stage of the analysis.The above results were obtained for a quite large gain of the SiPM. To see the effects ofa lower pixel gain value, the voltage bias applied to the device was decreased to 63.0 Vresulting in a gain around 8 mV per pixel, which corresponds to approximately half amillion electrons. The discriminator threshold value was kept unchanged, correspondingat about five pixels at this low pixel gain. The resulting spectrum is presented inFig. 37. Due to the lower device gain and to the high discriminator threshold value thecontribution from the thermal noise is here strongly suppressed, and the spectrum ismainly populated by LED driven events.To see the quality of the noise spectrum for this low SiPM gain, the threshold was setabove the pedestal, Fig. 38. At this low pixel gain value, the single-pixel structure ofthe thermal noise spectrum appears to be deteriorated, complicating the possibility toperform a fit of the pixel structure to calibrate the device. This complication might be

30


Amplitude [mV]0 50 100 150 200 250 300 350 400

Yiel

d

0

20

40

60

80

100

120

140

160

180310×

Amplitude [mV]160 180 200 220 240 260 280 300

Yiel

d

13000

13500

14000

14500

15000

15500

16000

16500

17000

SiPM 711 : 13.0 mVp.e.

<gain>

DAC: 480 Voltage Bias: 64.7 V

Figure 36: Single-pixel spectrum obtained by flashing the SiPM with LED light. Thedevice was operated in high pixel gain (13 mV per pixel) setting the SPIROCdiscriminator threshold level above the third pixel peak, and running theASIC in auto-trigger mode. The contribution from the thermal noise andthe LED events dominates the first peaks and the high tail of the spectrum,respectively. The peak structure of part of the spectrum for LED drivenevents is also presented in the zoomed panel for better visibility.

Amplitude [mV]0 20 40 60 80 100 120 140 160 180 200

Yiel

d

0

20

40

60

80

100

120

140

160

180310×

SiPM 711

: 8.0 mVp.e.

<gain>

DAC: 480


Figure 37: Single-pixel spectrum obtained by flashing the SiPM with LED light. Thedevice was operated in low pixel gain (8 mV per pixel) setting the SPIROCdiscriminator threshold level above the fifth pixel peak, and running the ASICin auto-trigger mode. Due to the lower device gain and to the high discrimi-nator threshold value the contribution from the thermal noise is here stronglysuppressed, and the spectrum is mainly populated by LED driven events.

overcome by operating the SiPM with a larger gain, as shown in Fig. 35 .As a comparison, the measurement was repeated using an external trigger to hold thepeaking amplitude and to open the gate of the ADC module, operating the SiPM atlow pixel gain and setting the discriminator threshold value above the pedestal. The

31


Amplitude [mV]0 20 40 60 80 100 120 140 160 180

Yiel

d

0

100

200

300

400

500

600

310×

Amplitude [mV]50 60 70 80 90 100 110 120

Yiel

d

25000

30000

35000

40000

45000

50000

55000

SiPM 711 : 8.0 mVp.e.

<gain>

DAC: 560 Voltage Bias: 63.0 V

Figure 38: Single-pixel spectrum obtained by flashing the SiPM with LED light. Thedevice was operated in low pixel gain (8 mV per pixel) setting the SPIROCdiscriminator threshold level above the pedestal, and running the ASIC inauto-trigger mode. The contribution from the thermal noise and the LEDevents dominates the first peaks and the high tail of the spectrum, respec-tively. The peak structure of part of the spectrum for LED driven events isalso presented in the zoomed panel for better visibility.

Amplitude [mV]0 20 40 60 80 100 120 140

Yiel

d

0

10000

20000

30000

40000

50000

60000

SiPM 711

: 8.0 mVp.e.

<gain>

DAC: 575


External Trigger

Figure 39: Typical SiPM single-pixel spectra obtained by flashing the SiPM with LEDlight. The device was operated in low pixel gain (8 mV per pixel) setting theSPIROC discriminator threshold level above the pedestal. Here, the signal isheld at its peaking amplitude by an external trigger given by the main pulsegenerator.

LED intensity was decreased to have a lower number of pixels firing, similarly to what isusually done calibrating a SiPM with an LED system. The single-pixel spectrum, nowwithout any contribution from the thermal noise, is presented in Fig. 39. The peaksappear to be well separated, allowing the calibration of the device using an external

32


light source system. Potentially, the calibration of the photodetector might be alsoperformed running the SPIROC in auto-trigger mode by analysing the thermal noise.In this case, during the calibration the SiPM should be operated at larger pixel gains,as shown above.

16 Towards Real Data Taking Conditions

When the measurements presented in this note have been performed, the software tooperate the chip in auto-trigger mode (see Sec. 7) was not fully implemented. Thislimitation could be somehow bypassed using the following procedure, thus testing thecapability and the efficiency of the chip to perform measurements in both physics andauto-trigger mode at different trigger threshold values, Fig. 40.These measurements were performed using the signal from a SiPM (SiPM number 758),thus simulating, as much as possible, real data taking conditions. Spectra suitable forfitting the single-pixel structure of the signal were obtained operating the high voltagesupply at 64.6 V, corresponding to 59.4 V voltage bias measured at the dynodes of SiPMby setting the input HV DAC tuning to zero units (see Sec. 9). Note that the nominaloperation voltage for this SiPM is 59.3 V, as declared in the SiPM database. Themain pulse generator triggered the generation of a negative voltage pulse (via a HewlettPackard 8130A pulse generator providing width, leading and trailing edges tunable downto the nanosecond level) to an LED, optically coupled to a SiPM whose signal was thendirectly input to the ASIC board, using the same high voltage line, Fig. 21. The intensityof the LED, and in turns of the SiPM signal, could be then regulated by the chainedpulser.

ADC module

CAEN V785N

bufferamplifier1x or 9x

VME CAEN 8002

hold

ASICSiPM

+HV

pulse generator

STS DG 535

pulse generatortrigger

HP 8130A

generatorgate

STS DG 535

pulse generator

Figure 40: Test bench setup used at DESY for the investigation of the efficiency of theSPIROC 1B chip to perform measurements in physics and auto-trigger modeat different trigger threshold values.

33


During test-bench measurements the signal to open the ADC module gate is typicallyprovided by the pulse generator, for every generated voltage pulse. Accessing the triggerallows instead to generate the open-gate signal only in case a processed signal (eitherfrom the thermal noise or from the LED) overshoots a chosen threshold value in thediscriminator. The generated trigger was therefore used as an external trigger to anadditional pulse generator, which in turns generated the signal to open the ADC modulegate at a suitable time. The hold signal was provided by the main pulser used to switchthe LED on.As a first step, the chip was operated in high gain mode in parallel with low intensityLED light, while applying different threshold DAC values via the LabView interface (thelarger is the DAC value set, the smaller is the applied threshold level value). Using thetrigger only to open the ADC gate, but holding the signal peaking amplitude via theexternal primary pulse generator allowed to easily fit the single-pixel structure of thespectrum corresponding to LED events, for the purpose of this measurement, Fig. 41- 42.In case a signal induced by thermal noise overshoots the discriminator threshold level

then the ADC gate is still opened by the generated trigger but the processed signal is notany more synchronised with the hold signal generated by the main pulser. This results indeteriorating the single-pixel structure of the thermal noise contribution, and populatingthe spectrum towards the pedestal region (the recorded signal amplitude is lower thanthe real peaking amplitude). This contribution from thermal noise to the spectrum isincreasingly suppressed with increasing the threshold value, as clearly visible in Fig. 41.Although the number of suppressed peaks in the spectrum increases by increasing thethreshold level, the measurements show that a remaining small contribution from thepeaks expected to be suppressed is still present. This feature, possibly due to theexperimental setup, has not been furtherly investigated at this stage of the analysis,being not relevant for the measurement presented here.From the above measurements the threshold values to cut specific spectrum peaks can bedetermined resulting in approximative 20 DAC units per peak, Tab. 1. This correspondsto a step of ≈ 37 mV in the fast shaping line (see Fig. 14).As a cross check, a similar spectrum was taken using the pulse generator to open theADC gate, obtaining the same single-pixel peak locations, Fig. 43. With the same setup,a mip signal was tentatively obtained tuning the LED amplitude such that the SiPMspectrum shows a maximum around the 15 pixel peak amplitude, Fig. 44. Keeping thesame LED amplitude, the mip-like signal was then measured using the low gain modeof the chip, Fig. 45, for a shaping time of 50 ns.Using again the generated trigger to open the ADC gate, and applying different thresh-old DAC values, the trigger efficiency with respect to the signal discrimination levelwas investigated for two values of the feedback capacitance, Fig. 46. In the plots, thethreshold DAC values are presented in terms of number of photo-electron peaks whichare cut by the selected threshold, according to Tab. 1. By increasing the DAC value (de-creasing the trigger threshold) the number of triggers generated by the noise increases,resulting in a larger contribution of pedestal events to the overall accumulated events inthe spectra. Already at half a mip threshold the fractional contribution of SiPM signalevents is almost 100%, for both the investigated ASIC configurations.

34


/ ndf 2χ 396 / 402Prob 0.5756p0 3.4± 306.1 p1 0.12± 20.55 p2 0.323± 4.078 p3 22.4± 254.2 p4 0.18± 29.15 p5 0.187± -2.443 p6 19.2± 291.3 p7 0.25± 36.18 p8 0.439± -3.118 p9 15.5± 253.7 p10 0.32± 44.34 p11 0.598± 3.423 p12 41.4± 113.3 p13 0.45± 51.68 p14 0.456± 2.558 p15 3.4± 190.2 p16 0.74± 59.38 p17 1.078± 6.613

Amplitude [mV]20 30 40 50 60 70 80 90 100 110

Yie

ld

0

100

200

300

400

500

600 / ndf 2χ 396 / 402

Prob 0.5756p0 3.4± 306.1 p1 0.12± 20.55 p2 0.323± 4.078 p3 22.4± 254.2 p4 0.18± 29.15 p5 0.187± -2.443 p6 19.2± 291.3 p7 0.25± 36.18 p8 0.439± -3.118 p9 15.5± 253.7 p10 0.32± 44.34 p11 0.598± 3.423 p12 41.4± 113.3 p13 0.45± 51.68 p14 0.456± 2.558 p15 3.4± 190.2 p16 0.74± 59.38 p17 1.078± 6.613

p.e.2 3 4 5 6 7 8

SiPM 758

: 7.4 mVp.e.

<gain>

DAC: 570


/ ndf 2χ 424.5 / 402Prob 0.2112p0 3.6± 346.1 p1 0.09± 21.52 p2 0.198± 3.875 p3 16.0± 368.3 p4 0.11± 29.76 p5 0.118± -2.397 p6 20.7± 397.4 p7 0.16± 36.63 p8 0.243± -2.866 p9 34.0± 356.6 p10 0.28± 44.56 p11 0.385± 3.553 p12 40.7± 135.6 p13 0.28± 52.37 p14 0.318± -2.424 p15 3.9± 262 p16 0.82± 59.53 p17 1.420± 7.497

Amplitude [mV]20 30 40 50 60 70 80 90 100 110

Yie

ld

0

100

200

300

400

500

600 / ndf 2χ 424.5 / 402

Prob 0.2112p0 3.6± 346.1 p1 0.09± 21.52 p2 0.198± 3.875 p3 16.0± 368.3 p4 0.11± 29.76 p5 0.118± -2.397 p6 20.7± 397.4 p7 0.16± 36.63 p8 0.243± -2.866 p9 34.0± 356.6 p10 0.28± 44.56 p11 0.385± 3.553 p12 40.7± 135.6 p13 0.28± 52.37 p14 0.318± -2.424 p15 3.9± 262 p16 0.82± 59.53 p17 1.420± 7.497

p.e.2 3 4 5 6 7 8

SiPM 758

: 7.4 mVp.e.

<gain>

DAC: 560


/ ndf 2χ 418.6 / 402Prob 0.2736p0 3.4± 326.9 p1 0.09± 21.17 p2 0.188± 3.871 p3 8.2± 453.5 p4 0.06± 29.72 p5 0.08± -2.43 p6 8.2± 518.9 p7 0.08± 36.67 p8 0.080± -2.707 p9 35.4± 449.8 p10 0.11± 44.31 p11 0.127± 3.309 p12 29.5± 177 p13 0.14± 51.89 p14 0.170± 2.498 p15 3.0± 334.1 p16 0.59± 59.11 p17 1.04± -8.06

Amplitude [mV]20 30 40 50 60 70 80 90 100 110

Yie

ld

0

100

200

300

400

500

600 / ndf 2χ 418.6 / 402

Prob 0.2736p0 3.4± 326.9 p1 0.09± 21.17 p2 0.188± 3.871 p3 8.2± 453.5 p4 0.06± 29.72 p5 0.08± -2.43 p6 8.2± 518.9 p7 0.08± 36.67 p8 0.080± -2.707 p9 35.4± 449.8 p10 0.11± 44.31 p11 0.127± 3.309 p12 29.5± 177 p13 0.14± 51.89 p14 0.170± 2.498 p15 3.0± 334.1 p16 0.59± 59.11 p17 1.04± -8.06

p.e.2 3 4 5 6 7 8

SiPM 758

: 7.4 mVp.e.

<gain>

DAC: 550


/ ndf 2χ 394.6 / 402Prob 0.5942p0 3.2± 275.7 p1 0.11± 20.83 p2 0.295± 4.261 p3 13.5± 534.8 p4 0.1± 30 p5 0.088± 2.427 p6 20.0± 782.8 p7 0.11± 37.09 p8 0.138± 2.708 p9 16.7± 788.3 p10 0.10± 44.56 p11 0.237± 3.064 p12 69.9± 434.8 p13 0.24± 51.58 p14 0.245± -2.725 p15 5.9± 567.3 p16 0.38± 59.73 p17 0.573± 6.151

Amplitude [mV]20 30 40 50 60 70 80 90 100 110

Yie

ld

0

200

400

600

800

1000 / ndf 2χ 394.6 / 402

Prob 0.5942p0 3.2± 275.7 p1 0.11± 20.83 p2 0.295± 4.261 p3 13.5± 534.8 p4 0.1± 30 p5 0.088± 2.427 p6 20.0± 782.8 p7 0.11± 37.09 p8 0.138± 2.708 p9 16.7± 788.3 p10 0.10± 44.56 p11 0.237± 3.064 p12 69.9± 434.8 p13 0.24± 51.58 p14 0.245± -2.725 p15 5.9± 567.3 p16 0.38± 59.73 p17 0.573± 6.151

p.e.2 3 4 5 6 7 8

SiPM 758

: 7.4 mVp.e.

<gain>

DAC: 540


/ ndf 2χ 425.4 / 412Prob 0.3143p0 1.61± 88.64 p1 0.20± 20.26 p2 0.428± 5.235 p3 4.5± 157.7 p4 0.09± 30.42 p5 0.098± 2.304 p6 5.2± 301.5 p7 0.09± 37.61 p8 0.116± 2.658 p9 11.1± 332.1 p10 0.13± 44.91 p11 0.181± 2.836 p12 5.0± 236.8 p13 0.45± 61.06 p14 0.490± 5.373 p15 28.9± 236 p16 0.17± 52.17 p17 0.324± 3.225

Amplitude [mV]20 30 40 50 60 70 80 90 100 110

Yie

ld

0

100

200

300

400

500

600 / ndf 2χ 425.4 / 412

Prob 0.3143p0 1.61± 88.64 p1 0.20± 20.26 p2 0.428± 5.235 p3 4.5± 157.7 p4 0.09± 30.42 p5 0.098± 2.304 p6 5.2± 301.5 p7 0.09± 37.61 p8 0.116± 2.658 p9 11.1± 332.1 p10 0.13± 44.91 p11 0.181± 2.836 p12 5.0± 236.8 p13 0.45± 61.06 p14 0.490± 5.373 p15 28.9± 236 p16 0.17± 52.17 p17 0.324± 3.225

p.e.2 3 4 5 6 7 8

SiPM 758

: 7.5 mVp.e.

<gain>

DAC: 530


/ ndf 2χ 420.8 / 392Prob 0.1519p0 1.69± 84.12 p1 0.17± 20.49 p2 0.419± 3.551 p3 3.0± 101.6 p4 0.21± 30.46 p5 0.337± 3.065 p6 8.8± 305.6 p7 0.13± 38.28 p8 0.156± 2.613 p9 14.6± 434.4 p10 0.15± 45.59 p11 0.219± 2.787 p12 48.2± 371.5 p13 0.19± 52.58 p14 0.315± -2.841 p15 5.3± 373 p16 0.32± 60.91 p17 0.663± 4.378

Amplitude [mV]20 30 40 50 60 70 80 90 100 110

Yie

ld

0

100

200

300

400

500

600 / ndf 2χ 420.8 / 392

Prob 0.1519p0 1.69± 84.12 p1 0.17± 20.49 p2 0.419± 3.551 p3 3.0± 101.6 p4 0.21± 30.46 p5 0.337± 3.065 p6 8.8± 305.6 p7 0.13± 38.28 p8 0.156± 2.613 p9 14.6± 434.4 p10 0.15± 45.59 p11 0.219± 2.787 p12 48.2± 371.5 p13 0.19± 52.58 p14 0.315± -2.841 p15 5.3± 373 p16 0.32± 60.91 p17 0.663± 4.378

p.e.2 3 4 5 6 7 8

SiPM 758

: 7.5 mVp.e.

<gain>

DAC: 520


Figure 41: The spectrum from SiPM nr.758 is measured in high gain mode applyingdifferent threshold DAC values at the signal discriminator located along thefast shaping line. The chip is operated in high gain mode at 25 ns shapingtime and 100 fF feedback capacitance.

The preliminary results presented here verify the possibility to operate the ASIC in auto-trigger mode (after the mentioned improvement of the track and hold switch) processingthe physics events at half a mip cut on the trigger threshold, as forseen in the ILCapplications.

35


/ ndf 2χ 386.4 / 392Prob 0.5706p0 1.58± 79.15 p1 0.28± 20.25 p2 0.630± 4.267 p3 4.56± 73.28 p4 0.25± 30.24 p5 0.338± 2.917 p6 5.6± 302.6 p7 0.15± 38.95 p8 0.179± 2.907 p9 18.7± 499.5 p10 0.11± 45.83 p11 0.142± 2.433 p12 66.9± 459.4 p13 0.14± 52.38 p14 0.275± -2.814 p15 5.1± 503.5 p16 0.3± 60.9 p17 0.782± 4.994

Amplitude [mV]20 30 40 50 60 70 80 90 100 110

Yie

ld

0

100

200

300

400

500

600

/ ndf 2χ 386.4 / 392Prob 0.5706p0 1.58± 79.15 p1 0.28± 20.25 p2 0.630± 4.267 p3 4.56± 73.28 p4 0.25± 30.24 p5 0.338± 2.917 p6 5.6± 302.6 p7 0.15± 38.95 p8 0.179± 2.907 p9 18.7± 499.5 p10 0.11± 45.83 p11 0.142± 2.433 p12 66.9± 459.4 p13 0.14± 52.38 p14 0.275± -2.814 p15 5.1± 503.5 p16 0.3± 60.9 p17 0.782± 4.994

p.e.2 3 4 5 6 7 8

SiPM 758

: 7.5 mVp.e.

<gain>

DAC: 510


/ ndf 2χ 426.8 / 396Prob 0.1379p0 1.67± 75.36 p1 0.16± 20.41 p2 0.313± 3.047 p3 1.58± 67.76 p4 0.19± 29.54 p5 0.350± 3.204 p6 4.2± 215.7 p7 0.18± 39.44 p8 0.190± 3.015 p9 21.0± 494.3 p10 0.10± 46.15 p11 0.108± 2.292 p12 36.0± 627.1 p13 0.15± 52.94 p14 0.216± 3.005 p15 7.8± 659.5 p16 0.19± 61.42 p17 0.369± 4.012

Amplitude [mV]20 30 40 50 60 70 80 90 100 110

Yie

ld

0

100

200

300

400

500

600

700

/ ndf 2χ 426.8 / 396Prob 0.1379p0 1.67± 75.36 p1 0.16± 20.41 p2 0.313± 3.047 p3 1.58± 67.76 p4 0.19± 29.54 p5 0.350± 3.204 p6 4.2± 215.7 p7 0.18± 39.44 p8 0.190± 3.015 p9 21.0± 494.3 p10 0.10± 46.15 p11 0.108± 2.292 p12 36.0± 627.1 p13 0.15± 52.94 p14 0.216± 3.005 p15 7.8± 659.5 p16 0.19± 61.42 p17 0.369± 4.012

p.e.2 3 4 5 6 7 8

SiPM 758

: 7.6 mVp.e.

<gain>

DAC: 500


/ ndf 2χ 266.5 / 249Prob 0.2135p0 7.5± 460.1 p1 0.14± 47.08 p2 0.105± -3.043 p3 40.1± 719.8 p4 0.12± 53.75 p5 0.121± -2.411 p6 109.8± 717.4 p7 0.2± 60.2 p8 0.313± 3.073 p9 12.9± 773.7 p10 0.38± 68.83 p11 0.796± 4.916

Amplitude [mV]30 40 50 60 70 80 90 100 110

Yie

ld

0

100

200

300

400

500

600

700

800

900

/ ndf 2χ 266.5 / 249Prob 0.2135p0 7.5± 460.1 p1 0.14± 47.08 p2 0.105± -3.043 p3 40.1± 719.8 p4 0.12± 53.75 p5 0.121± -2.411 p6 109.8± 717.4 p7 0.2± 60.2 p8 0.313± 3.073 p9 12.9± 773.7 p10 0.38± 68.83 p11 0.796± 4.916

p.e.4 5 6 7 8

SiPM 758

: 7.7 mVp.e.

<gain>

DAC: 490


/ ndf 2χ 224.2 / 249Prob 0.8686p0 9.4± 320.3 p1 0.21± 47.43 p2 0.148± 2.806 p3 17.5± 797 p4 0.09± 54.28 p5 0.13± -2.57 p6 82.9± 711.2 p7 0.12± 60.57 p8 0.180± -2.559 p9 6.3± 1078 p10 0.19± 68.74 p11 0.43± -5.57

Amplitude [mV]40 50 60 70 80 90 100 110

Yie

ld

0

200

400

600

800

1000

1200

/ ndf 2χ 224.2 / 249Prob 0.8686p0 9.4± 320.3 p1 0.21± 47.43 p2 0.148± 2.806 p3 17.5± 797 p4 0.09± 54.28 p5 0.13± -2.57 p6 82.9± 711.2 p7 0.12± 60.57 p8 0.180± -2.559 p9 6.3± 1078 p10 0.19± 68.74 p11 0.43± -5.57

p.e.5 6 7 8 9

SiPM 758

: 7.7 mVp.e.

<gain>

DAC: 480


/ ndf 2χ 222.8 / 234Prob 0.6896p0 24.1± 244.9 p1 0.35± 62.06 p2 0.291± 2.571 p3 56.1± 410.9 p4 0.18± 69.11 p5 0.439± 3.057 p6 7.7± 461.6 p7 0.89± 83.44 p8 1.838± 6.836 p9 124.8± 249.1 p10 0.43± 75.77 p11 0.528± 2.649

Amplitude [mV]60 70 80 90 100 110

Yie

ld

0

100

200

300

400

500

600

/ ndf 2χ 222.8 / 234Prob 0.6896p0 24.1± 244.9 p1 0.35± 62.06 p2 0.291± 2.571 p3 56.1± 410.9 p4 0.18± 69.11 p5 0.439± 3.057 p6 7.7± 461.6 p7 0.89± 83.44 p8 1.838± 6.836 p9 124.8± 249.1 p10 0.43± 75.77 p11 0.528± 2.649

p.e.7.5 8 8.5 9 9.5 10 10.5 11 11.5

SiPM 758

: 7.6 mVp.e.

<gain>

DAC: 450


/ ndf 2χ 219.9 / 181Prob 0.02573p0 12.2± 203 p1 0.23± 70.43 p2 0.214± 3.142 p3 37.6± 189.3 p4 0.17± 76.64 p5 0.218± -2.232 p6 4.0± 438.7 p7 0.17± 84.53 p8 0.6± 5.7

Amplitude [mV]65 70 75 80 85 90 95 100 105 110

Yie

ld

0

100

200

300

400

500

600

/ ndf 2χ 219.9 / 181Prob 0.02573p0 12.2± 203 p1 0.23± 70.43 p2 0.214± 3.142 p3 37.6± 189.3 p4 0.17± 76.64 p5 0.218± -2.232 p6 4.0± 438.7 p7 0.17± 84.53 p8 0.6± 5.7

p.e.8.5 9 9.5 10 10.5 11

SiPM 758

: 7.7 mVp.e.

<gain>

DAC: 430


Figure 42: The spectrum from SiPM nr.758 is measured in high gain mode applyingdifferent threshold DAC values at the signal discriminator located along thefast shaping line. The chip is operated in high gain mode at 25 ns shapingtime and 100 fF feedback capacitance.

17 Conclusions

During 2008 and 2009 systematic studies have been performed to characterise the ana-logue component of the SPIROC ASIC, designed for the readout of the analogue hadroniccalorimeter for the international linear collider project. The more significant results arepresented and described in this report showing the fulfilled requirements and the features

36


DAC value Suppressed peak number

530 3510 4490 5470 6450 7430 8410 9390 10

Table 1: DAC values applied at the signal discriminator to suppress specific peaks in theSiPM spectrum. The obtained DAC values refer to the chip operated in highgain mode at 25 ns shaping time and 100 fF feedback capacitance. One DACunits corresponds to ≈ 1.9 mV in the fast shaping line.

/ ndf 2χ 532.3 / 516

Prob 0.3006

Amplitude [mV]0 20 40 60 80 100

Yie

ld

0

100

200

300

400

500

600 / ndf 2χ 532.3 / 516

Prob 0.3006

p.e.0 2 4 6 8 10

SiPM 758

: 7.7 mVp.e.

<gain>

DAC: 400


Peak 0: -0.89 +- 0.070Peak 1: 6.46 +- 0.051Peak 2: 14.19 +- 0.054Peak 3: 21.80 +- 0.058Peak 4: 29.36 +- 0.082Peak 5: 37.15 +- 0.088Peak 6: 44.36 +- 0.154Peak 7: 53.01 +- 0.232








Figure 43: The SiPM single pixel spectrum obtained operating the chip in high gainmode at 25 ns shaping time and 100 fF feedback capacitance, and using themain external pulse generator to open the ADC gate.

which should be fixed in the next version of the chip. These measurements have beendone on the SPIROC version SPIROC 1B, which has the analogue processing of signalsalmost fully implemented.The ASIC was shown to handle the dynamic range covered by the SiPMs which areexpected to be readout in both calibration mode for the maximum amplification at 100fF feedback capacitance, and physics mode for values of feedback capacitance above 400fF, resulting non-saturated up to ≈ 80 and ≈ 8 mips, respectively. The values reportedhere refer to a SiPM with pixel gain of order 0.5 · 106. In case of SiPMs with highly

37


Amplitude [mV]20 40 60 80 100 120 140 160 180 200 220

Yie

ld

0

50

100

150

200

250

300

350

400

450

500

p.e.5 10 15 20 25

SiPM 758


Figure 44: A mip-like signal measured operating the chip in high gain mode at 25 nsshaping time and 100 fF feedback capacitance.

Amplitude [ADC]

1100 1120 1140 1160 1180 1200

Yield

0

20

40

60

80

100310×

SiPM 758


mip-like signal

Amplitude [ADC]

1100 1120 1140 1160 1180 1200

Yiel

d

0

50

100

150

200

250

300

350

400310×

pedestal

Figure 45: A mip-like signal (left panel) and the pedestal (right panel) are measuredoperating the chip in low gain mode at 50 ns shaping time and 200 fF feedbackcapacitance.

varying pixel gain (as for the SiPMs used in the past AHCAL test beam operations),the dynamic range covered by the photodetector changes, and the operation mode ofthe chip should be changed accordingly, resulting in a change of the signal over noiseratio.The data acquisition is forseen to run in auto-trigger mode, being activated by the SiPMsignals, and the chip appears to fulfil this requirement in the physics mode, reaching100% trigger efficiency for trigger threshold values above half a mip. For these valuesthe trigger time walk and jitter were found to be less than 3 and 1 ns, respectively. Quite

38


Amplitude [ADC]1130 1140 1150 1160 1170 1180 1190 1200

Yie

ld

0

50

100

150

200

250

300

350

400310×

SiPM 758

50 ns shaping time

200 fF feedb. capacitance

Fraction of mip events2.0 p.e.: 0.159

3.5 p.e.: 0.4445.0 p.e.: 0.832

7.5 p.e.: 0.98611.0 p.e.: 0.999

12.0 p.e.: 1.000

2.0 p.e.: 0.159

3.5 p.e.: 0.4445.0 p.e.: 0.832

7.5 p.e.: 0.98611.0 p.e.: 0.999

12.0 p.e.: 1.000

2.0 p.e.: 0.159

3.5 p.e.: 0.4445.0 p.e.: 0.832

7.5 p.e.: 0.98611.0 p.e.: 0.999

12.0 p.e.: 1.000

2.0 p.e.: 0.159

3.5 p.e.: 0.4445.0 p.e.: 0.832

7.5 p.e.: 0.98611.0 p.e.: 0.999

12.0 p.e.: 1.000

2.0 p.e.: 0.159

3.5 p.e.: 0.4445.0 p.e.: 0.832

7.5 p.e.: 0.98611.0 p.e.: 0.999

12.0 p.e.: 1.000

2.0 p.e.: 0.159

3.5 p.e.: 0.4445.0 p.e.: 0.832

7.5 p.e.: 0.98611.0 p.e.: 0.999

12.0 p.e.: 1.000

Amplitude [ADC]1130 1140 1150 1160 1170 1180 1190 1200

Yie

ld

0

50

100

150

200

250

300

350

400310×

SiPM 758

50 ns shaping time

400 fF feedb. capacitance

Fraction of mip events2.0 p.e.: 0.158

3.5 p.e.: 0.4445.0 p.e.: 0.832

7.5 p.e.: 0.98510.0 p.e.: 0.998

12.0 p.e.: 0.999

2.0 p.e.: 0.158

3.5 p.e.: 0.4445.0 p.e.: 0.832

7.5 p.e.: 0.98510.0 p.e.: 0.998

12.0 p.e.: 0.999

2.0 p.e.: 0.158

3.5 p.e.: 0.4445.0 p.e.: 0.832

7.5 p.e.: 0.98510.0 p.e.: 0.998

12.0 p.e.: 0.999

2.0 p.e.: 0.158

3.5 p.e.: 0.4445.0 p.e.: 0.832

7.5 p.e.: 0.98510.0 p.e.: 0.998

12.0 p.e.: 0.999

2.0 p.e.: 0.158

3.5 p.e.: 0.4445.0 p.e.: 0.832

7.5 p.e.: 0.98510.0 p.e.: 0.998

12.0 p.e.: 0.999

2.0 p.e.: 0.158

3.5 p.e.: 0.4445.0 p.e.: 0.832

7.5 p.e.: 0.98510.0 p.e.: 0.998

12.0 p.e.: 0.999

Figure 46: The efficiency in detecting a mip-like signal is measured at different thresholdvalues (in SiPM photo-electron units) operating the chip in low gain modeat 50 ns shaping time, 200 fF and 400 fF feedback capacitance, left and rightpanel, respectively.

remarkable, is the observed possibility to fit the thermal noise, opening the potentialityof self-calibrating the device.The electronic noise was investigated and found to be typically within one millivolt,depending on the specific shaping time and amplification setting. The most sizableadditional contribution to the noise is induced by switching on the track and hold com-ponent, approximately doubling the noise. When coupled to an external signal sourcethe noise dependence on varying the coupling capacitance (as for real SiPMs) was foundto be within 20% in the range 10-100 pF.Comparing the 36 input channels, the pedestals showed a spread of 2 mV, and theirdeviation due to cross-talk was measured to be within ±0.5 mV in the investigatedrange from one to 33 mips (40 pC).Each input SiPM high voltage can be individually tuned via a DAC HV adjustmentdedicated to each detector line. The DAC to volt calibration was performed for allchannels showing a channel to channel average variation of 100 mV, and an averagemaximum deviation to linearity of 80 mV (for some channels up to 200 mV). Theobserved deviation from linearity appears to be systematically reproducible, and couldbe corrected for via a proper calibration.The high-low gain path coupling was studied and a sizable dependence (up to 10%) onthe high gain amplification setting was measured for the physics mode readout.Probably the most surprising feature of the chip was the observed increase of the signalpeaking time with increasing injected charge, related to properties of the used track andhold switch. Investigation with simulations by the chip designers in Orsay is on-going,and a possible cure of the shown feature should be available in the next generations ofthe ASIC.

39


The investigation of the digital component of the ASIC, implemented in the versionSPIROC 2, is on going and will be presented in a separate future note.

Acknowledgments

We are deeply grateful to S. Callier, C. De La Taille, and L. Raux of theOMEGA group at Orsay, and to F. Sefkow and E. Garutti at DESY foruseful discussions and suggestions.

References

[1] J. Brau et al., International Linear Collider Reference Design Report,ILC-REPORT-2007-001 (2007).

[2] M. Bouchel et al., Proc. of the IEEE 2008 Nuclear Science Symposium, Dresden,Germany, October 2008.

[3] M. Groll, Construction and Commissioning of a Hadronic Test-Beam Calorime-ter to Validate the Particle-Flow Concept at the ILC, PhD Thesis 2007, DESY-THESIS-2007-018.

[4] N. Feege, Silicon Photomultipliers: Properties and Application in a Highly GranularCalorimeter, Diploma Thesis 2008, DESY-THESIS-2008-050.

[5] W. R. Leo, Techniques for Nuclear and Particle Physics Experiments, Springer-Verlag.

[6] E. Kowalski, Nuclear Electronics, Springer Verlag.

[7] L. Raux, private communications.

[8] L. Raux, SPIROC ASIC Measurement, Presentation given at CALICE ELEC-TRONICS meeting, March 11, 2008.

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Documents

Overview of Studies on the SPIROC Chip Characterisation · A schematic view of a single channel of the ASIC chip is given in Fig. 1. 3 Test-Bench Description The characterisation