Optimization of Phase-Locked Loop Circuits via Geometric Programming

D. Colleran, C. Portmann, A. Hassibi, C. Crusius, S. S. Mohan, S. Boyd,

T. H. Lee, and M. Hershenson

Outline• Motivation

• Geometric programming (GP)

• GP compatible transistor models

• Clock generation PLL topology

• PLL design in GP form

• Silicon results

Simulation-based methodsW1 = 1W2 = 2

: :L8 = 1

Power = 1Gain = 500

� General purpose � Long design cycles� Needs circuit expert� Needs optim. expert

Geometric programming-based method

Numerical GPOptimization

Solver

Gain > 100BW > 10MHz

0.13µµµµm CMOS

M1.gm=f1(W,L,…)

: : :

M1.Cgs= fn(W,L,…)

Vdd

RLRL

M1 M2

Ib

Gain = f1(R,M1,Ib)

: : :

BW = fn(R,M1,Ib)

Outline• Motivation

• Geometric programming (GP)

• GP compatible transistor models

• Clock generation PLL topology

• PLL design in GP form

• Silicon results

Geometric programming

ααα nnxxcxxg ⋅⋅⋅= 21

21)( )0( >c

• A monomial function g(x) has the form

• A posynomial function f(x) is a sum of monomials

For example, 53

21

7.01 5.2)(

2xxxxxf += −

• Geometric program (GP) is

0 ,,1 1 ,,1 1)(

)( 0

≥≥≥≥============≤≤≤≤

xp...i(x)gm...ixf

xf

i

i tosubject minimize

GPs can be easily transformed into convex problem

Solving GP’sNew interior point methods for GP

• are extremely fast

• find globally optimal solution or provide proof of infeasibility

• are independent of starting point

For PLL synthesis: 40k optimization variables and 150k constraints takes ~90 minutes on 2GHz PC

Outline• Motivation

• Geometric programming (GP)

• GP compatible transistor models

• Clock generation PLL topology

• PLL design in GP form

• Silicon results

D

S

G ID

• Complex GP models can be developed including short-channel effects, finite output impedance, etc…, e.g.,

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GP electrical models

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GP models – Id vs. Vds, 0.18µµµµm

0.0

0.5

1.0

1.5

0.0 0.2 0.4 0.6 0.8 1.0 1.2

Vds (V)

Id (m

A)

Placement and Routing• Symmetry Constraints• Mirroring Nets• Net Matching• Alignment• Capacitance

Constraints• Shielding• EM/IR drop

considerations• Dummy poly for

matching and STI

GP physical models

Posynomial expressions for

Width and height, e.g.,

AD, AS, PD & PS, e.g.,

Outline• Motivation

• Geometric programming (GP)

• GP compatible transistor models

• Clock generation PLL topology

• PLL design in GP form

• Silicon results

PLL topology

�Charge pump PLL with low–power programmable dividers (12 bit, >2GHz)

�Variables include device dimensions (W,L) and # of ring oscillator stages (S)

Charge pump topology

Example current mirror equalities

(monomial):

VCO topology

Example saturationmargin inequalities

(posynomial):

Outline• Motivation

• Geometric programming (GP)

• GP compatible transistor models

• Clock generation PLL topology

• PLL design in GP form

• Silicon results

Second-order PLL system-level equations, in monomial form

Power consumption (posynomial)

Accumulated jitter, Taj (posynomial)σσσσj

t0.5

κκκκ

Using Hajimiri’s phase noise model (JSSC 1998):

From McNeil (JSSC 1997):

Static phase error, Terr (posynomial)

Using Pelgrom’s mismatch model (JSSC 1989 ):D

S

G ID

Outline• Motivation

• Geometric programming (GP)

• GP compatible transistor models

• Clock generation PLL topology

• PLL design in GP form

• Silicon results

GP vs. Silicon – 0.18um PLL arrays

5.9

3.1

2.7

4.2

2.1

2.2

Tpj[ps]

81-135

250

400

1500

600-1600

1200-1900

Fvco[MHz]

9.69.73.03.016255

24.227.92.52.7483-66

12.014.32.83.228204

14.415.36.07.954103

8.07.57.38.862332

6.25.710.811.093501MeasGPMeasGP

Taj [ps]Power [mW]ΦΦΦΦe [ps]

Fref[MHz]

#

�Good agreement between GP and silicon meas.

GP vs. Silicon – 0.13um PLL arrays

12.7

4.6

4.1

4.3

3.2

5.4

Tpj[ps]

512

900-1050

192-384

1000-1400

500-1000

800-1600

Fvco[MHz]

6.74.76.110.13090-1055

43.544.98.5313.3220.56

6.96.711.111.743244

5.45.812.617.853203

13.113.9--13.24725-502

7.78.9--18.34050-1551MeasGPMeasGP

Taj [ps]Power [mW]ΦΦΦΦe [ps]

Fref[MHz]

#

�Good agreement between GP and silicon meas.

Acc. jitter vs. ∆∆∆∆Fvco trade-off analysis

020406080

100120140160

0 200 400 600 800 1000 1200 1400 1600

VCO frequency range (MHz)

Acc

. jitt

er (p

s)

Power vs. ∆∆∆∆Fvco trade-off analysis

0

5

10

15

20

25

30

35

0 200 400 600 800 1000 1200 1400 1600

VCO frequency range (MHz)

Po

wer

(mW

)

Automated design does not translate into performance degradation

0.0473.865.512449.730.0797.91251000-1400204

5

21

PLL#

8.1

16.040.1

Tpj,noise[ps]-[%Tvco/%Vdd]

0.081

0.0260.020

20

805

Fref[MHz]

1471000-2000

56.516019550

Taj,noise[ps]

Fvco[MHz]

Simulated 0.13µm, worst case PVT (FF, -40C or 125C) with 10% step on Vdd

Comparison to Literature• 0.10 %Tvco/%Vdd for 2.5V, 800-1400MHz PLL

(M. Mansuri, ISSCC 2003)• 0.08 %Tvco/%Vdd for 2.0V, 800-1330MHz PLL with voltage regulator

(V. Van Kaenel, JSSC 1998)Room temperature with 10% step on Vdd

Conclusions• First demonstration of fully-automated PLL

design, from specification to GDSII

• PLL design problem cast in GP form reduces design time from weeks to hours

• Measured 0.18 µµµµm and 0.13 µµµµm CMOS PLL arrays agree with GP predictions (e.g. 1.9 GHz, 11 mW PLL with 5.8 ps long-term jitter)

• Robust, systematic, and efficient PLL design