Embed Size (px)
Citation preview
38
5xx Active & Low Power Mode Operation
39
Lab 2: ULP Operation
• Lab Goals – Learn ULP Best Practices– Learn & understand how to configure two key modules of the 5xx to
achieve ultra-low power operation. • Power Management Module (PMM)• Unified Clock System (UCS)
– Run, study and measure the configuration and consumption of 5 x Active & LPM3 scenarios:
• Active @ 8 MHz (Study: Working with the FLL)• Active @ 25 MHz (Study: PMM core voltage settings)• LPM3 REFO (Study: UCS and default settings) • LPM3 LFXT1 (Study: 32 kHz oscillator and fail-safe behavior)• LPM3 VLO (Study: Ultra-low power tradeoffs)
40
ULP Operation Best Practices
• Power-efficient MSP430 apps:– Minimize instantaneous current draw
– Maximize time spent in low power modes
• The MSP430 is inherently low-power
• But your design has a big impact on power efficiency!
• Proper low-power design techniques make the difference
41
ULP Operation Best Practices
• Power draw increases with…– Vcc
– CPU clock speed (MCLK)
– Temperature
• Slowing MCLK reduces instantaneous power, but usually increases active duty cycle– Power savings can be nullified
– The ULP ‘sweet spot’ that maximizes performance for the minimum current consumption per MIPS: 8 MHz MCLK
• Full operating range (down to 1.8V)
– 5xx has integrated LDO with variable output voltage
– Optimize core voltage for chosen MCLK speed
42
ULP Operation Best Practices
• When P- and N- channels are on simultaneously, result is “shoot-through current.”
43
ULP Operation Best Practices
• Digital input pins subject to shoot-through current– Input voltages between VIL and VIH cause shoot-
through if input is allowed to “float” (left unconnected)
• Port I/Os should– Driven as outputs
– Be driven at Vcc/ground by an external device
– Have a pull-up/down resistor
ULP Clock Control: UCS Defaults
• FLLREFCLK = XT1CLK
• ACLK = XT1CLK
• MCLK = DCOCLKDIV
• SMCLK = DCOCLKDIV• DCOCKLDIV = DCOCLK / 2 • DCO_freq ~= 2 MHz, so • MCLK_freq ~= 1 MHz• SMCLK_freq ~= 1MHz
44
45
ULP Clock Control: The 5xx FLL
• FLLREFCLK sources:– 32 kHz internal REFO– LFXT1 / XT1
crystal oscillator– XT2 crystal oscillator
• DCO frequency equation fDCO = (fFLLREFCLK / n) * (N + 1) * D – n = FLLREFDIV– N = FLLN– D = FLLD
46
ULP Clock Control: The 5xx DCO
• DCO ranges from 200 kHz – 60 MHz • RSEL bits select the range • DCO bits set one of 32 taps in each range• MOD bits mix two frequencies
fDCO and fDCO+1 to produce DCOCLK
47
Lab 2: Import CCS Projects
• Select Project > Import Existing CCS/CCE Project• Click Browse…• Point to the
~/5xx_ODW folder• Ensure Lab_2 - Lab_5
are selected• Select Copy projects
into workspace• Click Finish
48
Lab 2: Active @ 8 MHz
• Lab Goals:– Learn how to initialize the FLL – Measure a typical average current scenario @ 8 MHz
• Lab Steps: – Select Lab 2 as Active Project
[Right-click project name then“Select as Active Project”]
– Select ACTIVE_8_MHZas Active Build Config
– Download, run, then terminate– Disconnect 14-pin JTAG cable– Switch “Power Selector” to
BATT powered– Disconnect USB cable– Remove 430 PWR Jumper and connect multimeter across the leads to
read current (set multimeter to >= 10 mA setting) • Connect the red lead to the pin closest to the edge of the board
– Should see between 1.9 mA – 2.1 mA
49
Study: The ACTIVE_8_MHz.c Example
• halBoardInit( )– Initializes the GPIO for ULP operation
• Init_FLL_Settle( )– Selection of RSEL – Selection of DCO taps – Delay for FLL to settle – MCLK, SMCLK, ACLK source selection
• How to use in the future – #include “hal_ucs.h”– Check MSP430 application notes for hal_UCS and
hal_PMM library descriptions
50
Study: The ACTIVE_8_MHz.c Example
• while(1) != real world active current consumption
• CPU executes a 32-bit fetch
• while(1) jmp $ can result in very different current consumption depending on alignment
jmp $
nop jmp $
nop 32-bits 32-bits
<< 230 uA/MHz >> 230 uA/MHz
Only a single fetch! A fetch on every cycle!
51
Study: The ACTIVE_8_MHz.c Example
• Why ACTIVE_MODE_TEST( )?.text
ACTIVE_MODE_TEST MOV #0x2000, R4MOV #0x4, 0(R4) MOV &0x2000, &0x2002ADD @R4, 2(R4)SWPB @R4+MOV @R4, R5
IDD_AM_L1 XOR @R4+, &0x2020DEC R5JNZ IDD_AM_L1JMP ACTIVE_MODE_TEST.end
• Good mix of MSP430 instruction and access types
- Code mixes with types of instructions: type I,II, JMP, emu- Code mixes with address modes- Type of Instruction
# of instructions: 6+8*3 = 30ALU inst: 2+2*8 = 18 -60%Data Read inst: 4+1*8 = 12 -40%Data Write inst: -40%Control/Jump : 8 -26%
STOP
52
But what if we want to go faster than 8 MHz?
53
Power Management Module
• Integrated LDO: VCC → VCORE
• VCORE programmable to four levels • BOR always on• PMM is password protected
– Unlock: PMMCTL_H = 0xA5– Lock: PMMCTL_H = 0x00
• Integrated Supervision and Monitoring– Monitoring provides interrupts on low voltage condition– Supervision generates POR on low voltage condition
• Vcc domain is referred to as the high-side (SVSH, SVMH)• Core voltage domain is referred to as the low-side (SVSL, SVML)
• Accurate voltage supervision – 200nA - Normal Performance Mode (20 us response time)– 2 uA - Fast Performance Mode (2 us response time)
54
Changing VCORE
Increasing the Core Voltage1) Change the low-side monitor threshold 2) Change the core voltage level3) Wait until the core voltage level is reached4) Change supervisor threshold to match the monitor level
Decreasing the Core Voltage5) Decrease supervisor and monitor levels6) Decrease the core voltage level
55
Voltage Supervision & Monitoring
Default
• Normal Performance Mode • +800 nA active current consumption• 0 nA LPM2,3,4 current consumption• 150 us wakeup from LPM2,3,4
High-side Full Performance Mode
• High-side Full Performance Mode
• Low-side SVS / SVM disabled
• +4uA active current consumption
• +0uA LPM2,3,4 current consumption
• Automatic high-side protection when CPU is active
SVS / SVM disabled
• SVS / SVM disabled
• Zero-power BOR protection is ALWAYS ON
• 5 us wakeup from LPM2,3,4
• +0 uA active & LPM2,3,4 current consumption
High-side Fast Performance Mode
• High-side Fast Performance Mode
• Low-side SVS / SVM disabled
• 5 us wakeup from LPM2,3,4
• +4 uA active & LPM2,3,4 current consumption
• Automatic high-side protection when CPU is active
Maximum Robustness
• Fast Performance Mode
• 5 us wakeup from LPM2,3,4
• +8 uA active & LPMx current consumption
Current
150 us wakeup from LPMx
5 us wakeup from LPMx
56
Lab 2: Active @ 25 MHz
• Lab Goals:– Learn how to change COREV levels for > 8 MHz operation
– Measure a typical average current scenario @ 25 MHz
• Lab Steps: – Reconnect 14-pin JTAG cable, 430 PWR jumper & USB FET
– Select ACTIVE_25_MHZ as Active Build Config
– Download, run, then terminate
– Disconnect 14-pin JTAG cable
– Remove 430 PWR Jumper and connect multimeter across the leads to read current (set multimeter to >= 10 mA setting)
• Connect the red lead to the pin closest to the edge of the board
– Should see between 7.1 mA – 8.3 mA
57
Study: The ACTIVE_25_MHz.c Example
• SetVCore(PMMCOREV_3)– One level at a time!
//****************************************************************************//// Set VCore//****************************************************************************//unsigned int SetVCore (unsigned char level){
unsigned int actlevel;unsigned int status = 0;level &= PMMCOREV_3; // Set Mask for Max. levelactlevel = (PMMCTL0 & PMMCOREV_3); // Get actual VCore
while (((level != actlevel) && (status == 0)) || (level < actlevel)) // step by step increase or decrease
{if (level > actlevel)status = SetVCoreUp(++actlevel);
elsestatus = SetVCoreDown(--actlevel);
}return status;
}
• SVSx & SVMx management– Turns off SVSL and SVML– Leaves SVSH in Full Performance Mode– Delivers fast-wake-up (5 us) time with SVS protection on DVcc
STOP
58
But what if we want to enter low power mode?
59
Entering Low Power Modes
60
Interrupts, the Stack, and LPMx
• Entering Interrupts– Any currently executing instruction is completed.– The PC, which points to the next instruction, is pushed onto the stack.– The SR is pushed onto the stack.– The interrupt with the highest priority is selected – The interrupt request flag resets automatically on single-source flags. Multiple
source flags remain set for servicing by software.– The SR is cleared. This terminates any low-power mode. Because the GIE bit is
cleared, further interrupts are disabled.– The content of the interrupt vector is loaded into the PC; the program continues with
the interrupt service routine at that address.
61
Using Intrinsic Functions to Edit SR
• Intrinsic Functions: __bic_SR_register(LPM3_bits);__bic_SR_register_on_exit(LPM3_bits);__bis_SR_register(LPM3_bits + GIE);__bis_SR_register_on_exit(unsigned short a);__get_SR_register(void); __get_SR_register_on_exit(void);__enable_interrupts( );__disable_interrupts( );
• Other useful intrinsics:__no_operation();__delay_cycles(1000000);__bcd_add_short( short, short ); __bcd_add_long( long, long );__even_in_range( );
• Refer to “intrinsics.h” or compiler documentation
62
Lab 2: LPM3 REFO
• Lab Goals:– Learn how to enter LPM3 with default ACLK settings– Measure a typical average current scenario in LPM3 when the
internal 32 kHz REFO sources ACLK
• Lab Steps: – Reconnect 14-pin JTAG cable, 430 PWR jumper & USB FET– Select LPM3_REFO as Active Build Config – Download, run, then terminate – Disconnect 14-pin JTAG cable– Remove 430 PWR Jumper and connect multimeter across the
leads to read current (set multimeter to <= 200 uA setting) • Connect the red lead to the pin closest to the edge of the board
– LED will blink on/off (P1.0) if program is running correctly– Should see 4.3 uA – 4.9 uA when LED is OFF (~3 seconds)
63
Study: The LPM3_REFO.c Example
• Watchdog triggers interrupt every ~3 seconds /* Initialize WDT to interval timer mode, triggering every 3 - 4 seconds */
WDTCTL = WDTPW+WDTSSEL__VLO+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0;
SFRIE1 |= WDTIE; // Enable WDT interrupt
• Entering LPM3 using intrinsic functions__bis_SR_register(LPM3_bits + GIE); // Enter LPM3, enable interrupts
__no_operation(); // For debugger
• Return from ISR using intrinsic function// Watchdog Timer interrupt service routine
#pragma vector = WDT_VECTOR
__interrupt void WDT_ISR(void)
{
__bic_SR_register_on_exit(LPM3_bits);
}
} Note the ISR declaration!!
STOP
64
But I thought the LPM3 value was 2.1 uA, not 4.5 uA…
What could be the reasons I don’t see 2.1 uA?
Can I run RTC in this mode?
65
Fail-Safe Behavior & Clock Requests
• LFXT1 reverts to REFO• HFXT1 & XT2 revert to DCO • On startup, LFXT1 will fail
because quartz crystals are not instant-on!
• Clearing the fault flags allows expected default operation
• Modules place clock requests to the system clocks
• LPM3 entry can be prevented if a module requires SMCLK to operate properly!
• Must be very conscious of the clocks required in the system.
66
ULP Review of Available Oscillators
Clock Frequency Precision Current Draw Crystal Required
High-Frequency
DCO 100kHz –60MHz
Low 60uA
HFXT1/ XT2 4 - 32MHz High 260uA @ 12MHz X
MODOSC 5MHz n/a n/a
Low-Frequency
LFXT1 32kHz High 300nA X
VLO ~10kHz Low 60nA
REFO 32kHz Medium/High 3uA
RTC
67
Lab 2: LPM3 LFXT1
• Lab Goals:– Learn how to handle oscillator faults to set LFXT1 ACLK – Measure a typical average current scenario in LPM3 when the
external 32 kHz crystal on the LFXT1 oscillator sources ACLK
• Lab Steps: – Reconnect 14-pin JTAG cable, 430 PWR jumper & USB FET– Select LPM3_LFXT1 as Active Build Config – Download, run, then terminate – Disconnect 14-pin JTAG cable– Remove 430 PWR Jumper and connect multimeter across the
leads to read current (set multimeter to <= 200 uA setting) • Connect the red lead to the pin closest to the edge of the board
– LED will blink on/off (P1.0) if program is running correctly – Should see 1.9 – 2.4 uA
68
Study: The LPM3_LFXT1.c Example
• Initializing crystal pins & LFXT_Start ( );
/* Initialize LFXT1 */P7SEL |= BIT0+BIT1; // Enable crystal pins LFXT_Start (XT1DRIVE_0); // Set lowest power crystal drive
• LFXT_Start (XT1DRIVE_0);
void LFXT_Start(unsigned int xtdrive){
UCSCTL6_L |= XT1DRIVE1_L+XT1DRIVE0_L; // Highest drive setting for XT1 startup
while ((SFRIFG1 & OFIFG)){ // check OFIFG fault flagUCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT1HFOFFG+XT2OFFG); // Clear OSC fault FlagsSFRIFG1 &= ~OFIFG; // Clear OFIFG fault flag
}UCSCTL6 = (UCSCTL6 & ~(XT1DRIVE_3)) |(xtdrive); // set Drive mode
}
STOP
69
But what if we don’t need RTC and just want the lowest power available?
70
ULP Review of Available Oscillators
Clock Frequency Precision Current Draw Crystal Required
High-Frequency
DCO 100kHz –60MHz
Low 60uA
HFXT1/ XT2 4 - 32MHz High 260uA @ 12MHz X
MODOSC 5MHz n/a n/a
Low-Frequency
LFXT1 32kHz High 300nA X
VLO ~10kHz Low 60nA
REFO 32kHz Medium/High 3uA
RTC
71
Lab 2: LPM3 VLO
• Lab Goals:– Learn the tradeoffs for oscillators at VLO ACLK – Measure a typical average current scenario in LPM3 when the
VLO sources ACLK
• Lab Steps: – Reconnect 14-pin JTAG cable, 430 PWR jumper & USB FET– Select LPM3_VLO as Active Build Config – Download, run, then terminate – Disconnect 14-pin JTAG Cable– Remove 430 PWR Jumper and connect multimeter across the
leads to read current (set multimeter to <= 200 uA setting) • Connect the red lead to the pin closest to the edge of the board
– LED will blink on/off (P1.0) if program is running correctly– Should see between 1.2 – 1.42 uA
72
Study: The LPM3_VLO.c Example
• ACLK Clock Source Selection
SELECT_ACLK(SELA__VLOCLK); // Select VLO_CLOCK to source ACLK
• Other UCS_Library macros– SELECT_FLLREF(source)– SELECT_MCLK(source)– SELECT_SMCLK(source)– SELECT_MCLK_SMCLK(source)– XT1_TO_MCLK– XT2_TO_MCLK– XT1_TO_SMCLK– XT2_TO_SMCLK– ACLK_DIV(x)– MCLK_DIV(x)– SMCLK_DIV(x)
• Check MSP430 application notes for hal_UCS and hal_PMM library descriptions
STOP
73
Lab 2: ULP Operation
• Lab Goals – Learn ULP Best Practices– Learn & understand how to configure two key modules of the 5xx to
achieve ultra-low power operation. • Power Management Module (PMM)• Unified Clock System (UCS)
– Run, study and measure the configuration and consumption of 5 x Active & LPM3 scenarios:
• Active @ 8 MHz (Study: Working with the FLL)• Active @ 25 MHz (Study: PMM core voltage settings)• LPM3 REFO (Study: UCS and default settings) • LPM3 LFXT1 (Study: 32 kHz oscillator and fail-safe behavior)• LPM3 VLO (Study: Ultra-low power tradeoffs)
