On-Chip Automatic Analog Functional Testing and Measurementsstrouce/DaTseminar/stroud05f2.pdf · 2005. 10. 6. · IC Test Board Test System Test Field Cost Test per Fault $ $1000

OnOn--Chip Automatic Analog Chip Automatic Analog Functional Testing and Functional Testing and

MeasurementsMeasurementsChuck Stroud, Foster Dai, and Chuck Stroud, Foster Dai, and DayuDayu YangYang

Electrical & Computer EngineeringElectrical & Computer EngineeringAuburn UniversityAuburn University

from presentation to Select Universities Technology, Inc. (SUTI)from presentation to Select Universities Technology, Inc. (SUTI)May 26, 2005May 26, 2005

5/26/055/26/05 Auburn University SUTI PresentationAuburn University SUTI Presentation 22

OutlineOutline•• The testing problemThe testing problem

Manufacture & system testing and costManufacture & system testing and cost•• BuiltBuilt--In SelfIn Self--TestTest

How does it work and how wellHow does it work and how wellDigital vs. analog testingDigital vs. analog testing

•• Analog functional testingAnalog functional testingMeasurements vs. fault detectionMeasurements vs. fault detection

•• BISTBIST--based functional measurementsbased functional measurementsOur approach vs. othersOur approach vs. others

•• Products & applicationsProducts & applications


The Testing ProblemThe Testing Problem2000 International Technology Roadmap for Semiconductors2000 International Technology Roadmap for Semiconductors

(by the Semiconductor Industry Association (by the Semiconductor Industry Association -- SEMATECHSEMATECH) ) predicted by 2014:predicted by 2014:

•• Test machines will cost Test machines will cost more than $20M each!more than $20M each!Many people say we are already thereMany people say we are already there

•• It will cost It will cost moremore to test a transistor than to manufacture it!to test a transistor than to manufacture it!Many people say we are already thereMany people say we are already there

Testing cost > 50% of product costTesting cost > 50% of product cost5M5M--100M transistors on a chip100M transistors on a chip

1 faulty transistor 1 faulty transistor ⇒⇒ faulty chipfaulty chip•• BuiltBuilt--In SelfIn Self--Test (BIST) is the most likely solutionTest (BIST) is the most likely solution

Analog BIST is needed for mixedAnalog BIST is needed for mixed--signal systemssignal systemsFault diagnosis is needed with BISTFault diagnosis is needed with BISTMethods needed for automatic implementation of BISTMethods needed for automatic implementation of BIST


Manufacture TestingManufacture Testing•• Where are the $20M testers?Where are the $20M testers?

Wafer testingWafer testingInk dot defective chipsInk dot defective chips

Typically not done for RF analog Typically not done for RF analog devicesdevices

Too costly in time & equipmentToo costly in time & equipmentPackage only good chipsPackage only good chips

Eliminates packaging defective partsEliminates packaging defective partsPackaging costs can be highPackaging costs can be high

Package testingPackage testingPackaging & handling Packaging & handling ⇒⇒ defectsdefectsBurnBurn--in testing for infant mortalityin testing for infant mortality

Board testingBoard testingAssembly & handling Assembly & handling ⇒⇒ defectsdefects


System TestingSystem Testing•• Manufacture systemManufacture system--level testlevel test

Unit & system testingUnit & system testingDefects due to assemblyDefects due to assembly

More customized testers specific to More customized testers specific to systemsystem

•• SystemSystem--level testing in the fieldlevel testing in the fieldTypically done periodically for Typically done periodically for

High reliability systemsHigh reliability systemsHigh availability systemsHigh availability systems

Done nightly for telephone switching Done nightly for telephone switching systemssystems

Special system hardware/software Special system hardware/software neededneeded

Cost is in system design & development Cost is in system design & development efforteffort


The Testing Problem (continued)The Testing Problem (continued)•• Automatic Test Equipment (ATE) cost is increasingAutomatic Test Equipment (ATE) cost is increasing

HighHigh--speed testing needs more expensive ATEspeed testing needs more expensive ATEChips are operating at higher speedsChips are operating at higher speeds

Longer test sequences for more complex chipsLonger test sequences for more complex chips

•• Product testing goes on long after design is doneProduct testing goes on long after design is doneCumulative testing cost must be consideredCumulative testing cost must be consideredCost of fault location/identification and repairCost of fault location/identification and repair

ICICTestTest

BoardBoardTestTest

SystemSystemTestTest

FieldFieldTestTestCost

perFault

$

$1000

$100

$10

$1

Factor of 10 increase in costFactor of 10 increase in costGenerally acceptedGenerally accepted

Sun Microsystems Sun Microsystems says multiplier is says multiplier is greater than 10 for greater than 10 for complex systemscomplex systems


Digital vs. Analog TestingDigital vs. Analog Testing•• Digital testing is defect orientedDigital testing is defect oriented

Test development based on fault models thatTest development based on fault models thatAttempt to accurately reflect behavior of defectsAttempt to accurately reflect behavior of defectsAre computationally efficient for fault simulationAre computationally efficient for fault simulation

•• Analog testing is specification orientedAnalog testing is specification orientedFunctional test based on specificationsFunctional test based on specifications

Linearity, frequency response, signalLinearity, frequency response, signal--toto--noise rationoise ratioRecent attempts made in defect oriented testingRecent attempts made in defect oriented testing

Difficult to determine if a circuit is faulty or just Difficult to determine if a circuit is faulty or just outside of nominal operation rangeoutside of nominal operation range

Chance of throwing away good productChance of throwing away good productFunctional testing is needed to compensate for Functional testing is needed to compensate for analog circuit operational variationanalog circuit operational variation


Other MixedOther Mixed--Signal BISTSignal BIST•• LFSR/accumulator (Stroud, 1987)LFSR/accumulator (Stroud, 1987)•• LFSR/SAR (LFSR/SAR (OhletzOhletz, 1991), 1991)•• Oscillation (Oscillation (KaminskaKaminska, 1996), 1996)

OPMAX OPMAX –– later bought out by later bought out by FluenceFluence•• MultiMulti--waveform/accumulator (Stroud, 1996)waveform/accumulator (Stroud, 1996)•• Histogram (Frisch, 1997)Histogram (Frisch, 1997)

TektronixTektronixLater offered by Logic Vision?Later offered by Logic Vision?

•• MultiMulti--waveform/accumulator (Stroud, 2001)waveform/accumulator (Stroud, 2001)•• FFT (FFT (EmmertEmmert, 2004), 2004)


AnalogAnalogCircuitCircuit

AnalogAnalogSystemSystemInputsInputs

ADCADCSystemSystemFunctionFunction

DigitalDigitalSystemSystemOutputsOutputs

AnalogAnalogSystemSystemOutputsOutputs

SystemSystemFunctionFunction

DigitalDigitalSystemSystemInputsInputs

Digital CircuitryDigital Circuitry

DACDAC

Analog CircuitryAnalog Circuitry

AnalogAnalogCircuitCircuit

BIST for MixedBIST for Mixed--Signal SystemsSignal Systems

ORAORA

TPGTPG

TestTestControlControl

MuxMux

AnalogAnalogMUXMUXBIST DoneBIST Done

BIST StartBIST Start

Pass/FailPass/Fail

101011000111011010101011000111011010

101011000111011010101011000111011010

•• Digital circuitry tests analog circuitryDigital circuitry tests analog circuitryMinimize area & performance penalty to analog circuitryMinimize area & performance penalty to analog circuitry

•• Parameterized models (VHDL or Parameterized models (VHDL or VerilogVerilog))Automatic synthesis into any mixedAutomatic synthesis into any mixed--signal systemsignal system


BIST for MixedBIST for Mixed--Signal SystemsSignal Systems

ADCADC

DACDACTPGTPG

ORAORA

AnalogAnalogCktryCktry

AnalogAnalogCktryCktry

•• Multiple BIST sequences with analog loopbacksMultiple BIST sequences with analog loopbacksPass/fail results indicate location of faulty analog circuitryPass/fail results indicate location of faulty analog circuitry

•• Location & number of analog loopback Location & number of analog loopback MUXsMUXsDetermine analog diagnostic resolution & fault coverageDetermine analog diagnostic resolution & fault coverageDesigner can tradeDesigner can trade--off analog area overhead & off analog area overhead & performance penaltiesperformance penalties


Application to RF Application to RF TranceiverTranceiver

Functionality of various components measured and compensatedFunctionality of various components measured and compensated•• Reduce power consumption (extend battery life)Reduce power consumption (extend battery life)•• Improve quality of communications Improve quality of communications


Important Analog Functional TestsImportant Analog Functional Tests•• LinearityLinearity

33rdrd--order order intermodulationintermodulation (IP3)(IP3)Quality of systemQuality of system

•• Frequency ResponseFrequency ResponseGainGainPhasePhase

•• SignalSignal--toto--Noise Ratio (SNR)Noise Ratio (SNR)Noise FigureNoise Figure

•• SS--parametersparametersInput impedanceInput impedanceOutput impedanceOutput impedance


IntermodulationIntermodulation

•• Two signals with different frequencies are Two signals with different frequencies are applied to a nonlinear systemapplied to a nonlinear system

Output exhibits components that are not Output exhibits components that are not harmonics of input fundamental frequenciesharmonics of input fundamental frequencies

•• 33rdrd--order order intermodulationintermodulation (IM3) is critical(IM3) is criticalVery close to fundamental frequenciesVery close to fundamental frequencies

IM3IM3

ff11 ff22

7 87 8 freqfreq

ff11 ff22

8800 22 44 66 1010 1212 1414 1616 1818 2020 2222 2424

ff22-- ff11 ff11++ff22

22ff11 22ff22

33ff11 33ff2222ff11-- ff22 22ff22-- ff11

freqfreq


Mathematical FoundationMathematical Foundation•• Input 2Input 2--tone:tone:

x(x(tt)=A)=A11cos cos ωω11tt + A+ A22 coscos ωω22tt

•• Output of nonOutput of non--linear device:linear device:y(y(tt)=α)=α00+α+α11x(x(tt)+α)+α22xx22((tt)+α)+α33xx33((tt)+)+……

•• Substituting Substituting x(x(tt) into ) into y(y(tt):):y(y(tt) = ) = ½½αα22(A(A11

22+A+A2222) )

+ [α+ [α11AA11+¾α+¾α33AA11(A(A1122+2A+2A22

22)]cos)]cosωω11t t + [α+ [α11AA22+¾α+¾α33AA22(2A(2A1122+A+A22

22)]cos)]cosωω22tt+ + ½½αα22(A(A11

22cos2cos2ωω11tt+A+A2222cos2cos2ωω22tt ) )

+ α+ α22AA11AA22[cos([cos(ωω11++ωω22))tt+cos(+cos(ωω11--ωω22))tt]]+ ¼α+ ¼α33[A[A11

33cos3cos3ωω11tt+A+A2222cos3cos3ωω22tt]]

+ ¾α+ ¾α33{A{A1122AA22[cos(2[cos(2ωω11++ωω22))tt+cos(2+cos(2ωω11--ωω22))tt]]

+A+A11AA2222[cos(2[cos(2ωω22++ωω11))tt+cos(2+cos(2ωω22--ωω11))tt]}]}

freqfreqωω11 ωω22 22ωω22--ωω1122ωω11--ωω22

¾ ¾ αα33AA22

αα11AA∆∆PP


3rd3rd--order Intercept Point (IP3)order Intercept Point (IP3)

freqfreqωω11 ωω22 22ωω22--ωω1122ωω11--ωω22

¾ ¾ αα33AA22

αα11AA∆∆PP

Input PowerInput Power(IIP3)(IIP3)

IP3IP3 20log(20log(αα11A)A)Out

put P

ower

Out

put P

ower

(OIP

3)(O

IP3)

∆∆P/2P/2

IM3IM3

fundamentalfundamental∆∆PP

20log(¾20log(¾αα33AA33))

•• IP3 is theoretical input power point where 3IP3 is theoretical input power point where 3rdrd--order order distortion and fundamental output lines interceptdistortion and fundamental output lines intercept

•• IIPIIP33[dBm]= [dBm]= ++PPinin[dBm[dBm]]∆∆P[dBP[dB]]22

Practical measurementPractical measurementwith spectrum analyzerwith spectrum analyzer


Direct Digital Synthesis (DDS)Direct Digital Synthesis (DDS)•• DDS DDS ⇒⇒ generating deterministic generating deterministic

communication carrier/reference signals in communication carrier/reference signals in discrete time using digital hardwarediscrete time using digital hardware

converted into analog signals using a DACconverted into analog signals using a DAC

•• AdvantagesAdvantagesCapable of generating a variety of waveformsCapable of generating a variety of waveformsHigh precision High precision ⇒⇒ sub Hzsub HzDigital circuitryDigital circuitry

Small size Small size ⇒⇒ fraction of analog synthesizer sizefraction of analog synthesizer sizeLow costLow costEasy implementationEasy implementation


Typical DDS ArchitectureTypical DDS Architecture

1/1/ffoutout1/1/ffoutout

1/1/ffclkclk

1/1/ffoutout

1/1/ffclkclk

1/1/ffoutout

1/1/ffclkclk

ffoutout==ffclkclkFFrr

22NN

AccumAccum--ulatorulator

NN

FrequencyFrequencyWordWord

WW SineSineLookupLookupTableTable

RR LowLowPassPassFilterFilter

SineSineWaveWaveFFrr

clkclk

Digital CircuitsDigital Circuits

DD--toto--AAConvConv..


22--Tone Test Pattern GeneratorTone Test Pattern Generator

LowLowPassPassFilterFilter 22--tonetone

WaveformWaveform

DD--toto--AAConvConv..

SineSineLookupLookupTable 1Table 1

FFrr11AccumAccum--ulatorulator

#1#1

SineSineLookupLookupTable 2Table 2

FFrr22AccumAccum--ulatorulator

#2#2

ΣΣ

•• Two DDS circuits generate two fundamental tonesTwo DDS circuits generate two fundamental tonesFFrr1 & 1 & FFrr2 control frequencies tones2 control frequencies tones

•• DDS outputs are superimposed using adder to DDS outputs are superimposed using adder to generate 2generate 2--tone waveform for IP3 measurementtone waveform for IP3 measurement

•• DAC & LPF convert to actual analog test waveformDAC & LPF convert to actual analog test waveform


Actual 2Actual 2--Tone IP3 MeasurementTone IP3 Measurement

DAC output DAC output x(x(tt): ):

DUT output DUT output y(y(tt):):

∆∆PP

•• Outputs of DAC and DUT taken with scope from Outputs of DAC and DUT taken with scope from our experimental hardware implementationour experimental hardware implementation

•• Typical Typical ∆∆PP measurement measurement requires expensive, requires expensive, external spectrum analyzerexternal spectrum analyzer

For BIST we need an efficient output response analyzerFor BIST we need an efficient output response analyzer


Output Response AnalyzerOutput Response AnalyzerMultiplier/accumulatorMultiplier/accumulator--based ORAbased ORA•• Multiply the output response by a frequencyMultiply the output response by a frequency

NN--bit multiplier, bit multiplier, NN = number of ADC bits= number of ADC bits•• Accumulate the multiplication resultAccumulate the multiplication result

NN++MM--bit accumulator for < 2bit accumulator for < 2MM clock cycle samplesclock cycle samples•• Average by # of accumulation clock cyclesAverage by # of accumulation clock cycles

Gives DC value proportional to power of signal at freqGives DC value proportional to power of signal at freq•• AdvantagesAdvantages

Easy to implementEasy to implementLow area overheadLow area overheadExact frequency controlExact frequency controlMore efficient than FFTMore efficient than FFT

XXy(y(tt))

ffxx

ΣΣ DCDCmultipliermultiplier

accumulatoraccumulator


DCDC11 AccumulatorAccumulator

0

20

40

60

80

100

120

140

1 21 41 61 81 101 121 141 161 181 201 221 241 261

Clock cycles (x50)

MATLAB Simulation ResultsMATLAB Simulation ResultsActual Hardware ResultsActual Hardware Results

•• y(y(tt) x ) x ff22 ⇒⇒ DCDC11≈≈ ½½AA2222αα11

•• Ripple in slope due to low Ripple in slope due to low frequency componentsfrequency components

Longer accumulation reduces effectLonger accumulation reduces effectfreqfreq

ff22 22ff22--ff11

¾ ¾ αα33AA22∆∆PP

αα11AA

XX

y(y(tt))

ff22

ΣΣ DCDC11

slope = DCslope = DC11≈≈ ½½AA22

22αα11


DCDC22 AccumulatorAccumulator

slope = DCslope = DC22≈≈ 33//88AA11

22AA2222αα33

-5

0

5

10

15

20

1 21 41 61 81 101 121 141 161 181 201 221 241 261

Clock cycles (x50)

MATLAB Simulation ResultsMATLAB Simulation ResultsActual Hardware ResultsActual Hardware Results

•• y(y(tt) x 2) x 2ff22--ff11 ⇒⇒ DCDC22≈≈ 33//88AA1122AA22

22αα33•• Ripple is bigger for DCRipple is bigger for DC22

Signal is smallerSignal is smallerTest controller obtains DCTest controller obtains DC22 at integral at integral multiple of multiple of 22ff22--ff11 freqfreq

ff22 22ff22--ff11

¾ ¾ αα33AA22∆∆PP

αα11AAXX

y(y(tt))

22ff22--ff11

ΣΣ DCDC22


BISTBIST--based based ∆∆P P MeasruementMeasruement•• DCDC11 & DC& DC22 are proportional to power at are proportional to power at ff22 & 2& 2ff22--ff11

•• Only need DCOnly need DC11 & DC& DC22 from accumulators to calculatefrom accumulators to calculate∆∆PP = 20 log (DC= 20 log (DC11) ) –– 20 log (DC20 log (DC22))

MATLAB Simulation ResultsMATLAB Simulation Results

0

10

20

30

40

50

60

1 21 41 61 81 101 121 141 161 181 201 221 241 261

Clock cycles (x50)

Actual Hardware ResultsActual Hardware Results


BIST ArchitectureBIST Architecture

XXTest Pattern GeneratorTest Pattern Generator

Output ResponseOutput ResponseAnalyzerAnalyzer

LUT2LUT2 AccumAccumff22 AccumAccum

x(x(tt)=cos()=cos(ff11)+cos()+cos(ff22))

DC1DC1

LUT1LUT1ff11 AccumAccum ΣΣ

LUT3LUT322ff22--ff11 AccumAccum

DACDAC DUTDUT ADCADC

y(y(tt))

XX DC2DC2AccumAccum

DC2DC2

•• BISTBIST--based IP3 measurementbased IP3 measurementReduce circuit by repeating test sequence for DCReduce circuit by repeating test sequence for DC22

•• BISTBIST--based frequency response needs subsetbased frequency response needs subset


Hardware ResultsHardware Results

∆∆PP≈≈1414

BIST measures BIST measures ∆∆P P ≈≈ 1414 Spectrum analyzerSpectrum analyzer

5

10

15

20

25

30

1 201 401 601 801 1001 1201

Clock Cycles (x100)

Del

ta_P

(dB

)

∆∆P distribution for 1000P distribution for 1000BIST BIST measurementmeasurementss

mean=13.97 dB, mean=13.97 dB, σσ =0.082=0.0820

0.5

1

1.5

2

13.68 13.77 13.87 13.96 14.05 14.14 14.24

Measured Delta_P(dB)

Per

cent

age(

%)


Measurements in Noisy Test SetMeasurements in Noisy Test Set--upup

0

5

10

15

20

25

30

35

40

1 21 41 61 81 101 121 141 161 181 201 221 241 261

0

5

10

15

20

25

30

35

40

1 21 41 61 81 101 121 141 161 181 201 221 241 261

14 dB 14 dB ∆∆PP BIST measurement BIST measurement inin noisy test setnoisy test set--upup

17.4 dB 17.4 dB ∆∆PP measurementmeasurementinin less noisy test setless noisy test set--upup


More MeasurementsMore Measurements• Results for

1000 BIST measurements

Better accuracy Better accuracy than spectrum than spectrum analyzeranalyzer

0102030405060708090

100

24.3

7

24.3

9

24.4

1

24.4

3

24.4

5

24.4

7

24.4

9

24.5

2

24.5

4

24.5

6

24.5

8

24.6

0

24.6

2

24.6

4

24.6

7

24.6

9

delta P

Freq

uenc

y (x

0.00

1)

0102030405060708090

14.2

90

14.2

92

14.2

94

14.2

97

14.2

99

14.3

01

14.3

03

14.3

06

14.3

08

14.3

10

14.3

13

14.3

15

14.3

17

delta P

Freq

uenc

y (x

0.00

1)

BIST MeasurementBIST Measurement

0.0030.0030.0540.05424.5224.5224.5 dB24.5 dB0.000030.000030.00550.005514.314.314.3 dB14.3 dB

σσ22σσmeanmeanSpectrumSpectrumAnalyzerAnalyzer


BIST IP3 Measurement ResultsBIST IP3 Measurement Results•• Good agreement with actual values for Good agreement with actual values for ∆∆PP < 30dB< 30dB•• For measured For measured ∆∆PP > 30dB, the actual > 30dB, the actual ∆∆P P is greateris greater

30dB limit due to 830dB limit due to 8--bit DAC/ADC with 6bit DAC/ADC with 6--bit resolutionbit resolutionGood threshold since Good threshold since ∆∆P P < 30dB is of most interest< 30dB is of most interest

10

15

20

25

30

35

40

45

50

10 15 20 25 30 35 40 45 50

actual delta P

BIST

mea

sure

d de

lta P


Frequency ResponseFrequency Response•• Gain and phase as a function of frequencyGain and phase as a function of frequency

Important analog function Important analog function measruementmeasruement

•• Sweep through frequencies adjusting DDS Sweep through frequencies adjusting DDS ff inputinputMeasure gain at output using BIST circuitMeasure gain at output using BIST circuit

Phase delay produces incorrect gain measurement results in ORAPhase delay produces incorrect gain measurement results in ORA

GainGain

PhasePhase


Phase Delay Phase Delay –– ORA MultiplicationORA Multiplication

-1.5

-1

-0.5

0

0.5

1

1.50

0.5 1

1.5 2

2.5 3

3.5 4

4.5 5

5.5 6

6.5

unity gain sine waveunity gain sine wave cosine wavecosine wave(270(270°° phase delayphase delay))

sine X sinesine X sine

cosine X sinecosine X sine

5/26/055/26/05 Auburn University SUTI PresentationAuburn University SUTI Presentation 3131-2

0

2

4

6

8

10

12

140

0.5 1

1.5 2

2.5 3

3.5 4

4.5 5

5.5 6

6.5

Phase Delay Phase Delay –– ORA AccumulationORA Accumulation

cosine X sinecosine X sineaccumulationaccumulation

sine X sinesine X sineaccumulationaccumulation

sine X sinesine X sine

cosine X sinecosine X sine


Phase Delay Phase Delay MeasruementMeasruement•• y(y(tt) ) xx coscos ff ⇒⇒ DCDC33 ≈≈ ½½AA22αα coscos∆φ∆φ•• y(y(tt) ) xx sin sin ff ⇒⇒ DCDC44 ≈≈ ½½AA22αα sinsin∆φ∆φ•• Hence, we measure phase delayHence, we measure phase delay

∆φ∆φ = tan= tan--11(DC(DC44/DC/DC33))

MATLAB simulation results MATLAB simulation results for output for output ∆φ∆φ = 135= 135°°

y(y(tt))

coscos ffXX ΣΣ

DCDC33

y(y(tt))

sinsin ffXX ΣΣ

DCDC44


BISTBIST--Based MeasurementBased Measurement

XXTest Pattern GeneratorTest Pattern Generator

Output ResponseOutput ResponseAnalyzerAnalyzer

CosCosLUTLUT AccumAccum

ffAccumAccum

x(x(tt)=)=cos(cos(ff))

DC3DC3

SinSinLUTLUTAccumAccum

DACDAC DUTDUT ADCADCy(y(tt))

XX DC4DC4AccumAccum

DC4DC4

•• Sweep through frequencies Sweep through frequencies Measure phase delayMeasure phase delayMeasure gain with correction for phase delayMeasure gain with correction for phase delay

Gain = DC3/cosGain = DC3/cos∆φ∆φ == DC4/sinDC4/sin∆φ∆φ•• Subset of BIST circuit for IP3 measurementSubset of BIST circuit for IP3 measurement

Can timeCan time--share ORAshare ORA

ff

cos(cos(ff))

sin(sin(ff))

GainGain

ff


Phase Delay Measurement ResultsPhase Delay Measurement Results

0

50

100

150

200

250

300

350

0 20 40 60 80 100 120 140

Millions

Thousands

Accumulation Cycles

Accumulator Value

DC4

DC3

DC3 and DC4 measured for DC3 and DC4 measured for ∆φ∆φ ≈≈7979°°


Phase MeasurementPhase Measurement

-100

-80

-60

-40

-20

0

0 5 10 15 20 25 30 35 40 45 50

Frequency K H z

Phase D

elay d

egre

es

actual m easurem ent

B IS T m easurem ent


Gain MeasurementGain Measurement

-14

-12

-10

-8

-6

-4

-2

0

0 5 10 15 20 25 30 35 40 45 50

Frequency K H z

Am

plitude d

B

B IS T m easurem ent

actual m easurem ent


Experimental Implementation of BISTExperimental Implementation of BIST•• TPG, ORA, test controller, & PC interface circuitsTPG, ORA, test controller, & PC interface circuits

Three 8Three 8--bit DDSs, two 17bit DDSs, two 17--bit bit ORAsORAs, serial interface, serial interfaceImplementation in VerilogImplementation in VerilogSynthesized into Xilinx Spartan 2S50 FPGASynthesized into Xilinx Spartan 2S50 FPGA

•• Amplifier device under test implemented in FPAAAmplifier device under test implemented in FPAA•• DACDAC--ADC PCBADC PCB

0

200

400

600

800

1000

1200

1400

1600

Slices LUTs FFs

Total in FPGADouble ORASingle ORAPCPC FPGAFPGA

TPG/ORATPG/ORA

DAC &DAC &ADCADC

FPAAFPAADUTDUT


Comparison to Other ApproachesComparison to Other Approaches•• FFTFFT--based approach report for 2based approach report for 2--tone testtone test

Basis for IP3 measurementBasis for IP3 measurementBut this approach did not measure IP3But this approach did not measure IP3

Required largest Xilinx FPGARequired largest Xilinx FPGA5,062 flip5,062 flip--flops & 106,553 combinational logic gatesflops & 106,553 combinational logic gates

Ours fits in smallest Xilinx FPGA with 160 flipOurs fits in smallest Xilinx FPGA with 160 flip--flops & 1200 flops & 1200 combinational logic gatescombinational logic gates

FFT looks at all frequencies simultaneouslyFFT looks at all frequencies simultaneouslyRequires sufficient resolution for accurate test and Requires sufficient resolution for accurate test and measurements measurements –– therefore, very largetherefore, very large

Ours looks at one frequency at a time which can be easily Ours looks at one frequency at a time which can be easily controlled controlled –– therefore, no resolution issuestherefore, no resolution issues

•• Other approaches are based offOther approaches are based off--chipchipIncluding this FFTIncluding this FFT--based approach since it is too big based approach since it is too big for onfor on--chip implementationchip implementation

Documents

On-Chip Automatic Analog Functional Testing and Measurementsstrouce/DaTseminar/stroud05f2.pdf · 2005. 10. 6. · IC Test Board Test System Test Field Cost Test per Fault $ $1000