A Test Pattern Generator forA Test Pattern Generator forDSP BIST in VirtexDSP BIST in Virtex--44

Chris EricksonChris Erickson

2/7/07 2

Outline of PresentationOutline of PresentationOverview of Digital Signal ProcessorOverview of Digital Signal Processor

Test configurationsTest configurationsTest problemsTest problems

Multiplier Implementation ComparisonMultiplier Implementation ComparisonArray multiplierArray multiplierModified Booth multiplierModified Booth multiplier

Test Algorithm ComparisonTest Algorithm ComparisonApplying each algorithm to all multipliersApplying each algorithm to all multipliersExperimental ResultsExperimental Results

Summary and ConclusionsSummary and Conclusions

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Primary Inputs Primary Inputs A A –– 18 bits18 bitsB B –– 18 bits18 bitsC C –– 48 bits48 bitsCinCinSubtractSubtract

Cascade Inputs Cascade Inputs BCinBCin –– 18 bits18 bitsPCinPCin –– 48 bits48 bits

Primary Outputs Primary Outputs P P –– 48 bits48 bits

Cascade OutputsCascade OutputsPCoutPCout –– 48 bits48 bitsBCoutBCout –– 18 bits18 bits

Outline of DSPOutline of DSP

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Test Configurations & ProblemsTest Configurations & Problems

Test configurations = 3 minimumTest configurations = 3 minimumTest Problems Test Problems –– no implementation detailsno implementation details

18x1818x18--bit Multiplierbit Multiplier4848--bit (3bit (3--input) Adder/input) Adder/SubtactorSubtactor

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Test Pattern GeneratorTest Pattern GeneratorNeed TPG to complete DSP BIST developmentNeed TPG to complete DSP BIST developmentGoals for multiplier and adder/Goals for multiplier and adder/subtractorsubtractor

Develop a set of test patterns that will work Develop a set of test patterns that will work regardless of design implementation used by Xilinxregardless of design implementation used by XilinxDevelop a minimum vector set that will provide 100% Develop a minimum vector set that will provide 100% fault coveragefault coverage

Previous multiplier work includes:Previous multiplier work includes:Minimum test vectors for a 16x16 array multiplierMinimum test vectors for a 16x16 array multiplier

10 test vectors for C6288 (10 test vectors for C6288 (KalyanaKalyana KantipudiKantipudi’’ss MS Defense)MS Defense)Test algorithm for a 16 x 16 Modified Booth multiplierTest algorithm for a 16 x 16 Modified Booth multiplier

256 test vectors256 test vectorsGizopoulosGizopoulos, , et.alet.al., IEEE Design & Test 1998., IEEE Design & Test 1998

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Multiplier ComparisonMultiplier ComparisonArray MultiplierArray Multiplier

Uses full addersUses full addersEasy to implementEasy to implementLow area overheadLow area overhead

18x1818x18--bitbit# gates = 1800# gates = 1800

SlowSlowImplementation Implementation choice for small area choice for small area applications applications

Booth MultiplierBooth MultiplierUses carryUses carry--save adderssave addersComplex to implementComplex to implementLarge area overheadLarge area overhead

18x1818x18--bitbit# gates = 2600# gates = 2600

FastFastImplementation choice Implementation choice for high performance for high performance applicationsapplicationsUse in Use in VirtexVirtex--IIII

Probably used in VirtexProbably used in Virtex--44

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Ripple CarryRipple CarryB0A0B1A1B2A3 B3 A2

S3 S2 S1 S0

Carryout Carryin

Easy and efficient to build but not fast. Every bit calculation is done in series. Not

an option for circuits requiring speed.

FAFA FA FA

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CarryCarry--Save AdderSave Adder

S3 S2 S1 S0

Only more efficient than ripple-carry when the number of inputs >= 3

B0A0 C0B3A3 C3 B2A2 C2 B1A1 C1

Carry3

FAFA FA FA

HAFAFAFA

Carry0Carry1Carry2

CarryinCarryout HA

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Carry LookCarry Look--AheadAhead

CarryinCarryout

B0A0B1A1B2A3 B3 A2

S3 S2 S1 S0

Requires significantly more area and logic. Speeds up calculation time immensely since

calculations can be completed in parallel.

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Array MultiplierArray Multiplier

HA

FA

HAFA FA

HA HA

FAFA

FAFA

FA

B0A0B0A1B0A2B0An-1

B3An-1

B2An-1

B1An-1

An-2B3

A1B1

A0B1

A1B3

A0B3

An-2B2

An-2B1

A0B2

A1B2

S0

S1

S2

S3

SnSn+1S2n-1S2n-2

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Modified Booth MultiplierModified Booth Multiplier

r

pp

A0

A1

A2

A3

A4

A5

A6A7

r

pp pp pp pp

pp pp pp pp pp

r

pp pp pp pp pp

r

pp pp pp pp pp

3,0 3,1 3,2 3,3

2,0 2,1 2,2 2,3

1,0 1,1 1,2 1,3

0,0 0,1 0,2 0,3

B0 B1 B2 B3

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Modified Booth MultiplierModified Booth Multiplier

P4P3P2P1P0

F F F F F

F F F F F

H H H H H

F F F F F

2,23,0 2,33,1

1,41,22,0 1,32,1

0,21,0 0,31,1

0,0 0,1

P10P9

P8

P7

P11

P6

P5

A7

A5

A3

A1

3,3 3,42,43,2

0,4

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Fault Simulation ModelsFault Simulation Models

ASL models developed for 18x18ASL models developed for 18x18--bitbitArray multiplier Array multiplier Modified Booth multiplierModified Booth multiplier

Applied previous test algorithms to both Applied previous test algorithms to both multipliersmultipliers

Single stuckSingle stuck--at gateat gate--level fault model with level fault model with AUSIMAUSIM

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Vector create/edit/compare ProgramVector create/edit/compare ProgramWill take a vector list and expand itWill take a vector list and expand itWill take the results of simulation and Will take the results of simulation and compare to its own generated resultscompare to its own generated resultsWill indicate where errors occurredWill indicate where errors occurredCapable of segmenting and parsing Capable of segmenting and parsing through long lines of binary data to through long lines of binary data to produce a readable, understandable produce a readable, understandable formatformat

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Vector Program ExampleVector Program Example

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Pattern ExpansionPattern Expansion

Expanded 18Expanded 18--bit Patternbit Pattern

110110110110110110 110111111111111111110110110110110110 110111111111111111011011011011011011 111111111111111111011011011011011011 111111111111111111000000000000000000 001011111111111111000000000000000000 001011111111111111101101101101101101 110111111111111111101101101101101101 110111111111111111111111111111111111 110101010101010101111111111111111111 110101010101010101111111111111111111 011010101010101010111111111111111111 011010101010101010001111111111111101 110101010101010101001111111111111101 110101010101010101001111111111111101 101010101010101011001111111111111101 101010101010101011111011011011011011 001011111111111111111011011011011011 001011111111111111110110110110110110 101010101010101010110110110110110110 101010101010101010

Minimum 10 vector set for 16Minimum 10 vector set for 16--bit Patternbit Pattern

1101101101101101 11011111111111111101101101101101 11011111111111110110110110110110 11111111111111110110110110110110 11111111111111110000000000000000 00101111111111110000000000000000 00101111111111111011011011011011 11011111111111111011011011011011 11011111111111111111111111111111 11010101010101011111111111111111 11010101010101011111111111111111 01101010101010101111111111111111 01101010101010100011111111111101 11010101010101010011111111111101 11010101010101010011111111111101 10101010101010110011111111111101 10101010101010111110110110110110 00101111111111111110110110110110 00101111111111111101101101101100 10101010101010101101101101101100 1010101010101010

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Array Multiplier Array Multiplier TestTest AlgorithmAlgorithm10 vectors total for C628810 vectors total for C628818x1818x18--bit array multiplier resultsbit array multiplier results

≈≈ 95%95%Pattern expansion requiredPattern expansion required

To go from 16x16To go from 16x16--bit for C6288 to 18x18bit for C6288 to 18x18--bit fro DSPbit fro DSP

Booth multiplier resultsBooth multiplier results≈≈ 37% with carry37% with carry--looklook--ahead implementationahead implementation≈≈ 62% with carry62% with carry--save implementationsave implementation

Booth multiplier models may have had bugsBooth multiplier models may have had bugs

Array multiplier test vectors do not test Booth Array multiplier test vectors do not test Booth multipliermultiplier

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Booth Multiplier Test AlgorithmBooth Multiplier Test Algorithm

Uses an 8Uses an 8--bit counter or bit counter or LFSRLFSRIs based on pseudoIs based on pseudo--exhaustive testingexhaustive testingReported to provide Reported to provide >99% fault coverage on >99% fault coverage on any size Nany size N--bit modified bit modified Booth multiplierBooth multiplier

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Test PatternsTest Patterns0000 0000 00000000 00000000 00000000 00000000 000000000001 0001 00010001 00010001 00010001 00010001 000100010010 0010 00100010 00100010 00100010 00100010 001000100011 0011 00110011 00110011 00110011 00110011 001100110100 0100 01000100 01000100 01000100 01000100 010001000101 0101 01010101 01010101 01010101 01010101 010101010110 0110 01100110 01100110 01100110 01100110 011001100111 0111 01110111 01110111 01110111 01110111 011101111000 1000 10001000 10001000 10001000 10001000 100010001001 1001 10011001 10011001 10011001 10011001 100110011010 1010 10101010 10101010 10101010 10101010 101010101011 1011 10111011 10111011 10111011 10111011 101110111100 1100 11001100 11001100 11001100 11001100 110011001101 1101 11011101 11011101 11011101 11011101 110111011110 1110 11101110 11101110 11101110 11101110 111011101111 1111 11111111 11111111 11111111 11111111 11111111

Groupings of 4Groupings of 4--bitsbitsAllows for recode circuitry to Allows for recode circuitry to be symmetrically alignedbe symmetrically aligned

X2i+1X2i X2i-1 Sign One Two Operation0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0 0

0 1 0

0 1 0

0 0 1

1 0 1

1 1 0

1 1 0

1 0 0

+0Y

+1Y

+1Y

+2Y

-2Y

-1Y

-1Y

-0Y

Recode Results

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Modified Booth MultiplierModified Booth Multiplier

r

pp

A0

A1

A2

A3

A4

A5

A6A7

r

pp pp pp pp

pp pp pp pp pp

r

pp pp pp pp pp

r

pp pp pp pp pp

3,0 3,1 3,2 3,3

2,0 2,1 2,2 2,3

1,0 1,1 1,2 1,3

0,0 0,1 0,2 0,3

B0 B1 B2 B3

00 00

00000000

00010001

00100010

11111111

00000000

1

00000

0

0 0

0 0

0 0

0 0

0

0 0 00 0

00010001

1

1

0

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Modified Booth MultiplierModified Booth Multiplierr

pp

A0

A1

A2

A3

A4

A5

A6A7

r

pp pp pp pp

pp pp pp pp pp

rpp pp pp pp pp

rpp pp pp pp pp

3,0 3,1 3,2 3,3

2,0 2,1 2,2 2,3

1,0 1,1 1,2 1,3

0,0 0,1 0,2 0,3

B0 B1 B2 B300 0100010001

00000

1

0 0

0 0

0 0

0 0

0

1 0 00 0

0000000001

00000

00001

000000010001

2/7/07 22

Booth Multiplier Booth Multiplier TestTest AlgorithmAlgorithmTried two algorithmsTried two algorithms

256 vectors total for 4256 vectors total for 4--bit groupingbit grouping88--bit counterbit counter

64 vectors total for 364 vectors total for 3--bit groupingbit grouping66--bit counterbit counter

18x1818x18--bit array multiplier resultsbit array multiplier results≈≈ 99.99%99.99%1 undetected fault1 undetected fault

Booth multiplier resultsBooth multiplier results≈≈ 70%70% with carrywith carry--looklook--ahead implementationahead implementation≈≈ 90%90% with carrywith carry--save implementationsave implementation≈≈ 90%90% with ripplewith ripple--carry implementationcarry implementation

Undetected faults primarily in recode circuitryUndetected faults primarily in recode circuitryBooth multiplier models may have had bugsBooth multiplier models may have had bugs

Booth multiplier test vectors do test Array multiplier Booth multiplier test vectors do test Array multiplier

2/7/07 23

Planned TPG DevelopmentPlanned TPG DevelopmentContinue debugging gateContinue debugging gate--level multiplierlevel multiplierIncorporate multiplier into the DSP model Incorporate multiplier into the DSP model Validate and debug gateValidate and debug gate--level DSP design level DSP design by comparing to VHDL/by comparing to VHDL/VerilogVerilog simulation simulation resultsresultsSimilar TPG development for 3Similar TPG development for 3--input input adder/adder/subtractorsubtractor in DSPin DSPAdditional test patterns for remaining logic Additional test patterns for remaining logic in DSPin DSP

If not tested by multiplier and adder/If not tested by multiplier and adder/subtractorsubtractortest algorithmstest algorithms

2/7/07 24

SummarySummaryCompared previously proposed test algorithms Compared previously proposed test algorithms forfor

Array multipliers Array multipliers -- small vector setsmall vector setModified Booth multiplier Modified Booth multiplier -- larger but reasonable larger but reasonable vector setvector set

Array multiplier test vectors do poor job of Array multiplier test vectors do poor job of testing Booth multipliertesting Booth multiplierBooth multiplier test vectors do good job of Booth multiplier test vectors do good job of testing multiplierstesting multipliers

Independent of implementationIndependent of implementation

Similar approach should feasible for Similar approach should feasible for development of TPG for 48development of TPG for 48--bit adder/bit adder/subtractorsubtractor