OMAP-L138 Applications ProcessorSystem

Reference Guide

Literature Number: SPRUGM7D

April 2010

2 SPRUGM7D–April 2010

Copyright © 2010, Texas Instruments Incorporated

Contents

Preface ...................................................................................................................................... 191 Overview .......................................................................................................................... 21

1.1 Introduction ................................................................................................................. 221.2 Block Diagram ............................................................................................................. 221.3 DSP Subsystem ........................................................................................................... 221.4 ARM Subsystem ........................................................................................................... 22

2 ARM Subsystem ................................................................................................................ 232.1 Introduction ................................................................................................................. 242.2 Operating States/Modes .................................................................................................. 252.3 Processor Status Registers .............................................................................................. 252.4 Exceptions and Exception Vectors ...................................................................................... 262.5 The 16-BIS/32-BIS Concept ............................................................................................. 272.6 16-BIS/32-BIS Advantages ............................................................................................... 272.7 Co-Processor 15 (CP15) ................................................................................................. 28

2.7.1 Addresses in an ARM926EJ-S System ........................................................................ 282.7.2 Memory Management Unit ...................................................................................... 282.7.3 Caches and Write Buffer ........................................................................................ 29

3 DSP Subsystem ................................................................................................................ 313.1 Introduction ................................................................................................................. 323.2 TMS320C674x Megamodule ............................................................................................. 33

3.2.1 Internal Memory Controllers ..................................................................................... 333.2.2 Internal Peripherals ............................................................................................... 33

3.3 Memory Map ............................................................................................................... 383.3.1 DSP Internal Memory ............................................................................................ 383.3.2 External Memory .................................................................................................. 38

3.4 Advanced Event Triggering (AET) ...................................................................................... 384 System Interconnect .......................................................................................................... 39

4.1 Introduction ................................................................................................................. 404.2 System Interconnect Block Diagram .................................................................................... 41

5 System Memory ................................................................................................................ 435.1 Introduction ................................................................................................................. 445.2 ARM Memories ............................................................................................................ 445.3 DSP Memories ............................................................................................................. 445.4 Shared RAM Memory ..................................................................................................... 445.5 External Memories ........................................................................................................ 445.6 Internal Peripherals ........................................................................................................ 455.7 Peripherals ................................................................................................................. 45

6 Memory Protection Unit (MPU) ............................................................................................ 476.1 Introduction ................................................................................................................. 48

6.1.1 Purpose of the MPU ............................................................................................. 486.1.2 Features ........................................................................................................... 486.1.3 Block Diagram .................................................................................................... 486.1.4 MPU Default Configuration ...................................................................................... 49

6.2 Architecture ................................................................................................................. 49

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6.2.1 Privilege Levels ................................................................................................... 496.2.2 Memory Protection Ranges ..................................................................................... 506.2.3 Permission Structures ............................................................................................ 506.2.4 Protection Check ................................................................................................. 526.2.5 DSP L1/L2 Cache Controller Accesses ....................................................................... 526.2.6 MPU Register Protection ........................................................................................ 526.2.7 Invalid Accesses and Exceptions .............................................................................. 536.2.8 Reset Considerations ............................................................................................ 536.2.9 Interrupt Support .................................................................................................. 536.2.10 Emulation Considerations ...................................................................................... 53

6.3 MPU Registers ............................................................................................................. 546.3.1 Revision Identification Register (REVID) ...................................................................... 566.3.2 Configuration Register (CONFIG) .............................................................................. 566.3.3 Interrupt Raw Status/Set Register (IRAWSTAT) ............................................................. 576.3.4 Interrupt Enable Status/Clear Register (IENSTAT) .......................................................... 586.3.5 Interrupt Enable Set Register (IENSET) ....................................................................... 596.3.6 Interrupt Enable Clear Register (IENCLR) .................................................................... 596.3.7 Fixed Range Start Address Register (FXD_MPSAR) ....................................................... 606.3.8 Fixed Range End Address Register (FXD_MPEAR) ........................................................ 606.3.9 Fixed Range Memory Protection Page Attributes Register (FXD_MPPA) ................................ 616.3.10 Programmable Range n Start Address Registers (PROGn_MPSAR) .................................... 626.3.11 Programmable Range n End Address Registers (PROGn_MPEAR) .................................... 636.3.12 Programmable Range n Memory Protection Page Attributes Register (PROGn_MPPA) ............. 646.3.13 Fault Address Register (FLTADDRR) ........................................................................ 656.3.14 Fault Status Register (FLTSTAT) ............................................................................. 666.3.15 Fault Clear Register (FLTCLR) ................................................................................ 67

7 Device Clocking ................................................................................................................ 697.1 Overview .................................................................................................................... 707.2 Frequency Flexibility ...................................................................................................... 727.3 Peripheral Clocking ........................................................................................................ 73

7.3.1 USB Clocking ..................................................................................................... 737.3.2 DDR2/mDDR Memory Controller Clocking .................................................................... 757.3.3 EMIFA Clocking ................................................................................................... 777.3.4 EMAC Clocking ................................................................................................... 787.3.5 uPP Clocking ...................................................................................................... 807.3.6 McASP Clocking .................................................................................................. 817.3.7 I/O Domains ....................................................................................................... 82

8 Phase-Locked Loop Controller (PLLC) ................................................................................. 838.1 Introduction ................................................................................................................. 848.2 PLL Controllers ............................................................................................................ 84

8.2.1 Device Clock Generation ........................................................................................ 868.2.2 Steps for Programming the PLLs ............................................................................... 87

8.3 PLLC Registers ............................................................................................................ 898.3.1 PLLC0 Revision Identification Register (REVID) ............................................................. 908.3.2 PLLC1 Revision Identification Register (REVID) ............................................................. 918.3.3 Reset Type Status Register (RSTYPE) ....................................................................... 918.3.4 PLLC0 Control Register (PLLCTL) ............................................................................. 928.3.5 PLLC1 Control Register (PLLCTL) ............................................................................. 938.3.6 PLLC0 OBSCLK Select Register (OCSEL) ................................................................... 948.3.7 PLLC1 OBSCLK Select Register (OCSEL) ................................................................... 958.3.8 PLL Multiplier Control Register (PLLM) ........................................................................ 968.3.9 PLLC0 Pre-Divider Control Register (PREDIV) .............................................................. 968.3.10 PLLC0 Divider 1 Register (PLLDIV1) ......................................................................... 97

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8.3.11 PLLC1 Divider 1 Register (PLLDIV1) ......................................................................... 978.3.12 PLLC0 Divider 2 Register (PLLDIV2) ......................................................................... 988.3.13 PLLC1 Divider 2 Register (PLLDIV2) ......................................................................... 988.3.14 PLLC0 Divider 3 Register (PLLDIV3) ......................................................................... 998.3.15 PLLC1 Divider 3 Register (PLLDIV3) ......................................................................... 998.3.16 PLLC0 Divider 4 Register (PLLDIV4) ....................................................................... 1008.3.17 PLLC0 Divider 5 Register (PLLDIV5) ....................................................................... 1008.3.18 PLLC0 Divider 6 Register (PLLDIV6) ....................................................................... 1018.3.19 PLLC0 Divider 7 Register (PLLDIV7) ....................................................................... 1018.3.20 PLLC0 Oscillator Divider 1 Register (OSCDIV) ............................................................ 1028.3.21 PLLC1 Oscillator Divider 1 Register (OSCDIV) ............................................................ 1028.3.22 PLL Post-Divider Control Register (POSTDIV) ............................................................ 1038.3.23 PLL Controller Command Register (PLLCMD) ............................................................ 1038.3.24 PLL Controller Status Register (PLLSTAT) ................................................................ 1048.3.25 PLLC0 Clock Align Control Register (ALNCTL) ........................................................... 1058.3.26 PLLC1 Clock Align Control Register (ALNCTL) ........................................................... 1068.3.27 PLLC0 PLLDIV Ratio Change Status Register (DCHANGE) ............................................ 1078.3.28 PLLC1 PLLDIV Ratio Change Status Register (DCHANGE) ............................................ 1088.3.29 PLLC0 Clock Enable Control Register (CKEN) ............................................................ 1098.3.30 PLLC0 Clock Status Register (CKSTAT) ................................................................... 1108.3.31 PLLC0 SYSCLK Status Register (SYSTAT) ............................................................... 1118.3.32 PLLC1 SYSCLK Status Register (SYSTAT) ............................................................... 1128.3.33 Emulation Performance Counter 0 Register (EMUCNT0) ................................................ 1138.3.34 Emulation Performance Counter 1 Register (EMUCNT1) ................................................ 113

9 Power and Sleep Controller (PSC) ..................................................................................... 1159.1 Introduction ............................................................................................................... 1169.2 Power Domain and Module Topology ................................................................................. 116

9.2.1 Power Domain States .......................................................................................... 1189.2.2 Module States ................................................................................................... 118

9.3 Executing State Transitions ............................................................................................ 1209.3.1 Power Domain State Transitions .............................................................................. 1209.3.2 Module State Transitions ....................................................................................... 120

9.4 IcePick Emulation Support in the PSC ................................................................................ 1219.5 PSC Interrupts ............................................................................................................ 121

9.5.1 Interrupt Events ................................................................................................. 1219.5.2 Interrupt Registers .............................................................................................. 1229.5.3 Interrupt Handling ............................................................................................... 123

9.6 PSC Registers ............................................................................................................ 1249.6.1 Revision Identification Register (REVID) .................................................................... 1259.6.2 Interrupt Evaluation Register (INTEVAL) .................................................................... 1259.6.3 PSC0 Module Error Pending Register 0 (modules 0-15) (MERRPR0) .................................. 1269.6.4 PSC1 Module Error Pending Register 0 (modules 0-31) (MERRPR0) .................................. 1269.6.5 PSC0 Module Error Clear Register 0 (modules 0-15) (MERRCR0) ...................................... 1279.6.6 PSC1 Module Error Clear Register 0 (modules 0-31) (MERRCR0) ...................................... 1279.6.7 Power Error Pending Register (PERRPR) ................................................................... 1289.6.8 Power Error Clear Register (PERRCR) ...................................................................... 1289.6.9 Power Domain Transition Command Register (PTCMD) .................................................. 1299.6.10 Power Domain Transition Status Register (PTSTAT) ..................................................... 1309.6.11 Power Domain 0 Status Register (PDSTAT0) ............................................................. 1319.6.12 Power Domain 1 Status Register (PDSTAT1) ............................................................. 1329.6.13 Power Domain 0 Control Register (PDCTL0) .............................................................. 1339.6.14 Power Domain 1 Control Register (PDCTL1) .............................................................. 1349.6.15 Power Domain 0 Configuration Register (PDCFG0) ...................................................... 135

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9.6.16 Power Domain 1 Configuration Register (PDCFG1) ...................................................... 1369.6.17 Module Status n Register (MDSTATn) ...................................................................... 1379.6.18 PSC0 Module Control n Register (modules 0-15) (MDCTLn) ............................................ 1389.6.19 PSC1 Module Control n Register (modules 0-31) (MDCTLn) ............................................ 139

10 Power Management .......................................................................................................... 14110.1 Introduction ............................................................................................................... 14210.2 Power Consumption Overview ......................................................................................... 14210.3 PSC and PLLC Overview ............................................................................................... 14210.4 Features ................................................................................................................... 14310.5 Clock Management ...................................................................................................... 144

10.5.1 Module Clock ON/OFF ........................................................................................ 14410.5.2 Module Clock Frequency Scaling ............................................................................ 14410.5.3 PLL Bypass and Power Down ............................................................................... 145

10.6 ARM Sleep Mode Management ........................................................................................ 14510.6.1 ARM Wait-For-Interrupt Sleep Mode ........................................................................ 14510.6.2 ARM Clock OFF ................................................................................................ 14610.6.3 ARM Subsystem Clock ON ................................................................................... 147

10.7 DSP Sleep Mode Management ........................................................................................ 14810.7.1 DSP Sleep Modes ............................................................................................. 14810.7.2 C674x DSP CPU Sleep Mode ............................................................................... 14810.7.3 C674x Megamodule Sleep Mode ............................................................................ 14810.7.4 C674x Megamodule Clock ON/OFF ......................................................................... 148

10.8 RTC-Only Mode .......................................................................................................... 15010.9 Dynamic Voltage and Frequency Scaling (DVFS) ................................................................... 151

10.9.1 Frequency Scaling Considerations .......................................................................... 15110.9.2 Voltage Scaling Considerations .............................................................................. 152

10.10 Deep Sleep Mode ....................................................................................................... 15210.10.1 Entering/Exiting Deep Sleep Mode Using Externally Controlled Wake-Up ........................... 15210.10.2 Entering/Exiting Deep Sleep Mode Using RTC Controlled Wake-Up ................................. 15310.10.3 Deep Sleep Sequence ....................................................................................... 15410.10.4 Entering/Exiting Deep Sleep Mode Using Software Handshaking ..................................... 154

10.11 Additional Peripheral Power Management Considerations ........................................................ 15510.11.1 USB PHY Power Down Control ............................................................................ 15510.11.2 DDR2/mDDR Memory Controller Clock Gating and Self-Refresh Mode .............................. 15510.11.3 SATA PHY Power Down .................................................................................... 15610.11.4 LVCMOS I/O Buffer Receiver Disable ..................................................................... 15610.11.5 Pull-Up/Pull-Down Disable .................................................................................. 156

11 System Configuration (SYSCFG) Module ............................................................................ 15711.1 Introduction ............................................................................................................... 15811.2 Protection ................................................................................................................. 158

11.2.1 Privilege Mode Protection ..................................................................................... 15811.2.2 Kicker Mechanism Protection ................................................................................ 159

11.3 Master Priority Control ................................................................................................... 15911.4 ARM-DSP Communication Interrupts ................................................................................. 16111.5 SYSCFG Registers ...................................................................................................... 161

11.5.1 Revision Identification Register (REVID) ................................................................... 16311.5.2 Device Identification Register 0 (DEVIDR0) ................................................................ 16311.5.3 Boot Configuration Register (BOOTCFG) .................................................................. 16411.5.4 Kick Registers (KICK0R-KICK1R) ........................................................................... 16511.5.5 Host 0 Configuration Register (HOST0CFG) ............................................................... 16611.5.6 Host 1 Configuration Register (HOST1CFG) ............................................................... 16711.5.7 Interrupt Registers ............................................................................................. 16811.5.8 Fault Registers ................................................................................................. 171

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11.5.9 Master Priority Registers (MSTPRI0-MSTPRI2) ........................................................... 17311.5.10 Pin Multiplexing Control Registers (PINMUX0-PINMUX19) ............................................ 17611.5.11 Suspend Source Register (SUSPSRC) ................................................................... 21611.5.12 Chip Signal Register (CHIPSIG) ........................................................................... 21911.5.13 Chip Signal Clear Register (CHIPSIG_CLR) ............................................................. 22011.5.14 Chip Configuration 0 Register (CFGCHIP0) .............................................................. 22111.5.15 Chip Configuration 1 Register (CFGCHIP1) .............................................................. 22211.5.16 Chip Configuration 2 Register (CFGCHIP2) .............................................................. 22511.5.17 Chip Configuration 3 Register (CFGCHIP3) .............................................................. 22711.5.18 Chip Configuration 4 Register (CFGCHIP4) .............................................................. 22811.5.19 VTP I/O Control Register (VTPIO_CTL) ................................................................... 22911.5.20 DDR Slew Register (DDR_SLEW) ......................................................................... 23111.5.21 Deep Sleep Register (DEEPSLEEP) ...................................................................... 23211.5.22 Pullup/Pulldown Enable Register (PUPD_ENA) ......................................................... 23311.5.23 Pullup/Pulldown Select Register (PUPD_SEL) ........................................................... 23311.5.24 RXACTIVE Control Register (RXACTIVE) ................................................................ 23511.5.25 Power Down Control Register (PWRDN) ................................................................. 235

12 ARM Interrupt Controller (AINTC) ....................................................................................... 23712.1 Introduction ............................................................................................................... 23812.2 Interrupt Mapping ........................................................................................................ 23812.3 AINTC Methodology ..................................................................................................... 241

12.3.1 Interrupt Processing ........................................................................................... 24112.3.2 Interrupt Enabling .............................................................................................. 24212.3.3 Interrupt Status Checking ..................................................................................... 24212.3.4 Interrupt Channel Mapping ................................................................................... 24212.3.5 Host Interrupt Mapping Interrupts ............................................................................ 24212.3.6 Interrupt Prioritization .......................................................................................... 24312.3.7 Interrupt Nesting ............................................................................................... 24312.3.8 Interrupt Vectorization ......................................................................................... 24412.3.9 Interrupt Status Clearing ...................................................................................... 24512.3.10 Interrupt Disabling ............................................................................................ 245

12.4 AINTC Registers ......................................................................................................... 24512.4.1 Revision Identification Register (REVID) ................................................................... 24612.4.2 Control Register (CR) ......................................................................................... 24712.4.3 Global Enable Register (GER) ............................................................................... 24812.4.4 Global Nesting Level Register (GNLR) ..................................................................... 24812.4.5 System Interrupt Status Indexed Set Register (SISR) .................................................... 24912.4.6 System Interrupt Status Indexed Clear Register (SICR) .................................................. 24912.4.7 System Interrupt Enable Indexed Set Register (EISR) ................................................... 25012.4.8 System Interrupt Enable Indexed Clear Register (EICR) ................................................. 25012.4.9 Host Interrupt Enable Indexed Set Register (HIEISR) .................................................... 25112.4.10 Host Interrupt Enable Indexed Clear Register (HIEICR) ................................................ 25112.4.11 Vector Base Register (VBR) ................................................................................ 25212.4.12 Vector Size Register (VSR) ................................................................................. 25212.4.13 Vector Null Register (VNR) ................................................................................. 25312.4.14 Global Prioritized Index Register (GPIR) .................................................................. 25312.4.15 Global Prioritized Vector Register (GPVR) ................................................................ 25412.4.16 System Interrupt Status Raw/Set Register 1 (SRSR1) .................................................. 25412.4.17 System Interrupt Status Raw/Set Register 2 (SRSR2) .................................................. 25512.4.18 System Interrupt Status Raw/Set Register 3 (SRSR3) .................................................. 25512.4.19 System Interrupt Status Raw/Set Register 4 (SRSR4) .................................................. 25612.4.20 System Interrupt Status Enabled/Clear Register 1 (SECR1) ........................................... 25612.4.21 System Interrupt Status Enabled/Clear Register 2 (SECR2) ........................................... 257

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12.4.22 System Interrupt Status Enabled/Clear Register 3 (SECR3) ........................................... 25712.4.23 System Interrupt Status Enabled/Clear Register 4 (SECR4) ........................................... 25812.4.24 System Interrupt Enable Set Register 1 (ESR1) ......................................................... 25812.4.25 System Interrupt Enable Set Register 2 (ESR2) ......................................................... 25912.4.26 System Interrupt Enable Set Register 3 (ESR3) ......................................................... 25912.4.27 System Interrupt Enable Set Register 4 (ESR4) ......................................................... 26012.4.28 System Interrupt Enable Clear Register 1 (ECR1) ....................................................... 26012.4.29 System Interrupt Enable Clear Register 2 (ECR2) ....................................................... 26112.4.30 System Interrupt Enable Clear Register 3 (ECR3) ....................................................... 26112.4.31 System Interrupt Enable Clear Register 4 (ECR4) ....................................................... 26212.4.32 Channel Map Registers (CMR0-CMR25) ................................................................. 26212.4.33 Host Interrupt Prioritized Index Register 1 (HIPIR1) ..................................................... 26312.4.34 Host Interrupt Prioritized Index Register 2 (HIPIR2) ..................................................... 26312.4.35 Host Interrupt Nesting Level Register 1 (HINLR1) ....................................................... 26412.4.36 Host Interrupt Nesting Level Register 2 (HINLR2) ....................................................... 26412.4.37 Host Interrupt Enable Register (HIER) .................................................................... 26512.4.38 Host Interrupt Prioritized Vector Register 1 (HIPVR1) ................................................... 26612.4.39 Host Interrupt Prioritized Vector Register 2 (HIPVR2) ................................................... 266

13 Boot Considerations ........................................................................................................ 26713.1 Introduction ............................................................................................................... 26813.2 DSP Wake Up ............................................................................................................ 269

A Revision History .............................................................................................................. 271

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List of Figures

1-1. OMAP-L138 Applications Processor Block Diagram ................................................................. 223-1. TMS320C674x Megamodule Block Diagram .......................................................................... 324-1. System Interconnect Block Diagram .................................................................................... 416-1. MPU Block Diagram....................................................................................................... 486-2. Revision ID Register (REVID) ........................................................................................... 566-3. Configuration Register (CONFIG) ....................................................................................... 566-4. Interrupt Raw Status/Set Register (IRAWSTAT) ...................................................................... 576-5. Interrupt Enable Status/Clear Register (IENSTAT) ................................................................... 586-6. Interrupt Enable Set Register (IENSET)................................................................................ 596-7. Interrupt Enable Clear Register (IENCLR) ............................................................................. 596-8. Fixed Range Start Address Register (FXD_MPSAR) ................................................................ 606-9. Fixed Range End Address Register (FXD_MPEAR) ................................................................. 606-10. Fixed Range Memory Protection Page Attributes Register (FXD_MPPA)......................................... 616-11. MPU1 Programmable Range n Start Address Register (PROGn_MPSAR)....................................... 626-12. MPU2 Programmable Range n Start Address Register (PROGn_MPSAR)....................................... 626-13. MPU1 Programmable Range n End Address Register (PROGn_MPEAR)........................................ 636-14. MPU2 Programmable Range n End Address Register (PROGn_MPEAR)........................................ 636-15. Programmable Range Memory Protection Page Attributes Register (PROGn_MPPA).......................... 646-16. Fault Address Register (FLTADDRR) .................................................................................. 656-17. Fault Status Register (FLTSTAT) ....................................................................................... 666-18. Fault Clear Register (FLTCLR) .......................................................................................... 677-1. Overall Clocking Diagram ................................................................................................ 717-2. USB Clocking Diagram ................................................................................................... 747-3. DDR2/mDDR Memory Controller Clocking Diagram.................................................................. 767-4. EMIFA Clocking Diagram................................................................................................. 777-5. EMAC Clocking Diagram ................................................................................................. 787-6. uPP Clocking Diagram.................................................................................................... 807-7. McASP Clocking Diagram................................................................................................ 818-1. PLLC Structure ............................................................................................................ 858-2. PLLC0 Revision Identification Register (REVID) ...................................................................... 908-3. PLLC1 Revision Identification Register (REVID) ...................................................................... 918-4. Reset Type Status Register (RSTYPE) ................................................................................ 918-5. PLLC0 Control Register (PLLCTL) ...................................................................................... 928-6. PLLC1 Control Register (PLLCTL) ...................................................................................... 938-7. PLLC0 OBSCLK Select Register (OCSEL) ............................................................................ 948-8. PLLC1 OBSCLK Select Register (OCSEL) ............................................................................ 958-9. PLL Multiplier Control Register (PLLM)................................................................................. 968-10. PLLC0 Pre-Divider Control Register (PREDIV) ....................................................................... 968-11. PLLC0 Divider 1 Register (PLLDIV1) ................................................................................... 978-12. PLLC1 Divider 1 Register (PLLDIV1) ................................................................................... 978-13. PLLC0 Divider 2 Register (PLLDIV2) .................................................................................. 988-14. PLLC1 Divider 2 Register (PLLDIV2) .................................................................................. 988-15. PLLC0 Divider 3 Register (PLLDIV3) .................................................................................. 998-16. PLLC1 Divider 3 Register (PLLDIV3) .................................................................................. 998-17. PLLC0 Divider 4 Register (PLLDIV4) ................................................................................. 1008-18. PLLC0 Divider 5 Register (PLLDIV5) ................................................................................. 1008-19. PLLC0 Divider 6 Register (PLLDIV6) ................................................................................. 101

9SPRUGM7D–April 2010 List of Figures

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8-20. PLLC0 Divider 7 Register (PLLDIV7) ................................................................................. 1018-21. PLLC0 Oscillator Divider 1 Register (OSCDIV) ...................................................................... 1028-22. PLLC1 Oscillator Divider 1 Register (OSCDIV) ...................................................................... 1028-23. PLL Post-Divider Control Register (POSTDIV) ...................................................................... 1038-24. PLL Controller Command Register (PLLCMD)....................................................................... 1038-25. PLL Controller Status Register (PLLSTAT)........................................................................... 1048-26. PLLC0 Clock Align Control Register (ALNCTL)...................................................................... 1058-27. PLLC1 Clock Align Control Register (ALNCTL)...................................................................... 1068-28. PLLC0 PLLDIV Ratio Change Status Register (DCHANGE) ...................................................... 1078-29. PLLC1 PLLDIV Ratio Change Status Register (DCHANGE) ...................................................... 1088-30. PLLC0 Clock Enable Control Register (CKEN) ...................................................................... 1098-31. PLLC0 Clock Status Register (CKSTAT) ............................................................................. 1108-32. PLLC0 SYSCLK Status Register (SYSTAT) ......................................................................... 1118-33. PLLC1 SYSCLK Status Register (SYSTAT) ......................................................................... 1128-34. Emulation Performance Counter 0 Register (EMUCNT0) .......................................................... 1138-35. Emulation Performance Counter 1 Register (EMUCNT1) .......................................................... 1139-1. Revision Identification Register (REVID) ............................................................................. 1259-2. Interrupt Evaluation Register (INTEVAL) ............................................................................. 1259-3. PSC0 Module Error Pending Register 0 (MERRPR0) .............................................................. 1269-4. PSC1 Module Error Pending Register 0 (MERRPR0) .............................................................. 1269-5. PSC0 Module Error Clear Register 0 (MERRCR0).................................................................. 1279-6. PSC1 Module Error Clear Register 0 (MERRCR0).................................................................. 1279-7. Power Error Pending Register (PERRPR)............................................................................ 1289-8. Power Error Clear Register (PERRCR) ............................................................................... 1289-9. Power Domain Transition Command Register (PTCMD)........................................................... 1299-10. Power Domain Transition Status Register (PTSTAT)............................................................... 1309-11. Power Domain 0 Status Register (PDSTAT0) ....................................................................... 1319-12. Power Domain 1 Status Register (PDSTAT1) ....................................................................... 1329-13. Power Domain 0 Control Register (PDCTL0) ........................................................................ 1339-14. Power Domain 1 Control Register (PDCTL1) ........................................................................ 1349-15. Power Domain 0 Configuration Register (PDCFG0) ................................................................ 1359-16. Power Domain 1 Configuration Register (PDCFG1) ................................................................ 1369-17. Module Status n Register (MDSTATn)................................................................................ 1379-18. PSC0 Module Control n Register (MDCTLn)......................................................................... 1389-19. PSC1 Module Control n Register (MDCTLn)......................................................................... 13910-1. Deep Sleep Mode Sequence........................................................................................... 15411-1. Revision Identification Register (REVID) ............................................................................. 16311-2. Device Identification Register 0 (DEVIDR0).......................................................................... 16311-3. Boot Configuration Register (BOOTCFG) ............................................................................ 16411-4. Kick 0 Register (KICK0R) ............................................................................................... 16511-5. Kick 1 Register (KICK1R) ............................................................................................... 16511-6. Host 0 Configuration Register (HOST0CFG)......................................................................... 16611-7. Host 1 Configuration Register (HOST1CFG)......................................................................... 16711-8. Interrupt Raw Status/Set Register (IRAWSTAT)..................................................................... 16811-9. Interrupt Enable Status/Clear Register (IENSTAT).................................................................. 16911-10. Interrupt Enable Register (IENSET) ................................................................................... 17011-11. Interrupt Enable Clear Register (IENCLR)............................................................................ 17011-12. End of Interrupt Register (EOI)......................................................................................... 17111-13. Fault Address Register (FLTADDRR) ................................................................................. 171

10 List of Figures SPRUGM7D–April 2010

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11-14. Fault Status Register (FLTSTAT) ...................................................................................... 17211-15. Master Priority 0 Register (MSTPRI0)................................................................................. 17311-16. Master Priority 1 Register (MSTPRI1)................................................................................. 17411-17. Master Priority 2 Register (MSTPRI2)................................................................................. 17511-18. Pin Multiplexing Control 0 Register (PINMUX0) ..................................................................... 17611-19. Pin Multiplexing Control 1 Register (PINMUX1) ..................................................................... 17811-20. Pin Multiplexing Control 2 Register (PINMUX2) ..................................................................... 18011-21. Pin Multiplexing Control 3 Register (PINMUX3) ..................................................................... 18211-22. Pin Multiplexing Control 4 Register (PINMUX4) ..................................................................... 18411-23. Pin Multiplexing Control 5 Register (PINMUX5) ..................................................................... 18611-24. Pin Multiplexing Control 6 Register (PINMUX6) ..................................................................... 18811-25. Pin Multiplexing Control 7 Register (PINMUX7) ..................................................................... 19011-26. Pin Multiplexing Control 8 Register (PINMUX8) ..................................................................... 19211-27. Pin Multiplexing Control 9 Register (PINMUX9) ..................................................................... 19411-28. Pin Multiplexing Control 10 Register (PINMUX10) .................................................................. 19611-29. Pin Multiplexing Control 11 Register (PINMUX11) .................................................................. 19811-30. Pin Multiplexing Control 12 Register (PINMUX12) .................................................................. 20011-31. Pin Multiplexing Control 13 Register (PINMUX13) .................................................................. 20211-32. Pin Multiplexing Control 14 Register (PINMUX14) .................................................................. 20411-33. Pin Multiplexing Control 15 Register (PINMUX15) .................................................................. 20611-34. Pin Multiplexing Control 16 Register (PINMUX16) .................................................................. 20811-35. Pin Multiplexing Control 17 Register (PINMUX17) .................................................................. 21011-36. Pin Multiplexing Control 18 Register (PINMUX18) .................................................................. 21211-37. Pin Multiplexing Control 19 Register (PINMUX19) .................................................................. 21411-38. Suspend Source Register (SUSPSRC) ............................................................................... 21611-39. Chip Signal Register (CHIPSIG) ....................................................................................... 21911-40. Chip Signal Clear Register (CHIPSIG_CLR) ......................................................................... 22011-41. Chip Configuration 0 Register (CFGCHIP0).......................................................................... 22111-42. Chip Configuration 1 Register (CFGCHIP1).......................................................................... 22211-43. Chip Configuration 2 Register (CFGCHIP2).......................................................................... 22511-44. Chip Configuration 3 Register (CFGCHIP3).......................................................................... 22711-45. Chip Configuration 4 Register (CFGCHIP4).......................................................................... 22811-46. VTP I/O Control Register (VTPIO_CTL) .............................................................................. 22911-47. DDR Slew Register (DDR_SLEW)..................................................................................... 23111-48. Deep Sleep Register (DEEPSLEEP).................................................................................. 23211-49. Pullup/Pulldown Enable Register (PUPD_ENA) ..................................................................... 23311-50. Pullup/Pulldown Select Register (PUPD_SEL) ...................................................................... 23311-51. RXACTIVE Control Register (RXACTIVE)............................................................................ 23511-52. Power Down Control Register (PWRDN) ............................................................................. 23512-1. AINTC Interrupt Mapping ............................................................................................... 23812-2. Flow of System Interrupts to Host ..................................................................................... 24112-3. Revision Identification Register (REVID) ............................................................................. 24612-4. Control Register (CR) ................................................................................................... 24712-5. Global Enable Register (GER) ......................................................................................... 24812-6. Global Nesting Level Register (GNLR) ............................................................................... 24812-7. System Interrupt Status Indexed Set Register (SISR) .............................................................. 24912-8. System Interrupt Status Indexed Clear Register (SICR)............................................................ 24912-9. System Interrupt Enable Indexed Set Register (EISR) ............................................................. 25012-10. System Interrupt Enable Indexed Clear Register (EICR) ........................................................... 250

11SPRUGM7D–April 2010 List of Figures

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12-11. Host Interrupt Enable Indexed Set Register (HEISR) ............................................................... 25112-12. Host Interrupt Enable Indexed Clear Register (HIEICR)............................................................ 25112-13. Vector Base Register (VBR)............................................................................................ 25212-14. Vector Size Register (VSR)............................................................................................. 25212-15. Vector Null Register (VNR) ............................................................................................. 25312-16. Global Prioritized Index Register (GPIR) ............................................................................. 25312-17. Global Prioritized Vector Register (GPVR) ........................................................................... 25412-18. System Interrupt Status Raw/Set Register 1 (SRSR1) ............................................................. 25412-19. System Interrupt Status Raw/Set Register 2 (SRSR2) ............................................................. 25512-20. System Interrupt Status Raw/Set Register 3 (SRSR3) ............................................................. 25512-21. System Interrupt Status Raw/Set Register 4 (SRSR4) ............................................................. 25612-22. System Interrupt Status Enabled/Clear Register 1 (SECR1) ...................................................... 25612-23. System Interrupt Status Enabled/Clear Register 2 (SECR2) ...................................................... 25712-24. System Interrupt Status Enabled/Clear Register 3 (SECR3) ...................................................... 25712-25. System Interrupt Status Enabled/Clear Register 4 (SECR4) ...................................................... 25812-26. System Interrupt Enable Set Register 1 (ESR1)..................................................................... 25812-27. System Interrupt Enable Set Register 2 (ESR2)..................................................................... 25912-28. System Interrupt Enable Set Register 3 (ESR3)..................................................................... 25912-29. System Interrupt Enable Set Register 4 (ESR4)..................................................................... 26012-30. System Interrupt Enable Clear Register 1 (ECR1) .................................................................. 26012-31. System Interrupt Enable Clear Register 2 (ECR2) .................................................................. 26112-32. System Interrupt Enable Clear Register 3 (ECR3) .................................................................. 26112-33. System Interrupt Enable Clear Register 4 (ECR4) .................................................................. 26212-34. Channel Map Registers (CMRn) ....................................................................................... 26212-35. Host Interrupt Prioritized Index Register 1 (HIPIR1) ................................................................ 26312-36. Host Interrupt Prioritized Index Register 2 (HIPIR2) ................................................................ 26312-37. Host Interrupt Nesting Level Register 1 (HINLR1) .................................................................. 26412-38. Host Interrupt Nesting Level Register 2 (HINLR2) .................................................................. 26412-39. Host Interrupt Enable Register (HIER) ................................................................................ 26512-40. Host Interrupt Prioritized Vector Register 1 (HIPVR1) .............................................................. 26612-41. Host Interrupt Prioritized Vector Register 2 (HIPVR2) .............................................................. 266

12 List of Figures SPRUGM7D–April 2010

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List of Tables

2-1. Exception Vector Table for ARM ........................................................................................ 262-2. Different Address Types in ARM System .............................................................................. 283-1. DSP Interrupt Map ........................................................................................................ 334-1. OMAP-L138 Applications Processor System Interconnect Matrix .................................................. 406-1. MPU Memory Regions.................................................................................................... 496-2. MPU Default Configuration............................................................................................... 496-3. Device Master Settings ................................................................................................... 496-4. Permission Fields.......................................................................................................... 506-5. Request Type Access Controls.......................................................................................... 516-6. MPU_BOOTCFG_ERR Interrupt Sources ............................................................................. 536-7. Memory Protection Unit 1 (MPU1) Registers .......................................................................... 546-8. Memory Protection Unit 2 (MPU2) Registers .......................................................................... 546-9. Revision ID Register (REVID) Field Descriptions ..................................................................... 566-10. Configuration Register (CONFIG) Field Descriptions................................................................. 566-11. Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions................................................ 576-12. Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions ............................................. 586-13. Interrupt Enable Set Register (IENSET) Field Descriptions ......................................................... 596-14. Interrupt Enable Clear Register (IENCLR) Field Descriptions....................................................... 596-15. Fixed Range Memory Protection Page Attributes Register (FXD_MPPA) Field Descriptions .................. 616-16. MPU1 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions ................ 626-17. MPU2 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions ................ 626-18. MPU1 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions ................. 636-19. MPU2 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions ................. 636-20. Programmable Range Memory Protection Page Attributes Register (PROGn_MPPA) Field Descriptions ... 646-21. Fault Address Register (FLTADDRR) Field Descriptions ............................................................ 656-22. Fault Status Register (FLTSTAT) Field Descriptions ................................................................. 666-23. Fault Clear Register (FLTCLR) Field Descriptions.................................................................... 677-1. Device Clock Inputs ....................................................................................................... 707-2. System Clock Domains ................................................................................................... 707-3. Example PLL Frequencies .............................................................................................. 737-4. USB Clock Multiplexing Options......................................................................................... 747-5. DDR2/mDDR Memory Controller MCLK Frequencies................................................................ 767-6. EMIFA Frequencies ....................................................................................................... 777-7. EMAC Reference Clock Frequencies................................................................................... 797-8. uPP Transmit Clock Selection ........................................................................................... 807-9. Peripherals ................................................................................................................. 828-1. System PLLC Output Clocks............................................................................................. 868-2. PLL Controller 0 (PLLC0) Registers .................................................................................... 898-3. PLL Controller 1 (PLLC1) Registers .................................................................................... 908-4. PLLC0 Revision Identification Register (REVID) Field Descriptions................................................ 908-5. PLLC1 Revision Identification Register (REVID) Field Descriptions................................................ 918-6. Reset Type Status Register (RSTYPE) Field Descriptions .......................................................... 918-7. PLLC0 Control Register (PLLCTL) Field Descriptions................................................................ 928-8. PLLC1 Control Register (PLLCTL) Field Descriptions................................................................ 938-9. PLLC0 OBSCLK Select Register (OCSEL) Field Descriptions...................................................... 948-10. PLLC1 OBSCLK Select Register (OCSEL) Field Descriptions...................................................... 958-11. PLL Multiplier Control Register (PLLM) Field Descriptions .......................................................... 96

13SPRUGM7D–April 2010 List of Tables

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8-12. PLLC0 Pre-Divider Control Register (PREDIV) Field Descriptions ................................................. 968-13. PLLC0 Divider 1 Register (PLLDIV1) Field Descriptions............................................................. 978-14. PLLC1 Divider 1 Register (PLLDIV1) Field Descriptions............................................................. 978-15. PLLC0 Divider 2 Register (PLLDIV2) Field Descriptions............................................................. 988-16. PLLC1 Divider 2 Register (PLLDIV2) Field Descriptions............................................................. 988-17. PLLC0 Divider 3 Register (PLLDIV3) Field Descriptions............................................................. 998-18. PLLC1 Divider 3 Register (PLLDIV3) Field Descriptions............................................................. 998-19. PLLC0 Divider 4 Register (PLLDIV4) Field Descriptions ........................................................... 1008-20. PLLC0 Divider 5 Register (PLLDIV5) Field Descriptions ........................................................... 1008-21. PLLC0 Divider 6 Register (PLLDIV6) Field Descriptions ........................................................... 1018-22. PLLC0 Divider 7 Register (PLLDIV7) Field Descriptions ........................................................... 1018-23. PLLC0 Oscillator Divider 1 Register (OSCDIV) Field Descriptions................................................ 1028-24. PLLC1 Oscillator Divider 1 Register (OSCDIV) Field Descriptions................................................ 1028-25. PLL Post-Divider Control Register (POSTDIV) Field Descriptions ................................................ 1038-26. PLL Controller Command Register (PLLCMD) Field Descriptions ................................................ 1038-27. PLL Controller Status Register (PLLSTAT) Field Descriptions .................................................... 1048-28. PLLC0 Clock Align Control Register (ALNCTL) Field Descriptions ............................................... 1058-29. PLLC1 Clock Align Control Register (ALNCTL) Field Descriptions ............................................... 1068-30. PLLC0 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions ................................ 1078-31. PLLC1 PLLDIV Ratio Change Status Register (DCHANGE) Field Descriptions ................................ 1088-32. PLLC0 Clock Enable Control Register (CKEN) Field Descriptions................................................ 1098-33. PLLC0 Clock Status Register (CKSTAT) Field Descriptions....................................................... 1108-34. PLLC0 SYSCLK Status Register (SYSTAT) Field Descriptions ................................................... 1118-35. PLLC1 SYSCLK Status Register (SYSTAT) Field Descriptions ................................................... 1128-36. Emulation Performance Counter 0 Register (EMUCNT0) Field Descriptions.................................... 1138-37. Emulation Performance Counter 1 Register (EMUCNT1) Field Descriptions.................................... 1139-1. PSC0 Default Module Configuration................................................................................... 1169-2. PSC1 Default Module Configuration................................................................................... 1179-3. Module States ............................................................................................................ 1199-4. IcePick Emulation Commands ......................................................................................... 1219-5. PSC Interrupt Events .................................................................................................... 1219-6. Power and Sleep Controller 0 (PSC0) Registers .................................................................... 1249-7. Power and Sleep Controller 1 (PSC1) Registers .................................................................... 1249-8. Revision Identification Register (REVID) Field Descriptions ....................................................... 1259-9. Interrupt Evaluation Register (INTEVAL) Field Descriptions ....................................................... 1259-10. PSC0 Module Error Pending Register 0 (MERRPR0) Field Descriptions ........................................ 1269-11. PSC0 Module Error Clear Register 0 (MERRCR0) Field Descriptions ........................................... 1279-12. Power Error Pending Register (PERRPR) Field Descriptions ..................................................... 1289-13. Power Error Clear Register (PERRCR) Field Descriptions......................................................... 1289-14. Power Domain Transition Command Register (PTCMD) Field Descriptions .................................... 1299-15. Power Domain Transition Status Register (PTSTAT) Field Descriptions ........................................ 1309-16. Power Domain 0 Status Register (PDSTAT0) Field Descriptions ................................................. 1319-17. Power Domain 1 Status Register (PDSTAT1) Field Descriptions ................................................. 1329-18. Power Domain 0 Control Register (PDCTL0) Field Descriptions.................................................. 1339-19. Power Domain 1 Control Register (PDCTL1) Field Descriptions.................................................. 1349-20. Power Domain 0 Configuration Register (PDCFG0) Field Descriptions .......................................... 1359-21. Power Domain 1 Configuration Register (PDCFG1) Field Descriptions .......................................... 1369-22. Module Status n Register (MDSTATn) Field Descriptions ......................................................... 1379-23. PSC0 Module Control n Register (MDCTLn) Field Descriptions .................................................. 138

14 List of Tables SPRUGM7D–April 2010

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9-24. PSC1 Module Control n Register (MDCTLn) Field Descriptions .................................................. 13910-1. Power Management Features.......................................................................................... 14311-1. Master IDs ................................................................................................................ 15911-2. Default Master Priority................................................................................................... 16011-3. System Configuration Module 0 (SYSCFG0) Registers ............................................................ 16111-4. System Configuration Module 1 (SYSCFG1) Registers ............................................................ 16211-5. Revision Identification Register (REVID) Field Descriptions ....................................................... 16311-6. Device Identification Register 0 (DEVIDR0) Field Descriptions ................................................... 16311-7. Boot Configuration Register (BOOTCFG) Field Descriptions ...................................................... 16411-8. Kick 0 Register (KICK0R) Field Descriptions......................................................................... 16511-9. Kick 1 Register (KICK1R) Field Descriptions......................................................................... 16511-10. Host 0 Configuration Register (HOST0CFG) Field Descriptions .................................................. 16611-11. Host 1 Configuration Register (HOST1CFG) Field Descriptions .................................................. 16711-12. Interrupt Raw Status/Set Register (IRAWSTAT) Field Descriptions .............................................. 16811-13. Interrupt Enable Status/Clear Register (IENSTAT) Field Descriptions ........................................... 16911-14. Interrupt Enable Register (IENSET) Field Descriptions............................................................. 17011-15. Interrupt Enable Clear Register (IENCLR) Field Descriptions ..................................................... 17011-16. End of Interrupt Register (EOI) Field Descriptions .................................................................. 17111-17. Fault Address Register (FLTADDRR) Field Descriptions........................................................... 17111-18. Fault Status Register (FLTSTAT) Field Descriptions................................................................ 17211-19. Master Priority 0 Register (MSTPRI0) Field Descriptions .......................................................... 17311-20. Master Priority 1 Register (MSTPRI1) Field Descriptions .......................................................... 17411-21. Master Priority 2 Register (MSTPRI2) Field Descriptions .......................................................... 17511-22. Pin Multiplexing Control 0 Register (PINMUX0) Field Descriptions ............................................... 17611-23. Pin Multiplexing Control 1 Register (PINMUX1) Field Descriptions ............................................... 17811-24. Pin Multiplexing Control 2 Register (PINMUX2) Field Descriptions ............................................... 18011-25. Pin Multiplexing Control 3 Register (PINMUX3) Field Descriptions ............................................... 18211-26. Pin Multiplexing Control 4 Register (PINMUX4) Field Descriptions ............................................... 18411-27. Pin Multiplexing Control 5 Register (PINMUX5) Field Descriptions ............................................... 18611-28. Pin Multiplexing Control 6 Register (PINMUX6) Field Descriptions ............................................... 18811-29. Pin Multiplexing Control 7 Register (PINMUX7) Field Descriptions ............................................... 19011-30. Pin Multiplexing Control 8 Register (PINMUX8) Field Descriptions ............................................... 19211-31. Pin Multiplexing Control 9 Register (PINMUX9) Field Descriptions ............................................... 19411-32. Pin Multiplexing Control 10 Register (PINMUX10) Field Descriptions ............................................ 19611-33. Pin Multiplexing Control 11 Register (PINMUX11) Field Descriptions ............................................ 19811-34. Pin Multiplexing Control 12 Register (PINMUX12) Field Descriptions ............................................ 20011-35. Pin Multiplexing Control 13 Register (PINMUX13) Field Descriptions ............................................ 20211-36. Pin Multiplexing Control 14 Register (PINMUX14) Field Descriptions ............................................ 20411-37. Pin Multiplexing Control 15 Register (PINMUX15) Field Descriptions ............................................ 20611-38. Pin Multiplexing Control 16 Register (PINMUX16) Field Descriptions ............................................ 20811-39. Pin Multiplexing Control 17 Register (PINMUX17) Field Descriptions ............................................ 21011-40. Pin Multiplexing Control 18 Register (PINMUX18) Field Descriptions ............................................ 21211-41. Pin Multiplexing Control 19 Register (PINMUX19) Field Descriptions ............................................ 21411-42. Suspend Source Register (SUSPSRC) Field Descriptions......................................................... 21611-43. Chip Signal Register (CHIPSIG) Field Descriptions................................................................. 21911-44. Chip Signal Clear Register (CHIPSIG_CLR) Field Descriptions................................................... 22011-45. Chip Configuration 0 Register (CFGCHIP0) Field Descriptions ................................................... 22111-46. Chip Configuration 1 Register (CFGCHIP1) Field Descriptions ................................................... 22311-47. Chip Configuration 2 Register (CFGCHIP2) Field Descriptions ................................................... 225

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11-48. Chip Configuration 3 Register (CFGCHIP3) Field Descriptions ................................................... 22711-49. Chip Configuration 4 Register (CFGCHIP4) Field Descriptions ................................................... 22811-50. VTP I/O Control Register (VTPIO_CTL) Field Descriptions ........................................................ 22911-51. DDR Slew Register (DDR_SLEW) Field Descriptions .............................................................. 23111-52. Deep Sleep Register (DEEPSLEEP) Field Descriptions ........................................................... 23211-53. Pullup/Pulldown Enable Register (PUPD_ENA) Field Descriptions............................................... 23311-54. Pullup/Pulldown Select Register (PUPD_SEL) Field Descriptions ................................................ 23311-55. Pullup/Pulldown Select Register (PUPD_SEL) Default Values .................................................... 23411-56. RXACTIVE Control Register (RXACTIVE) Field Descriptions ..................................................... 23511-57. Power Down Control Register (PWRDN) Field Descriptions....................................................... 23512-1. AINTC System Interrupt Assignments ................................................................................ 23912-2. ARM Interrupt Controller (AINTC) Registers ......................................................................... 24512-3. Revision Identification Register (REVID) Field Descriptions ....................................................... 24612-4. Control Register (CR) Field Descriptions ............................................................................. 24712-5. Global Enable Register (GER) Field Descriptions ................................................................... 24812-6. Global Nesting Level Register (GNLR) Field Descriptions ......................................................... 24812-7. System Interrupt Status Indexed Set Register (SISR) Field Descriptions ........................................ 24912-8. System Interrupt Status Indexed Clear Register (SICR) Field Descriptions ..................................... 24912-9. System Interrupt Enable Indexed Set Register (EISR) Field Descriptions ....................................... 25012-10. System Interrupt Enable Indexed Clear Register (EICR) Field Descriptions..................................... 25012-11. Host Interrupt Enable Indexed Set Register (HEISR) Field Descriptions......................................... 25112-12. Host Interrupt Enable Indexed Clear Register (HIEICR) Field Descriptions ..................................... 25112-13. Vector Base Register (VBR) Field Descriptions ..................................................................... 25212-14. Vector Size Register (VSR) Field Descriptions ...................................................................... 25212-15. Vector Null Register (VNR) Field Descriptions....................................................................... 25312-16. Global Prioritized Index Register (GPIR) Field Descriptions ....................................................... 25312-17. Global Prioritized Vector Register (GPVR) Field Descriptions ..................................................... 25412-18. System Interrupt Status Raw/Set Register 1 (SRSR1) Field Descriptions ....................................... 25412-19. System Interrupt Status Raw/Set Register 2 (SRSR2) Field Descriptions ....................................... 25512-20. System Interrupt Status Raw/Set Register 3 (SRSR3) Field Descriptions ....................................... 25512-21. System Interrupt Status Raw/Set Register 4 (SRSR4) Field Descriptions ....................................... 25612-22. System Interrupt Status Enabled/Clear Register 1 (SECR1) Field Descriptions ................................ 25612-23. System Interrupt Status Enabled/Clear Register 2 (SECR2) Field Descriptions ................................ 25712-24. System Interrupt Status Enabled/Clear Register 3 (SECR3) Field Descriptions ................................ 25712-25. System Interrupt Status Enabled/Clear Register 4 (SECR4) Field Descriptions ................................ 25812-26. System Interrupt Enable Set Register 1 (ESR1) Field Descriptions .............................................. 25812-27. System Interrupt Enable Set Register 2 (ESR2) Field Descriptions .............................................. 25912-28. System Interrupt Enable Set Register 3 (ESR3) Field Descriptions .............................................. 25912-29. System Interrupt Enable Set Register 4 (ESR4) Field Descriptions .............................................. 26012-30. System Interrupt Enable Clear Register 1 (ECR1) Field Descriptions ............................................ 26012-31. System Interrupt Enable Clear Register 2 (ECR2) Field Descriptions ............................................ 26112-32. System Interrupt Enable Clear Register 3 (ECR3) Field Descriptions ............................................ 26112-33. System Interrupt Enable Clear Register 4 (ECR4) Field Descriptions ............................................ 26212-34. Channel Map Registers (CMRn) Field Descriptions................................................................. 26212-35. Host Interrupt Prioritized Index Register 1 (HIPIR1) Field Descriptions .......................................... 26312-36. Host Interrupt Prioritized Index Register 2 (HIPIR2) Field Descriptions .......................................... 26312-37. Host Interrupt Nesting Level Register 1 (HINLR1) Field Descriptions ............................................ 26412-38. Host Interrupt Nesting Level Register 2 (HINLR2) Field Descriptions ............................................ 26412-39. Host Interrupt Enable Register (HIER) Field Descriptions.......................................................... 265

16 List of Tables SPRUGM7D–April 2010

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12-40. Host Interrupt Prioritized Vector Register 1 (HIPVR1) Field Descriptions ........................................ 26612-41. Host Interrupt Prioritized Vector Register 2 (HIPVR2) Field Descriptions ........................................ 266A-1. Document Revision History ............................................................................................. 271

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18 List of Tables SPRUGM7D–April 2010

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PrefaceSPRUGM7D–April 2010

Read This First

About This Manual

Describes the System-on-Chip (SoC) system. The SoC system includes TI’s standard TMS320C674xMegamodule and several blocks of internal memory (L1P, L1D, and L2). This document provides anoverview of the system and the following considerations associated with it:• ARM subsystem• DSP subsystem• System interconnect• System memory• Memory protection unit (MPU)• Device clocking• Phase-locked loop controller (PLLC)• Power and sleep controller (PSC)• Power management• System configuration (SYSCFG) module• ARM interrupt controller (AINTC)• Boot considerations

Notational Conventions

This document uses the following conventions.

• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40hexadecimal (decimal 64): 40h.

• Registers in this document are shown in figures and described in tables.

– Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name, its beginning and ending bit numbers above, and itsread/write properties below. A legend explains the notation used for the properties.

– Reserved bits in a register figure designate a bit that is used for future device expansion.

Related Documentation From Texas Instruments

Copies of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number inthe search box provided at www.ti.com.

The current documentation that describes related peripherals and other technical collateral, is available inthe C6000 DSP product folder at: www.ti.com/c6000.

SPRUFK9— TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide. Providesan overview and briefly describes the peripherals available on the TMS320C674x Digital SignalProcessors (DSPs) and OMAP-L1x Applications Processors.

SPRUFK5— TMS320C674x DSP Megamodule Reference Guide. Describes the TMS320C674x digitalsignal processor (DSP) megamodule. Included is a discussion on the internal direct memory access(IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidthmanagement, and the memory and cache.

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Related Documentation From Texas Instruments www.ti.com

SPRUFE8— TMS320C674x DSP CPU and Instruction Set Reference Guide. Describes the CPUarchitecture, pipeline, instruction set, and interrupts for the TMS320C674x digital signal processors(DSPs). The C674x DSP is an enhancement of the C64x+ and C67x+ DSPs with addedfunctionality and an expanded instruction set.

SPRUG82— TMS320C674x DSP Cache User's Guide. Explains the fundamentals of memory cachesand describes how the two-level cache-based internal memory architecture in the TMS320C674xdigital signal processor (DSP) can be efficiently used in DSP applications. Shows how to maintaincoherence with external memory, how to use DMA to reduce memory latencies, and how tooptimize your code to improve cache efficiency. The internal memory architecture in the C674xDSP is organized in a two-level hierarchy consisting of a dedicated program cache (L1P) and adedicated data cache (L1D) on the first level. Accesses by the CPU to the these first level cachescan complete without CPU pipeline stalls. If the data requested by the CPU is not contained incache, it is fetched from the next lower memory level, L2 or external memory.

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Chapter 1SPRUGM7D–April 2010

Overview

Topic ........................................................................................................................... Page

1.1 Introduction ...................................................................................................... 221.2 Block Diagram .................................................................................................. 221.3 DSP Subsystem ................................................................................................ 221.4 ARM Subsystem ................................................................................................ 22

21SPRUGM7D–April 2010 Overview

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Switched Central Resource (SCR)

1024KB L2 ROM

256KB L2 RAM

32KBL1 RAM

32KBL1 Pgm

16KBI-Cache

16KBD-Cache

AET4KB ETB

C674x™DSP CPU

ARM926EJ-S CPUWith MMU

DSP SubsystemARM SubsystemJTAG Interface

System Control

InputClock(s)

64KB ROM

8KB RAM(Vector Table)

Power/SleepController

PinMultiplexing

PLL/ClockGenerator

w/OSC

General-Purpose

Timer (x3)

Serial InterfacesAudio Ports

McASPw/FIFO

DMA

Peripherals

DisplaySharedMemory

LCDCtlr

128KBRAM

External Memory InterfacesConnectivity

EDMA3(x2)

Control Timers

eHRPWM(x2)

eCAP(x3)

EMIFA(8b/16B)NAND/Flash16b SDRAM

DDR2/mDDRMemory

Controller

RTC/32-kHzOSC

I C(x2)

2 SPI(x2)

UART(x3)

McBSP(x2)

Video

VPIF

ParallelPort

uPP

EMAC10/100

(MII/RMII)MDIO

USB1.1OHCI Ctlr

PHY

USB2.0OTG Ctlr

PHYHPI

MMC/SD(8b)(x2)

SATA

CustomizableInterface

PRUSubsystem

Introduction www.ti.com

1.1 Introduction

The OMAP-L138 Applications Processor contains two primary CPU cores: an ARM RISC CPU forgeneral-purpose processing and systems control; and a powerful DSP to efficiently handle communicationand audio processing tasks. The OMAP-L138 Applications Processor consists of the following primarycomponents:

• ARM926 RISC CPU core and associated memories• DSP and associated memories• A set of I/O peripherals• A powerful DMA subsystem and SDRAM EMIF interface

1.2 Block Diagram

A block diagram for the OMAP-L138 Applications Processor is shown in Figure 1-1.

1.3 DSP Subsystem

The DSP subsystem (DSPSS) includes TI’s standard TMS320C674x megamodule and several blocks ofinternal memory (L1P, L1D, and L2). Chapter 3 describes the DSPSS components.

1.4 ARM Subsystem

The ARM926EJ 32-bit RISC CPU in the ARM subsystem (ARMSS) acts as the overall system controller.The ARM CPU performs general system control tasks, such as system initialization, configuration, powermanagement, user interface, and user command implementation. Chapter 2 describes the ARMSScomponents and system control functions that the ARM core performs.

Figure 1-1. OMAP-L138 Applications Processor Block Diagram

Note: Not all peripherals are available at the same time due to multiplexing.

22 Overview SPRUGM7D–April 2010

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Chapter 2SPRUGM7D–April 2010

ARM Subsystem

Topic ........................................................................................................................... Page

2.1 Introduction ...................................................................................................... 242.2 Operating States/Modes ..................................................................................... 252.3 Processor Status Registers ................................................................................ 252.4 Exceptions and Exception Vectors ...................................................................... 26