OMAP-L137 Evaluation Module

OMAP-L137Evaluation Module

2008 DSP Development Systems

ReferenceTechnical

OMAP-L137 Evaluation Module Technical Reference

511345-0001 Rev. A November 2008

SPECTRUM DIGITAL, INC.12502 Exchange Drive, Suite 440 Stafford, TX. 77477

Tel: 281.494.4505 Fax: [email protected] www.spectrumdigital.com

IMPORTANT NOTICE

Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue anyproduct or service without notice. Customers are advised to obtain the latest version of relevantinformation to verify that the data being relied on is current before placing orders.

Spectrum Digital, Inc. warrants performance of its products and related software to currentspecifications in accordance with Spectrum Digital’s standard warranty. Testing and other qualitycontrol techniques are utilized to the extent deemed necessary to support this warranty.

Please be aware that the products described herein are not intended for use in life-support appliances, devices, or systems. Spectrum Digital does not warrant nor is Spectrum Digital liable for the product described herein to be used in other than a development environment.

Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does SpectrumDigital warrant or represent any license, either express or implied, is granted under any patent right,copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to anycombination, machine, or process in which such Digital Signal Processing development products orservices might be or are used.

WARNING

This equipment is intended for use in a laboratory test environment only. It generates, uses, and canradiate radio frequency energy and has not been tested for compliance with the limits of computingdevices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonableprotection against radio frequency interference. Operation of this equipment in other environmentsmay cause interference with radio communications, in which case the user at his own expense will berequired to take whatever measures necessary to correct this interference.

Copyright © 2008 Spectrum Digital, Inc.

Contents

1 Introduction to the OMAP-L137 Evaluation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Provides you with a description of the OMAP-L137 Evaluation Module, key features, and block diagram. 1.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2 Functional Overview of the OMAP-L137 EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.3 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.5 Configuration Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.6 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-62 Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Describes the operation of the major board components on the OMAP-L137 Evaluation Module. 2.1 EMIF-A Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.1 EMIF-B SDRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.2 Memory Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.3 UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.4 USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2 AIC3106 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.3 Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

2.4 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.5 Daughter Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

3 Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Describes the physical layout of the OMAP-L137 Evaluation Module and its connectors. 3.1 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.2.1 J1, USB Capacitance Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.2.2 J2, USB 2.0 Connector and Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.2.3 J3, USB Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.2.4 J4, 14 Pin External JTAG Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.2.5 J5, ARM JTAG Emulation Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.2.6 J6, +5 Volt Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.2.7 P1, RS-232 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.2.8 P2, MMC/SD Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.2.9 P3, Line In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.2.10 P4, Microphone In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.2.11 P5, Headphone Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.2.12 P6, Line Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.2.13 P8, RJ9 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3.2.14 P9, Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3.2.15 P10, Ethernet Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3.2.16 Expansion Connector Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3.2.16.1 P11, Audio / Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3.2.16.2 P12, Expansion 2 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3.2.16.3 P13, Expansion 3 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.2.17 P14, Phono Jack In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 3.2.18 P15, Phono Jack In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 3.2.19 J201, Embedded JTAG Emulation Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 3.3 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 3.4 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 3.4.1 SW1, EMU0/1 Select Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 3.4.2 SW2, Boot Mode Select Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 3.4.3 SW3, User Readable 4 Position DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 3.4.4 SW4, Reset Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 3.4.5 SW5, Pull-Up Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3.4.6 SW6, On/Off Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3.5 Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24A Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Contains the schematics for the OMAP-L137 Evaluation ModuleB Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 Contains the mechanical information about the OMAP-L137 Evaluation Module

About This Manual

This document describes the board level operations of the OMAP-L137 EvaluationModule (EVM). The EVM is based on the Texas Instruments OMAP-L137 Processor.

The OMAP-L137 Evaluation Module is a table top card that allows engineers andsoftware developers to evaluate certain characteristics of the OMAP-L137 processor todetermine if the processor meets the designers application requirements. Evaluatorscan create software to execute on board or expand the system in a variety of ways.

Notational Conventions

This document uses the following conventions.

The OMAP-L137 Evaluation Module will sometimes be referred to as the OMAP-L137EVM or EVM.

Program listings, program examples, and interactive displays are shown in a specialitalic typeface. Here is a sample program listing.

equations!rd = !strobe&rw;

Information About Cautions

This book may contain cautions.This is an example of a caution statement.A caution statement describes a situation that could potentially damage your software,or hardware, or other equipment. The information in a caution is provided for yourprotection. Please read each caution carefully.

Related Documents, Application Notes and User Guides

Information regarding the OMAP-L137 can be found at the following TexasInstruments website:

http://www.ti.com

Table 1: Manual History

Revision History

A Beta

Table 2: Board History

PWBRevision

History

D Beta Release

1-1

Chapter 1

Introduction to the OMAP-L137 EVM

Chapter One provides a description of the OMAP-L137 EVM along with thekey features and a block diagram of the circuit board.

Topic Page

1.1 Key Features 1-21.2 Functional Overview of the OMAP-L137 EVM 1-41.3 Basic Operation 1-41.4 Memory Map 1-51.5 Boot Switch Settings 1-61.6 Power Supply 1-6

Spectrum Digital, Inc

1-2 OMAP-L137 EVM Technical Reference

1.1 Key Features

The OMAP-L137 EVM is a standalone development platform that enables users toevaluate and develop applications for the OMAP-L137 processor. Schematics andapplication notes are available to ease hardware development and reduce time tomarket.

The EVM comes with a full complement of on board devices that suit a wide variety ofapplication environments. Key features include:

• A Texas Instruments OMAP-L137 device with a C674x VLIW DSP floating point processor and an ARM926EJ-S processor operating up to 300 Mhz.

• 64 Megabytes SDRAM

• SPI Boot EEPROM

• 2 Port Ethernet Phy/switch

• SD/MMC/MMC Plus media card interfaces

• TLV320AIC3106 Stereo Codec

• USB 1.1 High speed interface

• USB2 2.0 Full speed interface

• RS-232 Interface

Figure 1-1, Block Diagram OMAP-L137 EVM

JTAG

32SDRAM

SDRAM

S/P

DIF

HP

OU

T

MIC

IN

LINE

IN

LINE

OU

T

ENETRJ45

ENETRJ45

USB0USB1

Aud

io Expa

nsion

LEDs

DIP

EmbeddedJTAG

Emulator

On-boardJTAG

TI JTAG

ARM JTAG

Micrel ENETPHY + Switch

RTCPWR

PWR

PWR SW

EMIFB

EMIFA Expansion

EMIFA

HandsetM

IC

HandsetS

PK

R

TPS65023VREG

McASP0/1

MII

I2C Bus

RS-232

UART

CFG

I2CROM

AIC3106CODEC

SD/MMC

SD/MMC

USB1 / USB0

OMAP-L137

Serial Exp.

BOOT


1-3

• On chip real time clock

• Configurable boot load options

• 4 user LEDs/4 position user DIP switch

• Single voltage power supply (+5V)

• Expansion connectors for daughter card use

• Embedded JTAG Emulation

• 14 Pin TI JTAG/20 Pin ARM JTAG Interfaces

Figure 1-2, OMAP-L137 EVM



1.2 Functional Overview of the OMAP-L137 EVM

The OMAP-L137 on the EVM interfaces to on-board peripherals through the 16-bitwide multiplexed EMIF interface pins. The SDRAM memory is connected to its owndedicated 32 bit wide bus.

An on-board AIC3106 codec allows the DSP to transmit and receive analog audio

signals. The I2C bus is used for the codec control interface, while the McASP controlsthe audio stream. Signal interfacing is done through 3.5mm audio jacks that correspondto microphone input, headphone output, line input, and line output.

The EVM includes 4 user LEDs, a 4 position user DIP switch, and on chip real timeclock. On board multi-plexing allows ease of interfacing to the daughter cards.

An included +5V external power supply is used to power the board. On-board switchingvoltage regulators provide the CPU core voltage, +3.3V, +1.8V for peripheralinterfacing. The board is held in reset by the on board power controller until thesesupplies are within operating specifications.

Code Composer Studio communicates with the EVM through an embedded emulatoror via the TI 14 pin or ARM 20 pin external JTAG connectors.

1.3 Basic Operation

The EVM is designed to work with TI’s Code Composer Studio IDETM, orMontaVista tool environments. Code Composer communicates with the boardthrough an on board JTAG emulator. This EVM is shipped with an EVM specific CodeComposer Studio environment. To start, follow the instructions in the Quick StartGuide to install Code Composer. This process will install all of the necessarydevelopment tools, documentation and drivers.


1-5

1.4 Memory Map

The OMAP-L137 processor has a byte addressable address space. However, there aresome limitations to byte addressing determined by peripheral interconnection to theOMAP-L137 device. Program code and data can be placed anywhere in the unifiedaddress space. Addresses are multiple sizes depending on hardware implementation.Refer to the appropriate device data sheets for more details.

The memory map shows the address space of a generic OMAP-L137 processor on theleft with specific details of how each region is used on the right. By default, the internalmemory sits at the beginning of the address space. Portions of memory can beremapped in software as L2 cache rather than fixed RAM.

The part incorporates a dual EMIF interface. One dedicated EMIF, EMIF-B, directlyinterfaces to the SDRAM memory. EMIF-A has 3 separate addressable regions calledchip enable spaces (CE0, CS2, CS3), however the EVM uses this interface as aperipheral interface to daughter card connectors. The memory map of the OMAP-L137EVM is shown in the table below.

Table 1: OMAP-L137 EVM Memory Map

Start Address End AddressARM Mem

MapDSP Mem

Map

0x0080 0000 0x0083 FFFF DSP L2 RAM

0x00E0 0000 0x00f0 7FFFF DSP L1P RAM

0x00F0 0000 0x00F0 8000 DSP L1D RAM

0x0184 0000 0x0184 FFFF DSP Memory System

0x1180 0000 0x1183 FFFF DSP L2 RAM

0x11E0 0000 0x11E0 7FFF DSP L1P RAM

0x1FF0 0000 0x11F0 7FFF DSP L1D RAM

0x8000 0000 0x8001 FFFF Shared RAM

0xB000 0000 0xB000 7FFF EMIFB control regs

0xC000 0000 0xDFFF FFFF EMIFB SDRAM Data

0xFFFE E000 0xFFFE FFFF ARM Interrupt Controller0xFFFF 0000 0xFFFF 1FFF ARM Local RAM



1.5 Boot Switch Settings

The EVM has a 5 position switch that allow users to configure the operational state ofthe processor when it is released from reset and determine the source for processorbooting. Switch SW2 configures the boot mode that will be used when the DSP startsexecuting. By default the switches are configured to serial EEPROM boot. The tablebelow shows the boot mode sources and their respective switch positions.

* Supported on Standalone EVM

1.6 Power Supply

The EVM operates from a single +5V external power supply connected to the mainpower input (J6), a 2.5 MM. barrel-type plug. Internally, the +5V input is convertedinto core voltage, +1.8V and +3.3V using Texas Instruments TPS65023 PowerManagement Unit. The +3.3V and +1.8V supply are used for the DSP's I/Obuffers and other chips on the board.

Table 2: SW2, Boot Mode Select

Pos 1Boot[7]

Pos 2Boot[2]

Pos 3Boot[1]

Pos 4Boot[0]

Pos 5Boot[3]

Boot PinBTMODE[7,2,1,0,3]

Boot Mode

OFF OFF OFF ON NA 0 0 0 1 x NOR

OFF OFF ON OFF NA 0 0 1 0 x HPI

OFF ON OFF ON NA 0 1 0 1 x SPI0 Flash

OFF ON ON OFF NA 0 1 1 0 x SPI1 Flash

OFF ON ON ON NA 0 1 1 1 x NAND 8-bit

OFF OFF OFF OFF OFF 0 0 0 0 0 I2C0 Master

OFF OFF OFF OFF ON 0 0 0 0 1 I2C0 Slave

OFF OFF ON ON OFF 0 0 1 1 0 I2C1 Master

OFF OFF ON ON ON 0 0 1 1 1 I2C1 Slave

OFF ON OFF OFF OFF 0 1 0 0 0 SPI0 EEPROM *

OFF ON OFF OFF ON 0 1 0 0 1 SPI1 EEPROM

ON OFF OFF ON OFF 1 0 0 1 0 SPI0 Slave

ON OFF OFF ON ON 1 0 0 1 1 SPI1 Slave

ON OFF ON ON OFF 1 0 1 1 0 UART0

ON OFF ON ON ON 1 0 1 1 1 UART1

ON OFF ON OFF OFF 1 0 1 0 0 UART2 *

ON ON ON ON OFF 1 1 1 1 0 Emulation Debug *

2-1

Chapter 2

Board Components

This chapter describes the operation of the major board components onthe OMAP-L137 EVM.

Topic Page

2.1 EMIF-A Interfaces 2-22.1.1 EMIF-B SDRAM Memory Interface 2-22.1.2 Memory Card Interface 2-22.1.3 UART Interface 2-22.1.4 USB Interface 2-22.2 AIC3106 Interface 2-32.3 Ethernet Interface 2-42.4 I2C Interface 2-52.5 Daughter Card Interface 2-6



2.1 EMIF-A Interfaces

A separate 16 bit EMIF with three chip enables divide up the address space and allowfor asynchronous accesses on the EVM. The EVM uses this interface for peripheralinterfaces to the daughter card.

2.1.1 EMIF-B SDRAM Memory Interface

The OMAP-L137 device incorporates a dedicated 32 bit wide SDRAM memory bus.The EVM uses two 256 Megabit, 16 bit wide memories on this bus, for a total of 64megabytes of memory for program, data, and video storage. The internal SDRAMcontroller uses a PLL to control the SDRAM memory timing. Memory refresh forSDRAM is handled automatically by the OMAP-L137 internal SDRAM controller.

2.1.2 Memory Card Interface

The EVM supports SD/MMC/MMC PLUS media card interfaces. This interface ismultiplexed with other function the EMIFA bus.

2.1.3 UART Interface

The internal UART2 on the OMAP-L137 device is driven to connector P1. The UART’sinterface is routed to the RS-232 line drivers prior to being brought out to a DB-9connector, P1.

2.1.4 USB Interface

The OMAP-L137 incorporates two on chip USB controllers. The USB 2.0 interface isbrought out to a micro A/B connector. A jumper is provided to make a flexible host,peripheral, and USB on the go interface. The second USB 1.1 interface is broughtout to an A type host interface connector.


2-3

2.2 AIC3106 Interface

The EVM incorporates a Texas Instruments TLV320AIC3106 stereo codec for input andoutput of audio signals. The codec samples analog signals on the microphone or lineinputs and converts them into digital data so it can be processed by the DSP. When theDSP is finished with the data it uses the codec to convert the samples back into analogsignals on the line output so the user can hear the output.

The codec communicates using two serial channels, one to control the codec’s internal

configuration registers and one to send and receive digital audio samples. The I2C busis used as the AIC3106’s control channel. The control channel is generally only usedwhen configuring the codec, it is typically idle when audio data is being transmitted,

McASP1 is used as the bi-directional data channel. All audio data flows through thedata channel. Many data formats are supported based on the three variables ofsample width, clock signal source and serial data format. The EVM examples generallyuse a 16-bit sample width with the codec in master mode so it generates the framesync and bit clocks at the correct sample rate without effort on the DSP side.

The codec is clocked via a 24.576 Mhz oscillator. The internal sample rate generatorsubdivides the default system clock to generate common audio frequencies. Thesample rate is set by a codec register. The figure below shows the codec interface onthe OMAP-L137 EVM.

Figure 2-1, OMAP-L137 EVM CODEC INTERFACE

DOUTDIN

BCLKWCLK

MIC IN

LINE IN

LINE OUT

HP OUT

McASP

AIC3106 Codec

Digital Analog

MIC IN

LINE IN

LINE OUT

HP OUT

SCLSDA

I2CControlSCL

SDAI2C Format Control Registers

ADC

DAC

AXR[0]AXR[5]ACLKRACLKXAFSRAFSX



2.3 Ethernet Interface

The OMAP-L137 incorporates an ethernet MAC which interfaces to a MicrelKSZ8893MQL ethernet switch. The multi-port 10/100 Mbit interface is isolated andbrought out to two RJ-45 standard ethernet connectors, P9, P10. The ethernet

addresses is stored in the on board I2C EEPROM. The 2 ethernet addresses stored inthe EEPROM are the first address and the address + 1. The first address should

always be an even number. The I2C bus is also used to control configuration registersin the switch that are not accessible via the MDIO module.

Two ports provide the ability to input and pass data for Voice Over IP (VOIP) or otherdaisy chained applications. Connector P9 is the primary port for normal operation.

The RJ-45 jacks have 2 LEDs integrated into their connector. The LEDs are green andyellow and provide link and transmit status from the ethernet controller.

The MAC address for each EVM is also written on a label on the bottom of the board.The figure below shows an examples of this.

Figure 2-2, OMAP-L137 MAC Address


2-5

2.4 I2C0 Interface

The I2C0 bus on the OMAP-L137 is ideal for interfacing to the control registers of many

devices. On the OMAP-L137 EVM the I2C0 bus is used to configure the ethernet phy

and Codec. An I2C ROM is also interfaced via the serial bus. The format of the bus isshown in the figure below.

The addresses of the on board peripherals are shown in the table below.

Table 1: I2C0 Memory Map

Device Address R/W Function

KSZ8893MQL 0x5D R/W Ethernet Switch

TLV320AIC3106 0x1B R/W CODEC

I2C EEPROM 0x25 R/W I2C EEPROM

Figure 2-3, I2C Bus Format

Start Slave Address W ACK Sub Address ACK-S Data ACK-S Stop

Write Sequence

Start Slave Address R Data STOP

Read Sequence



2.5 Daughter Card Interfaces

The EVM provides expansion connectors that can be used to accept plug-in daughtercards. The daughter card allows users to build on their EVM platform to extend itscapabilities and provide customer and application specific I/O. The expansionconnectors are interfaces which include McASP, and serial I/O expansion. The EMIF-Asignals are brought out as LCD, peripheral, or EMIF signals.

The daughter card connectors used on the EVM are shown in the table below.

One of the compatible mating daughter card connectors used to interface to the EVMare shown in the table below (other heights are available).

Table 2: Daughter Card Connectors

Reference Designator

Part Numbers Used On EVM

Manufacturer

P11 QSE-040-01-L-D-A-K Samtec



Table 3: Mating Daughter Card Connectors

Reference Designator

Part Numbers Used On EVM

Manufacturer

XP11 QTE-040-02-L-D-A-K Samtec



3-1

Chapter 3

Physical Description

This chapter describes the physical layout of the OMAP-L137 EVM and itsinterfaces.

Topic Page

3.1 Board Layout 3-33.2 Connectors 3-43.2.1 J1, USB Capacitance Select 3-53.2.2 J2, USB 2.0 Connector and Jumpers 3-63.2.3 J3, USB 1.1 Connector 3-63.2.4 J4, 14 Pin External JTAG Connector 3-73.2.5 J5, ARM JTAG Emulation Header 3-73.2.6 J6, +5V Input 3-83.2.7 P1, RS-232 UART 3-83.2.8 P2, MMC/SD Connector 3-93.2.9 P3, Line In 3-103.2.10 P4, Microphone In 3-103.2.11 P5, Headphone Out 3-113.2.12 P6, Line Out 3-113.2.13 P8, RJ9 Connector 3-123.2.14 P9, Ethernet Interface 3-123.2.15 P10, Ethernet Interface 3-133.2.16 Expansion Connector Overview 3-143.2.16.1 P11, Audio / Expansion Connector 3-153.2.16.2 P12, Expansion 2 Connector 3-163.2.16.3 P13, Expansion 3 Connector 3-173.2.17 P14, Phono Jack In 3-183.2.18 P15, Phono Jack In 3-183.2.19 J201, Embedded JTAG Emulation Interface 3-18



Topic Page3.3 LEDs 3-183.4 Switches 3-193.4.1 SW1, EMU0/1 Select Switch 3-193.4.2 SW2, Boot Mode Select Switch 3-203.4.3 SW3, User Readable 4 Position DIP Switch 3-223.4.4 SW4, RESET Switch 3-223.4.5 SW5, Mux Control Switch 3-233.4.5 SW6, On/Off Switch 3-233.5 Test Points 3-24


3-3

3.1 Board Layout

The OMAP-L137 EVM is a 5.0 x 8.55 inch (127 x 217 mm.) ten (10) layer printed circuitboard which is powered by an external +5 volt only power supply. Figure 3-1 shows thelayout of the top side of the OMAP-L137 EVM.

Figure 3-1, OMAP-L137 EVM, Interfaces Top Side

J201

P1

J5

SW3

P6

P2

J3

J6

P3

SW6

DS5

SW2

J1

J4

DS7

P9

P10

P4

P14

P5

P15

P11

P12

P13

SW5

SW1

J205

SW4

J2

P8

DS5,8,9

DS1-4

DS501



3.2 Connectors

The EVM has numerous connectors and option jumpers to control and provideconnections to various peripherals. These connectors and jumpers are described in thefollowing sections.

Table 1: Connectors

Connector Size Function

J1 1 x 2 USB Capacitance Select

J2 2 USB Interface

J3 6 USB Interface

J4 2 x 7 TI 14 Pin JTAG

J5 2 x 8 ARM JTAG Emulation Header

J6 2 +5V In

P1 9 RS-232 UART

P2 28 SD/MMC Connector

P3 4 Line In

P4 4 Microphone In

P5 4 Headphone Out

P6 4 Line Out

P8 4 RJ9 Connector

P9 12 Ethernet

P10 12 Ethernet

P11 2 x 45 Audio Expansion Connector

P12 2 x 22 Expansion 2

P13 2 x 45 Expansion 3

P14 3 Phono Jack

P15 3 Phono Jack

J201 Embedded JTAG Interface

J205 2 x 5 Not populated, factory use only


3-5

3.2.1 J1, USB Capacitance Select

Connector J1 is a jumper is used to provide more capacitance when the USB connectoris used in the host mode. When the jumper is shorted the extra capacitance isprovided. These open and shorted position are shown below.

Table 2: J1, USB Capacitance Select

Position Function

Open 6.8 uF Capacitance

Shorted 106.8 uF Capacitance

J1

Figure 3-2, J1, USB Capacitance Select

USB VBUS

Open

J1

USB VBUS

Shorted



3.2.2 J2, USB 2.0 Connector and Jumpers

Connector J2 is a micro A/B USB connector. The pinout for the J2 connector is shownin the table below.

* Use internal register to swap DM/DP pair. This feature was used to improve printed circuit board routing.

The EVM supplies up to 500 ma of current to the USB_VBUS via a TPS2065. This isenabled via the OMAP-L137’s DRV_VBUS pin. J1 supplies extra capacitance for hostmode operations. Remove J1 for “USB On The Go” operations.

3.2.3 J3, USB 1.1 Connector

Connector J3 is a USB-A connector. This connector is connected directly to the OMAPL137 processor. A TPS2065 switches on host power via the L137 GPIO[15]. The pinoutfor the J3 connector is shown in the table below.

Table 3: J2, USB Connector

Pins Signal

1 USB_VBUS

2 USB_DM

3 USB_DP

4 USB_ID

5-9 USB_SHIELD

Table 4: J3, USB Connector

Pins Signal

1 VBUS

2 D-, USB1_DM

3 D+, USB1_DP

4 GND, Ground

5 USB_Shield

6 USB_Shield


3-7

3.2.4 J4, 14 Pin External JTAG Connector

Connector J4 is a 2 x 7 double row male header. This is the standard interface used byJTAG emulators to interface to Texas Instruments DSPs. The pinout for the connectoris shown in the figure below.

3.2.5 J5, ARM JTAG Emulation Header

The J5 emulation header is located on the top side of the board and is used to providean interface to ARM compatible JTAG emulators. The pinout for this connector isshown in the table below.

Table 5: J5, ARM JTAG Emulation Header

Pin # Signal Pin # Signal

1 VCC_3V3 2 VCC_3V3

3 ARM_TRSTn 4 Ground

5 ARM_TDI 6 Ground

7 ARM_TMS 8 Ground

9 ARM_TCK 10 Ground

11 ARM_TCKRET 12 Ground

13 ARM_TDO 14 Ground

15 ARM_RSTn 16 Ground

17 NC 18 Ground

19 NC 20 Ground

1 23 4

5 67 89 1011 1213 14

TMSTDI

PD (+3.3V)TDO

TCK-RET

TCKEMU0

TRST-GNDno pin (key)GNDGND

GNDEMU1

Header Dimensions

Pin-to-Pin spacing, 0.100 in. (X,Y)Pin width, 0.025-in. square post

Pin length, 0.235-in. nominal

Figure 3-3, 14 Pin External JTAG Connector



3.2.6 J6, +5V Input

Connector J6 is the input power connector. This connector brings in +5 volts to theEVM. This is a 2.5mm. jack. The inside of the jack is tied to through a fuse to VCC_5V.The other side is tied to ground and LED DS7. The figure below shows this connectoras viewed from the card edge.

3.2.7 P1, RS-232 UART

The P1 connector is a 9 pin male D-connector which provides a UART interface to theEVM. This connector interfaces to the MAX 3221 RS-232 line driver (U28) and islocated on the top side of the board. A view of the connector from the card edge isshown in the figure below. The signals present on this connector are defined in thefollowing table.

The pin numbers and their corresponding signals are shown in the table below. Thiscorresponds to a standard dual row to DB-9 connector interface used on personalcomputers.

Table 6: P1, RS-232 Pinout

Pin # Signal Name

1 NC

2 R_IN, Rx Data

3 T_OUT, Tx Data

4 NC

5 GND

6 NC

7 Pin 8

8 Pin 7

9 NC

PC Board

J6+5V

Ground

Front ViewFigure 3-4, J6, +5 Volt Input Connector

Figure 3-5, P1, DB9 Male Connector

6789

12345


3-9

3.2.8 P2, MMC/SD Connector

The P2 MMC/SD connector is located on the top side of the board and is used toprovide an interface to the following interfaces: MMC+, SD, and MMC. The pinout forthe P2 connector is shown in the table below.

Table 7: P2, MMC/SD Connector

Pin # Signal

1 MMC_SD_DATA3 - #1_MMC+/MMC/SD

2 MMC_SD_CMD - #2_MMC+/MMC/SD

3 GND - #3_MMC+/MMC/SD

4 DSK_3V3 - #4_MMC+/MMC/SD

5 MMC_SD_CLK - #5_MMC+/MMC/SD

6 GND - #6_MMC+/MMC/SD

7 MMC_SD_DATA0 - #7_MMC+/MMC/SD

8 MMC_SD_DATA1 - #8_MMC+/SD

9 MMC_SD_DATA2 - #9_MMC+/SD

10 MMC_SD_DATA4 - #10_MMC+



13 MMC_SD_DATA7 - #13_MMC+/

14 MMC_SD_WP - SD_WP

15 MMC_SD_INS - CD

16 Reserved

17 Reserved

18 GND

19 DSK_3V3

20 Reserved

21 GND

22 Reserved

23 Reserved

24 Reserved

25 NC -

26 NC -

27 GND

28 GND



3.2.9 P3, Line In

Connector P3 is an stereo audio line input. The input connector is a 3.5 mm stereo jack.The signals on the mating plug are shown in the figure below.

3.2.10 P4, Microphone In

Connector P4 is an stereo microphone line input. The input connector is a 3.5 mmstereo jack. The signals on the mating plug are shown in the figure below.

Table 8: P3, Line In Interface

Pin # AIC3106 Signal

1 (sleeve) GND_AC

2 (ring) LINE1L+

3 (tip) LINE1R+

4 (sleeve) GND_AC

Table 9: P4, Microphone In Interface


1 (sleeve) GND_AC

2 (ring) MIC3L/MIC3R

3 (tip) MIC3L/MIC3R

4 (sleeve) GND_AC

Right Line In (tip)

Ground (sleeve)

Figure 3-6, P3, Audio Line In Stereo Jack

Left Line In (ring)

Right Line In (tip)

Ground (sleeve)

Figure 3-7, P4, Microphone In Stereo Jack

Left Line In (ring)


3-11

3.2.11 P5, Headphone Out

The P5 connector is a 3.5 mm. stereo headphone output from the TVL320AIC3106 onthe EVM. The signals on the mating plug are shown in the figure below The signalspresent on this connector are defined in the following table.

3.2.12 P6, Line Out

The audio line out connector P6, is a stereo output. The output connector is a 3.5 mmstereo jack. The signals on the mating plug are shown in the figure below.

Table 10: P5, Headphone Out Interface


1(sleeve) GND_AC

2(ring HPLOUT

3(tip) HPROUT

4 NC

Table 11: P6, Audio Line Out Stereo Jack

Pin # AIC33 Signal

1 (sleeve) GND_AC

2 (ring) LEFT_LO+

3 (tip) RIGHT_LO+

4 (sleeve) NC

Left Line Out (tip)

Ground (sleeve)

Figure 3-8, P5, Headphone Out Stereo Jack

Right Line Out (ring)

Left Line Out (tip)

Ground (sleeve)

Figure 3-9, P6, Audio Line Out Stereo Jack

Right Line Out (ring)



3.2.13 P8, RJ9 Connector

The headset interface, P8, is a standard RJ9-4 connector which is not populated asshipped.

3.2.14 P9, Ethernet Interface

The P9 connector is located on the top side of the board and is used to provide anEthernet interface. P9 integrates the magnetics and standard RJ-45 connector. Thetwo tables below show the signals present on the magnetics interface and theconnector side.

The ethernet connector incorporates 2 LEDs which give link and transmit status fromthe ethernet controller.

Table 12: P9, Magnetics/LEDs Interface Signals


1 TXP1 (TXD+) 2 TXM1 (TXD-)

3 RXP1 (RXD+) 4 ENET_VDDATR (TXD-CT)

5 ENET_VDDATR (RXD-CT) 6 RXM1 (RXD-)

7 NC1 8 GND

9 VCC_3V3(LED1+) 10 P1LED2(LED1-)

11 DSK_3V3(LED2+) 12 P1LED3(LED2-)

Table 13: P9, RJ-45 Connector


1 TX_DATA+ 2 TX_DATA-

3 RX_DATA+ 4 NC

5 NC 6 RX_DATA-

7 NC 8 NC


3-13

3.2.15 P10, Ethernet Interface

The P10 connector is located on the top side of the board and is used to provide anEthernet interface. P10 integrates the magnetics and standard RJ-45 connector. Thetwo tables below show the signals present on the magnetics interface and theconnector side.

The ethernet connector incorporates 2 LEDs which give link and transmit status fromthe ethernet controller.

Table 14: P10, Magnetics/LEDs Interface Signals


1 TXP2 (TXD+) 2 TXM2 (TXD-)

3 RXP2 (RXD+) 4 ENET_VDDATR (TXD-CT)

5 ENET_VDDATR (RXD-CT) 6 RXM2 (RXD-)

7 NC1 8 GND

9 VCC_3V3(LED1+) 10 P2LED2(LED1-)

11 DSK_3V3(LED2+) 12 P2LED3(LED2-)

Table 15: P10, RJ-45 Connector


1 TX_DATA+ 2 TX_DATA-

3 RX_DATA+ 4 NC

5 NC 6 RX_DATA-

7 NC 8 NC



3.2.16 Expansion Connector Overview

The EVM has three expansion connectors which allow the user to interface to otherlogic which is unique to his application

Some of the signals on the EVM are multiplexed with an on board resource or theyhave multiple options on the L137 device. To enable these signals there are severalcontrol lines on the expansion connector. Pulling the control lines high enables thefunctions marked in the Mux_Ctl column tables. The number in the Mux_Ctl columnindicates which pins it controls. An ‘N’ in front of the column indicates the pin isavailable when the control line is not pulled high. Each control line is pulled down onthe EVM, therefore a pull-up resistor of approximately 500 ohms is required to enablethe control line to a logic ‘1’. A ‘*’ in the Mux_Ctl column indicates this is a control lineon the expansion connectors.

The next 3 tables indicate the interface signal and the appropriate control line on thepins of the expansion connectors.


3-15

3.2.16.1 P11, Audio / Expansion Connector

* 1 Control line for Mux_Ctl 1 signals, * 2 Control line for Mux_Ctl 2 signals* 3 Control line for Mux_Ctl 3 signals, * N5 is not control signal 5 (default)* N7 is not control signal 7 (default), * N11 is not control signal 11 (default)* N12 is not control signal 12 (default)

Table 16: P11, Audio / Expansion Connector

Pin Signal Mux_Ctl Pin Signal Mux_Ctl2 VCC_5V 1 VCC_5V4 VCC_5V 3 VCC_5V6 NC 5 I2C0_SDA

8 SEL_ENETn_MCASP0 * 1 7 I2C0_SCL10 T_AMUTE0 9 EXP_ACHLKR0 1

12 Ground 11 Ground14 EXP1_AFSX0 13 T_AFSR016 Ground 15 Ground

18 T_ACLKX0 17 T_ACLKR020 Ground 19 Ground22 EXP_AXR0[0] 1 21 EXP_AXR[8] 1

24 EXP_AXR0[1] 1 23 EXP_AXR0_9 N726 EXP_AXR0[2] 1 25 EXP_AXR0_10 N728 EXP_AXR0[3] 1 27 EXP1_AXR0_12 N11

30 EXP_AXR0[4] 1 29 EXP1_AXR0_13 N1132 EXP_AXR0[5] 1 31 EXP1_AXR0_14 N1134 EXP_AXR0[6] 1 33 EXP1_AXR0_15 N11

36 EXP_AXR0[7] 1 35 T_AXR0_11/AXR2_0/GPIO3_1138 Ground 37 Ground40 AHCLKR2 39 EXP1_AMUTE2_8 N12

42 EXP1_SPI1_SCSn 3 41 EXP1_SPI1_ENAn 344 EXP1_SPI1_CLK 43 EXP1_SPI1_SIMO46 EXP_RESETn 45 EXP1_SPI1_SOMI

48 Ground 47 Ground50 T_AMUTE1 49 EXP_AHCLKX1 252 Ground 51 Ground

54 EXP_AFSX1 2 53 T_AFSR156 Ground 55 Ground58 EXP_ACLKX1 2 57 T_ACLKR1

60 Ground 59 Ground62 EXP_AXR1[0] 2 61 T_AXR1[6]64 EXP_AXR1[1] 63 T_AXR1[7]

66 EXP_AXR1[2] 65 T_AXR1[8]68 EXP_AXR1[3] N5 67 T_AXR1[9]70 EXP_AXR1[4] N5 69 T_AXR1[10]

72 EXP_AXR1[5] 2 71 T_AXR1[11]74 EXP1_SEL_MCASP1 * 2 73 SEL_SPI1_EXP1 * 376 NC 75 NC

78 VCC_5V 77 VCC_5V80 VCC_5V 79 VCC_5V82 Ground 81 Ground

84 Ground 83 Ground86 Ground 85 Ground88 Ground 87 Ground

90 NC 89 NC



3.2.16.2 P12, Expansion 2 Connector

* 4 Control line for Mux_Ctl 4 signals* 5 Control line for Mux_Ctl 5 signals* 6 Control line for Mux_Ctl 6 signals* 7 Control line for Mux_Ctl 7 signals* 8 Control line for Mux_Ctl 8 signals* 9 Control line for Mux_Ctl 9 signals

Table 17: P12, Expansion 2 Connector

Pin Signal Mux_Ctl Pin Signal Mux_Ctl

2 VCC_5V 1 VCC_5V

4 VCC_5V 3 VCC_5V

6 Ground 5 Ground

8 EXP_SPI1_SOMI 9 7 EXP2_SPI0_SOMI 6

10 EXP2_SPI1_SIMO 9 9 EXP2_SPI0_SOMO 6

12 EXP_SPI1_CLK 9 11 EXP2_SPI0_CLK 6

14 EXP2_SPI1_SCSn 4 13 EQEP0A 6

16 EXP2_SPI1_ENAn 4 15 EQEP0B 6

18 Ground 17 Ground

20 SEL_SPI1_EXP2 * 4 19 IC20_SCL

22 EXP_EQEP1A 5 21 IC20_SDA

24 EXP_EQE1B 5 23 NC

26 SEL_EXP2_QEP1 * 5 25 SEL_EXP2_QEP0 * 6

28 EXP2_UART1_RXD 7 27 EXP2_TMP640_OUT12 9

30 EXP2_UART1_TXD 7 29 EXP2_TMP640_IN12 9

32 Ground 31 Ground

34 SEL_EXP2_UART1 * 7 33 SEL_SPI1_EXP2_B * 8

36 EXP_RESETn 35 SEL_EXP2_TIMER * 9

38 VCC_5V 37 VCC_5V

40 VCC_5V 39 VCC_5V

42 Ground 41 Ground

44 Ground 43 Ground


3-17

3.2.16.3 P13, Expansion 3 Connector

* 10 Control line for Mux_Ctl 10 signals* 11 Control line for Mux_Ctl 11 signals* 12 Control line for Mux_Ctl 12 signals* 13 Control line for Mux_Ctl 13 signals* 14 Control line for Mux_Ctl 14 signals

Table 18: P13, Expansion 3 Connector

Pin Signal Mux_Ctl Pin Signal Mux_Ctl2 VCC_5V 1 VCC_5V4 VCC_5V 3 VCC_5V6 EXP3_SEL_MEMD0_7 * 10 5 NC

8 EXP3_SEL_MEM * 11 7 EXP3_SEL_MEM_CTL * 1210 Ground 9 Ground

12 EXP_EMIFA_D0 10 11 EXP_EMIFA_D1 1014 EXP_EMIFA_D2 10 13 EXP_EMIFA_D3 1016 EXP_EMIFA_D4 10 15 EXP_EMIFA_D5 10

18 EXP_EMIFA_D6 10 17 EXP_EMIFA_D7 1020 Ground 19 Ground22 EXP_EMIFA_D8 13 21 EXP_EMIFA_D9 13

24 EXP_EMIFA_D10 13 23 EXP_EMIFA_D11 1326 EXP_EMIFA_D12 14 25 EXP_EMIFA_D13 1428 EXP_EMIFA_D14 14 27 EXP_EMIFA_D15 14

30 Ground 29 Ground32 EXP3_SEL_MEMD8_D11 * 13 31 EXP_EMIFA_WEn_DQM0 1134 EXP3_SEL_MEMD12_D16 * 14 33 EXP_EMIFA_WEn_DQM1 11

36 Ground 35 Ground38 EXP3_EMIFA_CLK 37 EMIFA_SDCKE40 Ground 39 Ground

42 Ground 41 Ground44 EXP3_EMIFA_OEn 11 43 EMIFA_CS4n 1046 EXP3_EMIFA_WEn 11 45 EMIFA_CS5n 10

48 Ground 47 NC50 EMIFA_WAIT0 49 EMIFA_CS2n52 EMIFA_CS0n 51 EXP3_EMIFA_CS3n 12

54 NC 53 NC56 EMIFA_BA0 55 EMIFA_BA158 EMIFA_A0 57 EXP_EMIFA_A1 10

60 EXP_EMIFA_A2 10 59 EMIFA_A462 EMIFA_A3 61 EMIFA_A664 EMIFA_A5 63 EMIFA_A8

66 EMIFA_A7 65 EMIFA_A1068 EMIFA_A9 67 EMIFA_A1270 EMIFA_A11 69 NC

72 Ground 71 Ground74 EXP_RESETn 73 NC76 NC 75 NC

78 VCC_5V 77 VCC_5V80 VCC_5V 79 VCC_5V82 Ground 81 Ground

84 Ground 83 Ground86 Ground 85 Ground88 Ground 87 Ground

90 NC 89 NC



3.2.17 P14, Phono Jack In

Connector P14 is a phono jack input. This connector is not populated as shipped.

3.2.18 P15, Phono Jack In

Connector P15 is a phono jack input. This connector is not populated as shipped.

3.2.21 J201, Embedded JTAG Emulation Interface

Connector J201 is a USB interface providing JTAG access to the processor. This allowsthe user to develop and debug using Code Composer Studio on a PC.

3.3 LEDs

The EVM has ten (10) LEDs which are located on the top side of the board. Information regarding the LEDs are shown in the table below.

Table 19: LEDs

LED # Use Color

DS1 User control, EMIFA D12 Green




DS5 USB-EMU ON/OFF Green

DS6 VCC_1V2 Green

DS7 VCC_5V Green

DS8 VCC_1V8 Green

DS9 VCC_3V3 Green

DS501 On board EMU status Green


3-19

3.4 Switches

The EVM has six (6) switches. The function of these switches are shown in the tablebelow.

3.4.1 SW1, EMU0/1 Select Switch

SW1 is a 2 position DIP switch providing 4 options in selecting the state of the EMU0and EMU1 pins on the OMAP-L137 processor. This switch is not needed for theOMAP-L137 processor.

The default is to select pull ups on the EMU0 and EMU1.

Table 20: Switches

Switch Function Type

SW1 EMU0/EMU1 Control 4 Position DIP

SW2 Boot Mode Select 6 Position DIP

SW3 User Readable 4 Position DIP

SW4 RESET Switch Push Button/Momentary

SW5 Pull Up Select 6 Position DIP

SW6 On/Off Power Switch Toggle



3.4.2 SW2, Boot Mode Select Switch

Switch SW2 is a 6 position DIP switch. Only 5 of the positions are used. Note that only5 combinations provide valid options. The boot mode options are described in the tablebelow.

The figure below shows the SW2 switch.

Table 21: SW2, Boot Mode Select DIP Switch

Position Pins Signal

1 1-12 BOOTMODE[7]

2 2-11 BOOTMODE[2]

3 3-10 BOOTMODE[1]

4 4-9 BOOTMODE[0]

5 5-8 BOOTMODE[3]

6 6-7 NC

Figure 3-10, SW2, Boot Mode Select Switch

SW2Raised

1

2

3

4

5

6

1

2

3

4

5

6

12

11

10

9

8

7

Actuator


3-21

The table below shows the position settings which select the various boot modes.

* Supported in standalone EVM

Table 22: SW2, Boot Mode Select

Pos 1Boot[7]

Pos 2Boot[2]

Pos 3Boot[1]

Pos 4Boot[0]

Pos 5Boot[3]

Boot PinBTMODE[7,2,1,0,3]

Boot Mode

OFF OFF OFF ON NA 0 0 0 1 x NOR

OFF OFF ON OFF NA 0 0 1 0 x HPI

OFF ON OFF ON NA 0 1 0 1 x SPI0 Flash

OFF ON ON OFF NA 0 1 1 0 x SPI1 Flash

OFF ON ON ON NA 0 1 1 1 x NAND 8-bit

OFF OFF OFF OFF OFF 0 0 0 0 0 I2C0 Master

OFF OFF OFF OFF ON 0 0 0 0 1 I2C0 Slave

OFF OFF ON ON OFF 0 0 1 1 0 I2C1 Master

OFF OFF ON ON ON 0 0 1 1 1 I2C1 Slave

OFF ON OFF OFF OFF 0 1 0 0 0 SPI0 EEPROM *

OFF ON OFF OFF ON 0 1 0 0 1 SPI1 EEPROM

ON OFF OFF ON OFF 1 0 0 1 0 SPI0 Slave

ON OFF OFF ON ON 1 0 0 1 1 SPI1 Slave

ON OFF ON ON OFF 1 0 1 1 0 UART0

ON OFF ON ON ON 1 0 1 1 1 UART1

ON OFF ON OFF OFF 1 0 1 0 0 UART2 *

ON ON ON ON OFF 1 1 1 1 0 Emulation Debug *



3.4.3 SW3, User Readable 4 Position DIP Switch

Switch SW6 is a 4 position DIP switch mapped to EMIFA data bus lines D8-D11 viaa multiplexer. The table below shows what signal each position appears on.

3.4.4 SW4, RESET Switch

Switch SW4 is a push button reset switch that will RESET the board.

Table 23: SW3, User Readable 4 Position DIP Switch

Position Signal

1 SW_DIP0, EMIFA - D8




Figure 3-11, SW3, User Readable 4 Position DIP Switch SW3

4

Raised

321

ON Actuator


3-23

3.4.5 SW5, Mux Control Switch

Switch SW5 is a 6 position DIP switch that allows mux control signals to be pulled up to+3.3 volts. This switch allows enabling on mux control signals. The six signals that canbe pulled up are shown in the table below. Alternatively the multiplexer control lines canbe enabled via daughter card connectors. Additional control lines are mapped to thedaughter card connectors. Refer to the expansion connector sections 3.2.16.1 to3.2.16.2 for more information.

The figure below shows the SW5 switch.

3.4.6 SW6, On/Off Switch

Switch SW6 is an on/off toggle switch that allows +5 volts from the J6 connector to beapplied to the board.

Table 24: SW5, Pull-Up Switch

Position Signal Mux_Ctl

SW5-1 SEL_ENETn_MCASP0 * 1

SW5-2 SEL_EXP2_TIMER * 9

SW5-3 SEL_EXP2_UART1 * 7

SW5-4 ON_BD_OFF_BD U19 control for USB

SW5-5 EXP3_SEL_MEMD8-D11 * 13

SW5-6 EXP3_SEL_MEMD12-D15 * 14

Figure 3-12, SW5, Pull-Up Switch

Raised

1

2

3

4

5

6

1

2

3

4

5

6

12

11

10

9

8

7

SW

5

CFG_EN

Actuator



3.5 Test Points

The EVM has 49 test points. All test points appear on the top of the board. Thefollowing figure identifies the position of each test point. The next table lists each testpoint and the signal appearing on that test point.

Figure 3-13, OMAP-L137 EVM, Test Points

TP7

TP17

TP27

TP26

TP31

TP24

TP32

TP40

TP6

TP18

TP35-38

TP20TP34 TP515

TP21

TP22

TP8

TP4

TP5

TP23

TP25

TP514

TP2

TP1

TP517

TP14 TP13

TP16

TP15

TP9-12

TP33

TP520

PTP1

PTP10

PTP2

PTP4

PTP3

PTP5

PTP6

PTP7

PTP8

PTP9

TP39


3-25

There are 10 power test point pairs for major power domains on the EVM. These testpoints provide a convenient mechanism to check the EVM’s multiple power supplies.The table below shows the voltages for each test point and what the supply is used for.

Table 25: OMAP-L137 EVM Test Points

Test Point #

SignalTest Point

#Signal

TP1 U13, Pin 6,7,8, VBUS From J2 TP16 U41, Pin 6, P2LED0

TP2 DSK_3V3, U13, Pin 5, OCn TP27 U44, Pin 28, INTn

TP4 U14, Pin 6,7,8, VBUS from J3 TP28 U44, Pin 20, VLDO1

TP5 DSK_3V3, U14, Pin 5, OCn TP29 U44, Pin 18, VLDO2

TP6 U1, F7, RSV1 TP33 VCC_5V

TP7 U38, Pin 35, GPIO1 TP34 U54, Pin 5, ALT_CPU_1V2

TP8 U38, Pin 35, GPIO2 TP35 USB1, TAIN0

TP9 U38, Pin 45, MFP0 TP36 USB1, TAIN1



TP12 U38, Pin 48, MFP3 TP39 U38, Pin 27, MONO_LO+

TP13 U41, Pin 2, P1LED1 TP40 U38, Pin 28, MONO_LO-

TP14 U41, Pin 3, P1LED0 TP515 Factory Use

TP15 U41, Pin 5, P2LED1 TP517 Factory Use

TP520 Factory Use

Table 26: Power Test Points

AccessTest Points

Voltage Shunt Comments

TP17, TP18 DSK_3V3 0.025 ohms All EVM 3.3V supplies except CPU

TP19, TP20 CPU_1V2 0.025 ohms All CPU 1.2V supplies


TP23, TP24 DSK_1V8 0.025 ohms All EVM 1.8V supplies except CPU




Furthermore the EVM has ten 2 pin power test points for specific power domains onthe L137 device. These voltages are measured across a resistor which is why there aretwo points to each test position. The square pad is the ground. The round padis the measured voltage. The figure below shows what a typical power test point lookslike.

The table below shows the power test points and the voltage measured.

Table 27: Power Test Points

PowerTest Point

VoltageMeasured

PTP1 CPU_3V3

PTP2 CPU_1V2

PTP3 CPU_1V2

PTP4 CPU_1V2

PTP5 CPU_1V2

PTP6 CPU_1V2

PTP7 CPU_3V3

PTP8 CPU_1V8

PTP9 CPU_3V3

PTP10 CPU_1V8

Measured voltage

Figure 3-14, Power Test Point

Ground

Pin 2

Pin 1

A-1

Appendix A

Schematics

This appendix contains the schematics for the OMAP-L137 EVM.


A-2 OMAP-L137 EVM Technical Reference

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

D

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5113

42-0

001

Mo

nd

ay,

No

vem

ber

24

, 2

00

81

32

B

OM

AP

-L13

7 E

VM

TIT

LE P

AG

E

REV

ENGR

2REVISION STATUS OF SHEETS

111

SH

DATE

14

12

13

DATE

ENGR-MGR

MFG

7

DWN

DATE

8

DATE

10

SH

DATE

CHK

RLSE

APPLICATION

REV

35

NEXT ASSY

DATE

6

DATE

9

QA

USED ON

4

15

BB

BA

A

DA

AC

R.R.P.

T.W.K.

R.R.P.

R.R.P.

C.M.D.

R.R.P.

R.R.P.

06/01/2008

16

REV

SH

A

D

A

BD

BB

06/01/2008

12/01/2006

06/01/2008

06/01/2008

06/01/2008

06/01/2008

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

AA

BA

AB

BB

BB

AA

AA

BB

REV

SH

SCHEMATIC

CONTENTS

SHEET01 - TITLE PAGE

SHEET02 - L137 McASP/ETHERNET

SHEET03 - ETHERNET/McASP MUX

SHEET04 - L137 SERIAL I/O

SHEET05 - SPI MUXING

SHEET06 - L137 USB 2.0 PORT

SHEET07 - L137 USB 1.0 PORT

SHEET08 - L137 EMIF A

SHEET09 - L137 EMIF B

SHEET10 - L137 JTAG/CLOCKS

SHEET11 - L137 POWER PINS

SHEET12 - L137 GROUND PINS

SHEET13 - L137 DECOUPLING CAPACITORS

SHEET14 - BOOT MODE SWITCHES

SHEET15 - EMIFB SDRAM

SHEET16 - SPI ROM

SHEET17 - USER SWITCHES/LEDS

SHEET18 - RS232 INTERFACE

SHEET19 - SD/MMC MUXING

SHEET20 - SD/MMC/MMC Plus CARD INTERFACE

SHEET21 - JTAG CONNECTOR INTERFACE

SHEET22 - AIC3106 AUDIO CODEC

SHEET23 - AIC PHONE/AUDIO JACK

SHEET24 - ETHERNET PHY/SWITCH

SHEET25 - ETHERNET POWER

SHEET26 - ETHER NET PORTS

SHEET27 - EXPANSION CONNECTOR 1



SHEET30 - POWER

SHEET31 - POWER II

SHEET32 - POWER IN


A-3

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

T_A

MU

TE

1T

_AF

SX

1T

_AC

LKX

1T

_A

HC

LKX

1

T_

AF

SR

1T

_AC

LK

R1

T_

AH

CLK

R1

T_

AX

R1[

0]

T_

AX

R1[

1]

T_

AX

R1[

2]

T_

AX

R1[

3]

T_A

CLK

X0

T_

AF

SR

0T

_AC

LK

R0

T_

AX

R1[

4]

T_

AX

R1[

5]

T_

AX

R1[

6]

T_

AX

R1[

7]

T_

AX

R1[

8]

T_

AX

R1[

9]

T_

AX

R1[

10]

T_

AX

R1[

11]

T_A

XR

0[6

]/R

MII

_RX

ER

T_A

XR

0[4

]/R

MII

_RX

D[0

]

T_

AX

R0

[3]/

RM

II_

CR

S_

DV

T_A

XR

0[2

]/RM

II_T

XE

N

T_A

XR

0[5

]/R

MII

_RX

D[1

]

T_A

XR

0[0]

/RM

II_T

XD

[0]

T_A

XR

0[1]

/RM

II_T

XD

[1]

T_

AX

R0

[8]/

RM

II_M

DIO

_D

T_A

XR

0[7

]/R

MII_

MD

IO_

CL

K

T_A

XR

0_11

/AX

R2_

0/G

PIO

3_11

T_A

MU

TE

0

AF

SR

0

AF

SX

1

AX

R1

[1]

RM

II_

RX

D[1

]

AC

LK

R1

AX

R1

[9]

AX

R1

[2]

AC

LKX

0

RM

II_

CR

S_

DV

AM

UT

E1

AC

LK

R0

AX

R1

[10

]

AX

R1

[5]

RM

II_

TX

D[1

]

RM

II_

RX

D[0

]

AH

CL

KR

1

RM

II_M

DIO

_D

RM

II_

MD

IO_

CL

K

AX

R1

[6]

AX

R1

[11

]

RM

II_T

XD

[0]

AX

R1

[3]

RM

II_

RX

ER

RM

II_

MH

Z_

50A

CLK

X1

AX

R1

[7]

AX

R1

[0]

AF

SR

1

AX

R1

[8]

AX

R1

[4]

AF

SX

0

RM

II_T

XE

N

AM

UT

E0

T_A

HC

LKR

0/R

MII

_M

HZ

_50

AH

CLK

X1

T_

AH

CLK

X1

T_A

FS

X1

T_A

XR

1[0]

T_A

XR

1[5]

T_A

CLK

X1

T_

AIC

_B

CL

K

T_

AIC

_MC

LK

EX

P_A

CLK

X1

EX

P_A

HC

LKX

1

T_

AX

R1[

3]

T_

AX

R1[

4]

T_A

FS

X0

DS

K_3

V3

DS

K_

3V3

VC

C_

3V3

DS

K_3

V3

DS

K_

3V3

DS

K_

3V

3

T_

AX

R1[

10]

27

T_

AX

R1[

11]

27

T_

AC

LK

R1

27T

_A

FS

R1

27

T_A

MU

TE

12

7

T_

AX

R1[

8]

27

T_

AX

R1[

1]

27

T_

AX

R1[

2]

27

T_

AX

R1[

6]

27

T_

AX

R1[

7]

27

T_

AX

R1[

9]

27

T_

AX

R0

[8]/

RM

II_

MD

IO_

D3

T_

AX

R0

_11/

AX

R2_

0/G

PIO

3_11

27T

_A

HC

LK

R0

/RM

II_M

HZ

_50

3

T_A

CLK

R0

27

T_A

CLK

X0

6,2

7T

_A

FS

R0

27

T_A

FS

X0

27

T_A

XR

0[0]

/RM

II_T

XD

[0]

3T

_AX

R0[

1]/R

MII

_TX

D[1

]3

T_A

XR

0[2

]/RM

II_T

XE

N3T_

AX

R0

[3]/

RM

II_

CR

S_

DV

3

T_

AX

R0

[4]/

RM

II_R

XD

[0]

3T

_A

XR

0[5

]/R

MII_

RX

D[1

]3

T_

AX

R0[

6]/R

MII

_RX

ER

3

T_

AX

R0

[7]/

RM

II_

MD

IO_

CL

K3

T_A

MU

TE

02

7

T_

AIC

_WC

LK

22

T_A

IC_

BC

LK

22

T_A

IC_

DIN

22T

_A

IC_D

OU

T22

T_

AIC

_M

CL

K2

2

EX

P1

_SE

L_M

CA

SP

127

EX

P_A

XR

1[3]

27

EX

P_A

XR

1[4]

27

EX

P_E

QE

P1

A28

EX

P_E

QE

P1

B28

SE

L_E

XP

2_Q

EP

128

BO

OT

_DIS

AB

LE

n3

,4,5

,8,1

6,1

9,27

,31

BO

OT

_D

ISA

BL

En

,4,5

,8,1

6,1

9,2

7,3

1 BO

OT

_DIS

AB

LE

3,1

4,1

6,1

9,3

1

EX

P_A

CLK

X1

27

EX

P_A

FS

X1

27E

XP

_AH

CLK

X1

27

EX

P_A

XR

1[0]

27

EX

P_A

XR

1[5]

27

T_

AH

CL

KR

127

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5113

42-0

001

Mo

nd

ay,

No

vem

ber

24

, 2

00

82

32

B

OM

AP

-L13

7 E

VM

McA

SP

/Eth

ern

et

MA

C

MCLK: AHCLKX1 (drive this clock into McASP)

BCLK: ACLKX1 (McASP will drive this into the AIC)

WCLK: AFSX1 (McASP will drive this into the AIC)

DIN: AXR1[5] (McASP)

DOUT: AXR1[0] (McASP)

Drive the MCLK into McASP1 Tx.

McASP generates the Tx bit and frame clocks.

Configure McASP such that the Rx section

operates off of the Tx section clocks.

RN

2R

PA

CK

4-2

2

12345 6 7 8

RN

5R

PA

CK

4-2

2

12345 6 7 8

RN

6R

PA

CK

4-2

2

12345 6 7 8

R6

22

R2

NO

-PO

P

RN

1R

PA

CK

4-2

2

12345 6 7 8

U4

SN

74

LV

C1

G3

2D

CK

RG

4

1 2

3

4

5

C2

0.1

uF

R1

3N

O-P

OP

R8

22

OM

AP

L13

7ZK

B

U1-

6

AX

R1_

0/G

PIO

4_0

T3

AX

R1_

11/G

PIO

5_11

T4

AX

R1_

1/G

PIO

4_1

R2

AX

R1_

3/E

QE

P1A

/GP

IO4_

3P

1A

XR

1_2/

GP

IO4_

2P

2

AX

R1_

5/E

PW

M2B

/GP

IO4_

5N

1A

XR

1_4/

EQ

EP

1B/G

PIO

4_4

N2

AX

R1_

10__

GP

IO5_

10N

3A

XR

1_9/

GP

IO4_

9M

1A

XR

1_8/

EP

WM

1A/G

PIO

4_8

M2

AX

R1_

7/E

PW

M1B

/GP

IO4_

7M

3A

XR

1_6/

EP

WM

2A/G

PIO

4_6

M4

AH

CLK

R1/

GP

IO4_

11L1

AC

LKR

1/E

CA

P2/

AP

WM

2/G

PIO

4_12

L2

AF

SR

1/G

PIO

4_13

L3

AM

UT

E0_

_RE

SE

TO

UT

L4

AH

CLK

X1/

EP

WM

0B/G

PIO

3_14

K2

AC

LKX

1/E

PW

M0A

/GP

IO3_

15K

3

AF

SX

1/E

PW

MS

YN

CI/E

PW

MS

YN

C0/

GP

IO4_

10K

4

AM

UT

E1/

EH

RP

WM

TZ

/GP

IO4_

14D

4

AF

SX

0/G

PIO

2_13

/BO

OT

_10

D5

AX

R0_

6/R

MII_

RX

ER

/AC

LKR

2/G

PIO

3_6

D7

AX

R0_

2/R

MII_

TX

EN

/AX

R2_

3/G

PIO

3_2

D8

AF

SR

0/G

PIO

3_12

C4

AC

LKX

0/E

CA

P0/

AP

WM

0/G

PIO

2_12

C5

AX

R0_

5/R

MII_

RX

D1/

AF

SX

2/G

PIO

3_5

C7

AX

R0_

1/R

MII_

TX

D1/

AC

LKX

2/G

PIO

3_1

C8

AC

LKR

0/E

CA

P1/

AP

WM

1/G

PIO

2_15

B4

AH

CLK

X0/

AH

CLK

X2/

US

B_R

EF

CLK

IN/G

PIO

2_11

B5

AX

R0_

8/M

DIO

_D/G

PIO

3_8

B6

AX

R0_

4/R

MII_

RX

D_0

/AX

R2_

1/G

PIO

3_4

B7

AX

R0_

0/R

MII_

TX

D0/

AF

SR

2/G

PIO

3_0

B8

AH

CLK

R0/

RM

II_M

HZ

_50C

LK/G

PIO

2_14

/BO

OT

_11

A4

AX

R0_

11/A

XR

2_0/

GP

IO3_

11A

5

AX

R0_

7/M

DIO

_CLK

/GP

IO3_

7A

6

AX

R0_

3/R

MII_

CR

S_D

V/A

XR

2_2/

GP

IO3_

3A

7

C1

0.1

uF

R1

22

R7

22

C3

.1u

F

R1

82K

U5

SN

74

LV

C1

G0

0D

CK

RG

4

1 2

3

4

5

R1

50

R1

422

R9

22R

10

22

R1

622

U2

SN

74C

BT

LV3

257P

W

1A4

4B1

14

2A7

3B1

11

3A9

4A12

4B2

13

S1

1B1

2

OE

15

3B2

10

1B2

3

2B1

5

2B2

6

VC

C16

GN

D8

RN

3R

PA

CK

4-2

2

12345 6 7 8

R4

22

R1

222

U3

SN

74C

BT

LV3

384P

W

1OE

1

2OE

13

1A1

3

1A2

4

1A3

7

1A4

8

1A5

11

1B1

2

1B2

5

1B3

6

1B4

9

1B5

10

2A1

14

2A2

17

2A3

18

2A4

21

2A5

22

Vcc

24

GN

D12

2B1

15

2B2

16

2B3

19

2B4

20

2B5

23

R5

22

C4

.1u

FR

192K

R1

122

R3

2K

RN

4R

PA

CK

4-2

2

12345 6 7 8

R1

72K



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

T_

AX

R0[

0]/R

MII_

TX

D[0

]

T_

AX

R0[

8]/R

MII

_M

DIO

_D

T_

AH

CL

KR

0/R

MII

_M

HZ

_50

T_

AX

R0[

6]/R

MII

_RX

ER

T_

AX

R0[

3]/R

MII

_C

RS

_D

V

T_

AX

R0

[5]/

RM

II_R

XD

[1]

B_R

MII_

TX

D[1

]

B_

RM

II_

CR

S_

DV

B_

RM

II_

RX

D[0

]

B_

RM

II_

RX

ER

T_A

XR

0[2

]/RM

II_T

XE

NT

_A

XR

0[1

]/RM

II_T

XD

[1]

T_

AX

R0

[4]/

RM

II_R

XD

[0]

T_

AX

R0[

7]/R

MII_

MD

IO_C

LK

B_R

MII_

TX

D[0

]

B_

RM

II_

RX

D[1

]

B_

RM

II_T

XE

N

B_

RM

II_

MH

Z_5

0

EX

P_A

HC

LK

R0

EX

P_

AX

R0[

0]E

XP

_A

XR

0[1]

EX

P_

AX

R0[

3]E

XP

_A

XR

0[2]

EX

P_

AX

R0[

4]E

XP

_A

XR

0[5]

EX

P_

AX

R0[

6]

EX

P_

AX

R0[

8]E

XP

_A

XR

0[7]

DS

K_3

V3

DS

K_3

V3

DS

K_3

V3

T_

AX

R0

[8]/

RM

II_

MD

IO_

D2T_

AH

CL

KR

0/R

MII

_M

HZ

_50

2

T_

AX

R0[

0]/R

MII_

TX

D[0

]2

T_

AX

R0[

1]/R

MII_

TX

D[1

]2

T_

AX

R0

[2]/R

MII

_T

XE

N2 T_

AX

R0

[3]/

RM

II_

CR

S_D

V2

T_A

XR

0[4

]/R

MII

_RX

D[0

]2

T_A

XR

0[5

]/R

MII

_RX

D[1

]2

T_

AX

R0[

6]/R

MII

_RX

ER

2

T_A

XR

0[7

]/R

MII

_MD

IO_

CLK

2

SE

L_E

NE

Tn_

MC

AS

P0

14,

27

B_

RM

II_T

XD

[0]

24B

_R

MII

_TX

D[1

]24

B_

RM

II_T

XE

N24

B_

RM

II_C

RS

_D

V24

B_

RM

II_

RX

D[0

]24

B_

RM

II_

RX

D[1

]24

B_

RM

II_M

HZ

_50

24

EX

P_A

XR

0[8

]27

EX

P_A

HC

LKR

02

7

EX

P_A

XR

0[0

]27

EX

P_A

XR

0[1

]27

EX

P_A

XR

0[2

]27

EX

P_A

XR

0[3

]27

EX

P_A

XR

0[4

]27

EX

P_A

XR

0[5

]27

EX

P_A

XR

0[6

]27

EX

P_A

XR

0[7

]27

BO

OT

_D

ISA

BL

E2

,14

,16

,19

,31

BO

OT

_DIS

AB

LE

n2

,4,5

,8,1

6,1

9,2

7,3

1

B_

RM

II_

MD

IO_

CL

K24

B_

RM

II_M

DIO

_D

24

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

B

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5113

42-0

001

Mo

nd

ay,

No

vem

ber

24

, 2

00

83

32

B

OM

AP

-L13

7 E

VM

Eth

ern

et

Mu

xes

FUNCTION TABLE

INPUTS INPUTS/OUTPUTS FUNCTION

S2 S1 S0 A1 A2

L L L Z Z Disconnect

L L H B1 Z A1 port = B1 port

L H L B2 Z A1 port = B2 port

L H H Z B1 A2 port = B1 port

H L L Z B2 A2 port = B2 port

H L H Z Z Disconnect

H H L B1 B2 A1 port = B1 port/A2 port = B2 port

H H H B2 B1 A1 port = B2 port/ A2 port = B1 port

C8

.01

uF

R2

02K

R2

136

0R

22

1K

U8

SN

74C

BT

LV1

621

2DG

GR

S1

56

GN

D.2

19

1A1

2

11A

125

1B1

54

1B2

53

GN

D.1

8

VC

C.1

17

GN

D.3

38

GN

D.4

49

S2

55

2A1

4

3A1

6

4A1

9

5A1

11

6A1

13

7A1

15

8A1

18

9A1

21

10A

123

12A

127

1A2

3

2A2

5

3A2

7

4A2

10

5A2

12

6A2

14

7A2

16

8A2

20

S0

1

2B1

52

3B1

50

9B1

36

4B1

47

5B1

45

6B1

43

7B1

41

8B1

39

10B

134

2B2

51

3B2

48

4B2

46

5B2

44

6B2

42

7B2

40

8B2

37

11B

231

12B

229

9A2

22

10A

224

11A

226

12A

228

11B

132

12B

130

9B2

35

10B

233

U6 S

N7

4L

VC

1G

08

DC

KR

G4

1 24

5 3 U7 S

N74

LV

C1

G0

2D

CK

R

1 24

5 3

C7

0.1

uF

C6

0.1

uF

R2

336

0

C5

0.1

uF


A-5

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

AX

R0

_10

AX

R0

_9

T_S

PI1

_EN

An

UA

RT

0_T

XD

_I2

C0

_S

CL

UA

RT

0_

RX

D_I

2C0

_SD

A

AX

R0_

9

AX

R0_

10U

AR

T0

_TX

D_I

2C0

_SC

L

UA

RT

0_R

XD

_I2

C0_

SD

A

T_S

PI1

_SC

Sn

VC

C_3

V3

VC

C_

3V

3

DS

K_

3V3

DS

K_

3V3

DS

K_3

V3

DS

K_3

V3

DS

K_

3V3

DS

K_

3V3

DS

K_3

V3

DS

K_3

V3

SP

I1_

CLK

5,1

4 SP

I1_S

IMO

5

SP

I0_

CLK

14

,16 S

PI0

_SIM

O1

4,16

BO

OT

MO

DE

[1]

14

,16

BO

OT

MO

DE

[0]

14

,16

BO

OT

MO

DE

[2]

14

,16

BO

OT

MO

DE

[3]

14

,16

BO

OT

MO

DE

[7]

5,1

4

SP

I1_S

OM

I5

T_

SP

I1_E

NA

n5

T_S

PI1

_SC

Sn

5

EX

P_A

XR

0_10

27

EX

P_A

XR

0_9

27

EX

P2_

UA

RT

1_T

XD

28

EX

P2

_UA

RT

1_R

XD

28

SE

L_E

XP

2_U

AR

T1

14,

28

SP

I0_S

OM

I1

4,16

SP

I0_

EN

An

14,1

6

SP

I0_

SC

Sn

16

I2C

0_

SC

L1

6,2

2,2

4,2

7,28

,30

I2C

0_

SD

A1

6,2

2,2

4,2

7,2

8,3

0E

XP

2_T

MP

64P

0_O

UT

12

28

EX

P2_

TM

P64

P0_

IN12

28

BO

OT

_DIS

AB

LE

n2

,3,5

,8,1

6,1

9,2

7,3

1B

OO

T_

DIS

AB

LEn

2,3

,5,8

,16

,19

,27

,31

SE

L_E

XP

2_T

IME

R1

4,2

8

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5113

42-0

001

Mo

nd

ay,

No

vem

ber

24

, 2

00

84

32

B

OM

AP

-L13

7 E

VM

Se

ria

l I/O

R2

8N

O-P

OP

R2

620

K

U9

SN

74C

BT

LV3

257P

W

1A4

4B1

14

2A7

3B1

11

3A9

4A12

4B2

13

S1

1B1

2

OE

15

3B2

10

1B2

3

2B1

5

2B2

6

VC

C16

GN

D8

OM

AP

L13

7ZK

B

U1-

9

SP

I0_C

LK/E

QE

P1I

/GP

IO5_

2/B

OO

T_2

T5

SP

I1_C

LK/E

QE

P1S

/GP

IO5_

7/B

OO

T_7

T6

UA

RT

0_R

XD

/I2C

0_S

DA

/TM

64P

0_IN

12/G

PIO

5_8/

BO

OT

_8R

3

SP

I1_E

NA

n/U

AR

T2_

RX

D/G

PIO

5_12

R4

SP

I0_E

NA

n/U

AR

T0_

CT

Sn/

EQ

EP

0A/G

PIO

5_3/

BO

OT

_3R

5

SP

I0_S

OM

I/EQ

EP

0I/G

PIO

5_0/

BO

OT

_0R

6

UA

RT

0_T

XD

/I2C

0_S

CL/

TM

64P

0_O

UT

12/G

PIO

5_9/

BO

OT

_9P

3

SP

I1_S

CS

n/U

AR

T2_

TX

D/G

PIO

5_13

P4

SP

I1_S

OM

I/I2C

1_S

CL/

GP

IO5_

5/B

OO

T_5

P5

SP

I0_S

IMO

/EQ

EP

0S/G

PIO

5_1/

BO

OT

_1P

6

SP

I0_S

CS

n/U

AR

T0_

RT

Sn/

EQ

EP

0B/G

PIO

5_4/

BO

OT

_4N

4

SP

I1_S

IMO

/I2C

1_S

DA

/GP

IO5_

6/B

OO

T_6

N5

UA

RT

1_T

XD

/AX

R0_

10/G

PIO

3_10

D6

UA

RT

1_R

XD

/AX

R0_

9/G

PIO

3_9

C6

RN

8R

PA

CK

4-2

2

12345 6 7 8

R3

122

R46

2K

R3

8N

O-P

OP

R3

4N

O-P

OP

C9

0.1

uF

U1

0

SN

74C

BT

LV3

257

PW

1A4

4B1

14

2A7

3B1

11

3A9

4A12

4B2

13

S1

1B1

2

OE

15

3B2

10

1B2

3

2B1

5

2B2

6

VC

C16

GN

D8

R3

6N

O-P

OP

R4

72

K

R4

22

.2K

R3

222

R3

922

R3

720

K

R4

32

.2K

R4

436

0R

45

360

R3

3N

O-P

OP

R4

02

.2K

C1

0

0.1

uF

R3

520

K

R2

722

R3

022

R2

52

0K

RN

7R

PA

CK

4-2

2

12345 6 7 8

R41

2.2

K

R2

922

R2

420

K



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

T_

SP

I1_

SC

Sn

T_

SP

I1_

EN

An

VC

C_

3V

3

VC

C_

3V

3

SE

L_S

PI1

_EX

P2

28

UA

RT

2_R

XD

18

UA

RT

2_T

XD

18

SE

L_S

PI1

_EX

P1

27

T_

SP

I1_

EN

An

4

T_

SP

I1_

SC

Sn

4

SP

I1_

SO

MI

4

SP

I1_

CL

K4

,14 S

PI1

_SIM

O4

EX

P_S

PI1

_SO

MI

27

EX

P1_

SP

I1_C

LK27

EX

P1_

SP

I1_S

IMO

27

EX

P2_

SP

I1_

SO

MI

28

EX

P2_

SP

I1_C

LK28

EX

P2_

SP

I1_S

IMO

28

SE

L_S

PI1

_EX

P2_

B28

BO

OT

_D

ISA

BL

En

2,3

,4,8

,16

,19

,27

,31

BO

OT

_DIS

AB

LEn

2,3

,4,8

,16,

19,2

7,3

1

EX

P1

_SP

I1_E

NA

n2

7E

XP

2_S

PI1

_EN

An

28

EX

P1_

SP

I1_S

CS

n27

EX

P2_

SP

I1_S

CS

n28

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5113

42-0

001

Mo

nd

ay,

No

vem

ber

24

, 2

00

85

32

B

OM

AP

-L13

7 E

VM

SP

I M

UX

ING

R4

83

60

U12

74C

BT

LV32

53

1B1

6

1B2

5

1B3

4

1B4

3

2B1

10

2B2

11

2B3

12

2B4

13

2OE

15

S0

14

1A7

2A9

10E

1

S1

2V

IN16

GN

D8

C1

1

0.1

uF

R5

02K

R51

2K

U1

1

SN

74C

BT

LV32

57P

W

1A4

4B1

14

2A7

3B1

11

3A9

4A12

4B2

13

S1

1B1

2

OE

15

3B2

10

1B2

3

2B1

5

2B2

6

VC

C16

GN

D8

R4

92K

C1

2

0.1

uF


A-7

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

US

B_

SH

IELD

US

B_

SH

IEL

D

US

B_

SH

IEL

D

US

B_

SH

IEL

D

US

B_

SH

IEL

D

US

B0

_D

P

US

B0

_DM

CP

U_

1V8

CP

U_

3V3

DS

K_3

V3

VC

C_

5V

DS

K_

3V3

DS

K_3

V3

DS

K_3

V3

ON

_B

D_

OF

F_

BD

8,1

4

T_A

CLK

X0

2,2

7

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

B

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5113

42-0

001

Mo

nd

ay,

No

vem

ber

24

, 2

00

86

32

B

OM

AP

-L13

7 E

VM

PR

IMU

S U

SB

2.0

IN

TE

RF

AC

E

FULLSIZE B CONNECTOR

FULLSIZE A CONNECTOR

MICRO A-B CONNECTOR

THESE FOOTPRINTS ARE OVERLAYED

ONLY 1 OF 3 IS POPULATED AT 1 TIME

Differential Pair

J2C

US

B-m

icro

/A/B

co

nn

ect

or

VB

US

-A1A

D-

2A

D+

3A

GN

D4A

SH

IELD

33

SH

IELD

44

R5

50

.02

C2

7.2

2u

F

C1

50

.1u

F

C2

20

.1u

F

E1 NF

M2

1P

C47

4R

1C

3D

13

2

OM

AP

L13

7ZK

B

U1

-7

US

B0_

VS

SA

33H

4

US

B0_

VD

DA

33H

5

US

B0_

DM

G4

US

B0_

VS

SA

F3

US

B0_

DP

F4

US

B0_

VD

DA

18E

3

US

B0_

DR

VV

BU

S/G

PIO

4_15

E4

US

B0_

IDD

2

US

B0_

VB

US

D3

US

B0_

VD

DA

12C

3

C2

70.1

uF

U5

5

TP

D2E

001D

RL

IO1

3IO

25

VCC1 GND 4

NC

.22

C2

640

.1u

F

L59

3

BLM

18A

G12

1SN

1D

C2

01

uF

L1B

LM

21P

G22

1SN

1

C2

10

.00

1uF

C1

80

.1u

F

J1

HE

AD

ER

2

1 2

L59

4B

LM18

AG

121S

N1D

C1

70

.00

1uF

TP

1V

BU

S

C2

30

.01

uF

U5

97

4C

BT

LV

1G

125

CR

G4

3

4

5

2

1

U13

TP

S20

65D

OU

T1

8IN

12

GN

D1

EN 4

OCn 5

IN2

3O

UT

27

OU

T3

6

R5

610

K

+

C1

46

.8uF

R5

310

K

E2

NF

M2

1P

C4

74

R1C

3D

13

2

R5

4N

O-P

OP

R5

210

0K

+ C1

31

0u

F

R3

91

1M

+

C1

610

0uF

TP

2V

BU

S_

OC

n2

R5

70

.02

PT

P8

HE

AD

ER

2

11

22

C2

6N

O-P

OP

R5

8N

O-P

OP

C2

41

uF

J2

B

US

B-m

icro

/A/B

co

nn

ect

or

AT

TA

CH

1B

D-

2B

D+

3B

GN

D4B

SH

IELD

11

SH

IELD

22

C19

0.0

1u

F

J2

A

US

B-m

icro

/A/B

co

nn

ect

or

VB

US

1AB

D-

2AB

D+

3AB

GN

D5A

B

SHIELD5 5

ID4A

B

SHIELD6 6

SHIELD7 7

SHIELD8 8

MH1 9

MH2 10

C2

66 .1u

F

PT

P7

HE

AD

ER

2

11

22

R5

9N

O-P

OP



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

US

B1

_S

H

US

B_

DP

US

B_

DM

US

B1

_S

H

CP

U_1

V8

CP

U_3

V3

DS

K_

3V3

VC

C_5

V

ON

_B

D_

US

B_

DR

V8

ON

_B

D_

US

B_

OV

C8

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5113

42-0

001

Mo

nd

ay,

No

vem

ber

24

, 2

00

87

32

B

OM

AP

-L13

7 E

VM

US

B 1

.0 H

OS

T I

NT

ER

FA

CE

Differential Route 90 ohms

R61

10K

R3

921M

R6

40

.02

C3

70

.01u

F

R60

100K

R1

20

15K

TP

4V

BU

S

C3

50

.00

1uF

OM

AP

L13

7Z

KBU1

-8

US

B1_

VD

DA

33C

1

US

B1_

VD

DA

18C

2U

SB

1_D

MB

3

US

B1_

DP

A3

PT

P9

HE

AD

ER

2

11

22

R6

30

.02

R6

21

0K

U1

4T

PS

2065

D

OU

T1

8IN

12

GN

D1

EN 4

OCn 5

IN2

3O

UT

27

OU

T3

6

C3

81

uF

C3

30

.01

uF

R3

93

15K

J3 US

B-A

co

nn

ect

or

VB

US

1

D-

2

D+

3

GN

D4

S2

5

S1

6C

34

1u

FC

32

0.1

uF

C3

00

.1u

F

R2

23

24

.9 1

%

C27

1.1

uF

U5

6T

PD

2E00

1D

RL

IO1

3IO

25

VCC1 GND 4

NC

.22

+

C2

91

00u

F

E4

NF

M2

1P

C4

74

R1

C3

D1

3

2

C36

0.1

uF

C3

10

.00

1uF

+ C2

81

0uF

C26

30

.1u

F

PT

P10

HE

AD

ER

2

11

22

R3

75

24

.9 1

%

E3

NF

M2

1P

C4

74

R1

C3

D1

3

2

TP

5

VB

US

_O

Cn

1


A-9

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

EM

IFA

_C

LK

EM

IFA

_O

En

EM

IFA

_W

En

_D

QM

0E

MIF

A_

WE

n_

DQ

M1

EM

IFA

_C

S3

n

EM

IFA

_W

En

_D

QM

0

EM

IFA

_WE

n_D

QM

1

EM

IFA

_W

En

EM

IFA

_OE

n

EM

IFA

_C

LK

EM

IFA

_W

En

EM

IFA

_D

9

EM

IFA

_D

11

EM

IFA

_D

12

EM

IFA

_D

13

EM

IFA

_D

10

EM

IFA

_D

15

EM

IFA

_D

14

EM

IFA

_D

8

EM

IFA

_D

0

EM

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B_D

16G

15

EM

B_D

2/G

PIO

6_2

G16

EM

B_D

15/G

PIO

6_15

F13

EM

B_D

29F

14

EM

B_D

30F

15

EM

B_D

0/G

PIO

6_0

F16

EM

B_D

13/G

PIO

6_13

E13

EM

B_D

27E

14

EM

B_D

28E

15

EM

B_D

14/G

PIO

6_14

E16

EM

B_C

S0n

D9

EM

B_A

0/G

PIO

7_2

D10

EM

B_A

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7_6

D11

EM

B_A

8/G

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7_10

D12

EM

B_D

9/G

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6_9

D13

EM

B_D

10/G

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6_10

D14

EM

B_D

11/G

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6_11

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EM

B_D

12/G

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6_12

D16

EM

B_B

A0/

GP

IO7_

1C

9

EM

B_A

1/G

PIO

7_3

C10

EM

B_A

5/G

PIO

7_7

C11

EM

B_A

9/G

PIO

7_11

C12

EM

B_S

DC

KE

C13

EM

B_C

LKC

14

EM

B_W

E_D

QM

1n/G

PIO

5_14

C15

EM

B_D

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6_8

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B_B

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GP

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0B

9

EM

B_A

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7_4

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EM

B_A

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PIO

7_8

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EM

B_A

11/G

PIO

7_13

B12

EM

B_W

E_D

QM

2nB

13

EM

B_D

25B

14

EM

B_A

12/G

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3_13

B15

EM

B_R

AS

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8

EM

B_A

10/G

PIO

7_12

A9

EM

B_A

3/G

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7_5

A10

EM

B_A

7/G

PIO

7_9

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QM

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12

EM

B_D

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13

EM

B_D

26A

14

RN

14

RP

AC

K8

-22

123456789 10 11 12 13 14 15 16

RN

16

RP

AC

K8-

22

1 2 3 4 5 6 7 8910111213141516

R6

2710

K

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52

2

R6

3010

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02

2

RN

17

RP

AC

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1 2 3 4 5 6 7 8910111213141516

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62

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291

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2510

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22

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1 2 3 4 5 6 7 8910111213141516

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72

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1 2 3 4 5 6 7 8910111213141516

R9

12

2

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A-11

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

DS

P_

TR

ST

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DS

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MS

DS

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Da

te:

DW

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of

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ge

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A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5113

42-0

001

Mo

nd

ay,

No

vem

ber

24

, 2

00

810

32

B

OM

AP

-L13

7 E

VM

CP

U J

TA

G/C

LO

CK

S

SD G

oldPa

naso

nic

supe

rcap

R1

080

R1

06N

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Hz

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ST

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U_0

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IH

1

RT

C_X

OH

2

TC

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3

RT

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VD

DG

1

RT

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SS

G2

RE

SE

TG

3

OS

CO

UT

F1

OS

CIN

F2

OS

CV

SS

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12

33

C4

71

8 p

F

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07

100

+

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07

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F

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00

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2

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0

22

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40

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10

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R1

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0

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VC

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2

1 24

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81

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F

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142

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R1

132

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0110

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SW

1

CA

SD

20

TB

1 2 3

4 5 6

R1

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61

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50

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1010

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040

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1M

MB

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148

13

2

C4

91

8 p

F



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

CV

DD

DV

DD

CP

U_

1V

2

CP

U_

3V3

CP

U_

1V

2

AL

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CP

U_1

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CP

U_

1V

2

ALT

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U_

1V2

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

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of

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e:

Pa

ge

Co

nte

nts

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C

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5113

42-0

001

Mo

nd

ay,

No

vem

ber

24

, 2

00

811

32

B

OM

AP

-L13

7 E

VM

CP

U P

OW

ER

PIN

S

L24

BLM

G1P

500S

PT

PT

P1

HE

AD

ER

2

11

22

R1

150

.02

5

L25

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G1P

500S

PT

PT

P3

HE

AD

ER

2

11

22

R1

17N

O-P

OP

C5

21

uF

R1

180

.02

C27

20

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uF

PT

P4

HE

AD

ER

2

11

22

C5

50

.00

1u

FC

54

0.1

uF

R1

19

0.0

2

PT

P5

HE

AD

ER

2

11

22

PT

P6

HE

AD

ER

2

11

22

C5

80.

01

uF

C5

60

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R1

160

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TP6

TE

ST

PO

INT

1

OM

AP

L13

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U1

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DD

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1

DV

DD

.2R

16

DV

DD

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5

DV

DD

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8

DV

DD

.5M

9

DV

DD

.6M

12

DV

DD

.7L5

CV

DD

.1L6

DV

DD

.8L1

1

DV

DD

.9L1

2

DV

DD

.10

K5

CV

DD

.2K

6

CV

DD

.3K

7

CV

DD

.4K

10

CV

DD

.5K

11

DV

DD

.11

K12

CV

DD

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CV

DD

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CV

DD

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0

CV

DD

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1

CV

DD

.10

J12

RV

DD

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6

CV

DD

.11

H7

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DD

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H10

CV

DD

.13

H11

RV

DD

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12

DV

DD

.12

G5

CV

DD

.14

G6

CV

DD

.15

G7

CV

DD

.16

G10

CV

DD

.17

G11

DV

DD

.13

G12

DV

DD

.14

F5

CV

DD

.18

F6

RS

V1

F7

DV

DD

.15

F11

DV

DD

.16

F12

PLL

0_V

SS

AE

1

DV

DD

.17

E5

DV

DD

.18

E8

DV

DD

.19

E9

DV

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E12

PLL

0_V

DD

AD

1

RS

V2

B1

DV

DD

.21

B16

C5

70

.1u

F

C53

0.0

1uF


A-13

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5113

42-0

001

Mo

nd

ay,

No

vem

ber

24

, 2

00

812

32

B

OM

AP

-L13

7 E

VM

L1

37

GR

OU

ND

PIN

S

OM

AP

L1

37Z

KB

U1-

1

VS

S.2

9T

1

VS

S.3

0T

2

VS

S.3

1T

15

VS

S.3

2T

16

VS

S.2

5M

6

VS

S.2

6M

7

VS

S.2

7M

10

VS

S.2

8M

11

VS

S.2

1L7

VS

S.2

2L8

VS

S.2

3L9

VS

S.2

4L1

0

VS

S.1

7K

8

VS

S.1

8K

9

VS

S.1

9J8

VS

S.2

0J9

VS

S.1

H8

VS

S.2

H9

VS

S.3

G8

VS

S.4

G9

VS

S.5

F8

VS

S.6

F9

VS

S.7

F10

VS

S.8

E6

VS

S.9

E7

VS

S.1

0E

10

VS

S.1

1E

11

VS

S.1

2B

2

VS

S.1

3A

1

VS

S.1

4A

2

VS

S.1

5A

15

VS

S.1

6A

16



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

CV

DD

CV

DD

DV

DD

DV

DD

DV

DD

CV

DD

DV

DD

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5113

42-0

001

Mo

nd

ay,

No

vem

ber

24

, 2

00

813

32

B

OM

AP

-L13

7 E

VM

L1

37

DE

CO

UP

LIN

G C

AP

AC

ITO

RS

C8

40

.1u

F

C7

40

.1u

F

C6

10

.1u

F

+C

71

33

uF

+C

10

33

3uF

C7

80

.1u

FC

79

0.1

uFC

87

0.1

uF

C8

90

.1uF

+C

100

33

uF

+C

72

33

uF

C9

60

.1u

F

+C

70

33

uF+

C6

93

3u

FC

75

0.1

uF

C7

60

.1u

F

C6

40

.1u

F

+C

10

13

3u

F

C6

70

.1uF

C8

80

.1u

FC

97

0.1

uF

C8

00

.1u

F

C9

50

.1u

F

C9

90

.1uF

C9

10.

1u

F

C9

80

.1u

F

C8

60

.1u

F

C7

70

.1u

F

C6

30

.1u

FC

60

0.1

uF

C6

20

.1u

F

C7

30

.1u

F

C9

20

.1uF

C8

10.

1u

F

+C

10

23

3uF

C6

60

.1u

F

C9

30

.1u

F

C8

50

.1u

F

C6

80

.1u

F

C9

40

.1u

F

C5

90

.1u

F

C8

30

.1u

F

C9

00

.1u

F

C8

20

.1uF

C65

0.1

uF


A-15

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

DS

K_3

V3

DS

K_

3V

3

DS

K_

3V3

DS

K_3

V3

SE

L_E

NE

Tn_

MC

AS

P0

3,2

7S

EL_

EX

P2_

TIM

ER

4,2

8S

EL_

EX

P2_

UA

RT

14

,28

ON

_B

D_

OF

F_

BD

6,8

BO

OT

MO

DE

[1]

4,1

6B

OO

TM

OD

E[0

]4

,16

BO

OT

MO

DE

[2]

4,1

6B

OO

TM

OD

E[7

]4

,5

EX

P3_

SE

L_M

EM

D8_

D1

18,

29

EX

P3

_SE

L_M

EM

D12

_D

15

8,2

9

BO

OT

MO

DE

[3]

4,1

6

BO

OT

_D

ISA

BLE

2,3

,16

,19

,31

CP

U_

RE

SE

T1

0,3

1

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

D

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5113

42-0

001

Mo

nd

ay,

No

vem

ber

24

, 2

00

814

32

B

OM

AP

-L13

7 E

VM

BO

OT

MO

DE

S

BOOTMODE0 - INTERNAL PD IMPLEMENTED



BOOTMODE3 - INTERNAL PU IMPLEMENTED

BOOTMODE4 - INTERNAL PU DONE






BOOTMODE10 - INTERNAL PD DONE

BOOTMODE11 - INTERNAL PD DONE





R1

22

2K

R1

25

2K

R128 20K

1 2 3 4 5 6SW

2

DIP

_S

WIT

CH

_6

1 2 3 4 5 67891012 11

R1

21

2K

R3

79

100

R3

76

100

R3

85

100

R1

26

2K

1 2 3 4 5 6SW

5

DIP

_S

WIT

CH

_6

1 2 3 4 5 67891012 11

R130 20K

R3

77

100

R3

86

100

R124 20K

R1

23

2K

R127 20K

U6

0S

N74

LV

C1G

125

3

4

5

2

1

C27

30

.1u

F

R3

78

100

U6

1 1G08

1 24

5 3

C27

40

.1u

F

R129 20K



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

EM

IFB

_A2

EM

IFB

_A4

EM

IFB

_A6

EM

IFB

_A0

EM

IFB

_A5

EM

IFB

_A3

EM

IFB

_A1

EM

IFB

_A7

EM

IFB

_A

12

EM

IFB

_A

10

EM

IFB

_A8

EM

IFB

_A

11

EM

IFB

_A9

EM

IFB

_BA

1E

MIF

B_B

A0

EM

IFB

_S

DC

KE

EM

IFB

_WE

n

EM

IFB

_R

AS

nE

MIF

B_

CA

Sn

EM

IFB

_C

LK

EM

IFB

_C

S0n

EM

IFB

_W

En_

DQ

M0

EM

IFB

_W

En_

DQ

M1

EM

IFB

_A2

EM

IFB

_A4

EM

IFB

_A6

EM

IFB

_A0

EM

IFB

_A5

EM

IFB

_A3

EM

IFB

_A1

EM

IFB

_A7

EM

IFB

_A1

2

EM

IFB

_A1

0

EM

IFB

_A8

EM

IFB

_A1

1

EM

IFB

_A9

EM

IFB

_BA

1E

MIF

B_B

A0

EM

IFB

_S

DC

KE

EM

IFB

_WE

n

EM

IFB

_R

AS

nE

MIF

B_

CA

Sn

EM

IFB

_CLK

EM

IFB

_C

S0n

M_

EM

IFB

_D2

3M

_E

MIF

B_D

22

M_

EM

IFB

_D2

1M

_E

MIF

B_D

20

M_

EM

IFB

_D1

9M

_E

MIF

B_D

18

M_

EM

IFB

_D1

7M

_E

MIF

B_D

16

EM

IFB

_WE

n_D

QM

2E

MIF

B_W

En

_DQ

M3

M_

EM

IFB

_D2

3

M_

EM

IFB

_D1

6

M_

EM

IFB

_D1

7M

_E

MIF

B_D

18

M_

EM

IFB

_D1

9M

_E

MIF

B_D

20

M_

EM

IFB

_D2

2M

_E

MIF

B_D

21

DS

K_

3V3

DS

K_3

V3

EM

IFB

_A7

9

EM

IFB

_B

A0

9E

MIF

B_

BA

19

EM

IFB

_A0

9E

MIF

B_A

19

EM

IFB

_A2

9E

MIF

B_A

39

EM

IFB

_A4

9E

MIF

B_A

59

EM

IFB

_A6

9

EM

IFB

_A8

9E

MIF

B_A

99

EM

IFB

_A

109

EM

IFB

_A

119

EM

IFB

_A

129

EM

IFB

_C

S0n

9

EM

IFB

_CA

Sn

9E

MIF

B_R

AS

n9

EM

IFB

_C

LK

9EM

IFB

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DC

KE

9E

MIF

B_

WE

n9

EM

IFB

_WE

n_D

QM

19

EM

IFB

_WE

n_D

QM

09

EM

IFB

_WE

n_D

QM

39

EM

IFB

_WE

n_D

QM

29

EM

IFB

_D

13

9E

MIF

B_

D1

49

EM

IFB

_D

15

9

EM

IFB

_D

09

EM

IFB

_D

19

EM

IFB

_D

29

EM

IFB

_D

39

EM

IFB

_D

49

EM

IFB

_D

59

EM

IFB

_D

69

EM

IFB

_D

79

EM

IFB

_D

89

EM

IFB

_D

99

EM

IFB

_D

10

9E

MIF

B_

D1

19

EM

IFB

_D

12

9E

MIF

B_

D29

9E

MIF

B_

D30

9E

MIF

B_

D31

9

EM

IFB

_D

249

EM

IFB

_D

259

EM

IFB

_D

269

EM

IFB

_D

279

EM

IFB

_D

289 E

MIF

B_

D21

9E

MIF

B_

D22

9

EM

IFB

_D

239

EM

IFB

_D

169

EM

IFB

_D

179

EM

IFB

_D

189

EM

IFB

_D

199

EM

IFB

_D

209

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5113

42-0

001

Mo

nd

ay,

No

vem

ber

24

, 2

00

815

32

B

OM

AP

-L13

7 E

VM

SD

RA

M -

EM

IF B

RN

19

RP

AC

K8

-10

1 2 3 4 5 6 7 8910111213141516

C1

12

0.1

uF

C1

08

0.1

uF

+C

10

422

uF

C1

09

0.1

uF

C1

13

0.1

uF

C1

18

0.1

uF

C1

20

0.1

uF

RN

22

RP

AC

K8

-10

1 2 3 4 5 6 7 8910111213141516

RN

20

RP

AC

K8-

101 2 3 4 5 6 7 8

910111213141516

RN

21

RP

AC

K8

-10

1 2 3 4 5 6 7 8910111213141516

C1

06

0.1

uF

U2

1

IS4

2S1

616

0B-6

BL

DQ

0A

8D

Q1

B9

DQ

2B

8D

Q3

C9

DQ

4C

8D

Q5

D9

DQ

6D

8D

Q7

E9

A0

H7

A1

H8

A2

J8

A3

J7

A4

J3

A5

J2

A6

H3

A7

H2

A8

H1

A9

G3

A10

H9

A11

G2

BA

0G

7

BA

1G

8

CS

G9

RA

SF

8C

AS

F7

WE

F9

DQ

ML

E8

NC

E2

DQ

MH

F1

CLK

F2

CK

EF

3

A12

G1

DQ

15A

2

DQ

14B

1

DQ

13B

2

DQ

12C

1

DQ

11C

2

DQ

10D

1

DQ

9D

2

DQ

8E

1

VD

DQ

.4D

3V

DD

Q.3

C7

VD

DQ

.2B

3V

DD

Q.1

A7

VD

D.1

A9

VD

D.3

J9V

DD

.2E

7V

SS

.1A

1

VS

S.2

E3

VS

S.3

J1

VS

SQ

.1A

3

VS

SQ

.2B

7

VS

SQ

.3C

3

VS

SQ

.4D

7

C1

19

0.1

uF

C1

11

0.1

uF

C1

16

0.1

uF

+C

10

52

2 u

FC

107

0.1

uF

+C

115

22

uF

C1

21

0.1

uF

U2

2

IS42

S16

160

B-6

BL

DQ

0A

8D

Q1

B9

DQ

2B

8D

Q3

C9

DQ

4C

8D

Q5

D9

DQ

6D

8D

Q7

E9

A0

H7

A1

H8

A2

J8

A3

J7

A4

J3

A5

J2

A6

H3

A7

H2

A8

H1

A9

G3

A10

H9

A11

G2

BA

0G

7

BA

1G

8

CS

G9

RA

SF

8C

AS

F7

WE

F9

DQ

ML

E8

NC

E2

DQ

MH

F1

CLK

F2

CK

EF

3

A12

G1

DQ

15A

2

DQ

14B

1

DQ

13B

2

DQ

12C

1

DQ

11C

2

DQ

10D

1

DQ

9D

2

DQ

8E

1

VD

DQ

.4D

3V

DD

Q.3

C7

VD

DQ

.2B

3V

DD

Q.1

A7

VD

D.1

A9

VD

D.3

J9V

DD

.2E

7V

SS

.1A

1

VS

S.2

E3

VS

S.3

J1

VS

SQ

.1A

3

VS

SQ

.2B

7

VS

SQ

.3C

3

VS

SQ

.4D

7

C11

0

0.1

uF

C1

17

0.1

uF

+C

114

22

uF


A-17

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

SP

I_W

P

RO

M_

SP

I0_

CS

0SP

I_H

OL

DR

OM

_S

PI0

_C

LK

RO

M_S

PI0

_SIM

O

RO

M_S

PI0

_SO

MI

RO

M_

SP

I0_C

LK

RO

M_

SP

I0_

SO

MI

RO

M_

SP

I0_

SIM

OR

OM

_S

PI0

_CS

0

I2C

0_S

DA

I2C

0_S

CL

DS

K_

3V3

DS

K_3

V3

DS

K_

3V3

DS

K_3

V3

DS

K_3

V3

DS

K_3

V3

DS

K_

3V

3

DS

K_3

V3

DS

K_

3V3

SP

I0_

CL

K4

,14

SP

I0_

SO

MI

4,1

4 SP

I0_

SIM

O4

,14

SP

I0_

SC

Sn

4

SE

L_E

XP

2_Q

EP

028

EQ

EP

0A2

8

EX

P2

.SP

I0_C

LK28

EX

P2.

SP

I0_S

OM

I28

EQ

EP

0B2

8E

XP

2.S

PI0

_SIM

O28

SP

I0_

EN

An

4,1

4

BO

OT

_DIS

AB

LE

2,3

,14

,19

,31B

OO

T_D

ISA

BL

En

,5,8

,19

,27

,31

I2C

0_

SC

L4

,22

,24

,27

,28,

30

I2C

0_

SD

A4

,22

,24

,27

,28,

30

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5113

42-0

001

Mo

nd

ay,

No

vem

ber

24

, 2

00

816

32

B

OM

AP

-L13

7 E

VM

SP

I R

OM

R1

43N

O-P

OP

R1

38

NO

-PO

P

C1

25

.1u

F

U2

5S

N7

4LV

C1

G3

2D

CK

RG

4

1 2

3

4

5

R1

37

2K

C1

24

.1u

F

U24

SN

74C

BT

LV3

384P

W

1OE

1

2OE

13

1A1

3

1A2

4

1A3

7

1A4

8

1A5

11

1B1

2

1B2

5

1B3

6

1B4

9

1B5

10

2A1

14

2A2

17

2A3

18

2A4

21

2A5

22

Vcc

24

GN

D12

2B1

15

2B2

16

2B3

19

2B4

20

2B5

23

R1

3510

K

R1

420

C1

22

0.1

uF

R1

341

0K

R1

31

10K

R1

3310

K

R1

41

0

R1

39N

O-P

OP

U2

3

W25

X32

VS

FIG

CS

7

DIO

15

GN

D10

VC

C2

HO

LD1

WP

9D

O8

SC

LK16

NC

.33

NC

.44

NC

.55

NC

.66

NC

.11

11

NC

.12

12

NC

.13

13

NC

.14

14

C1

230

.1u

F

R14

0N

O-P

OP

C1

26

.1uF

U2

6S

N7

4L

VC

1G

00

DC

KR

G4

1 2

3

4

5

U2

7 24

WC

256

A0

1V

CC

8

VS

S4

NC

3S

CL

6

SD

A5

A1

2W

P7

R1

3610

K

R1

32

10K



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

DS

K_3

V3

DS

K_3

V3

US

ER

_S

W1

8U

SE

R_

SW

28

US

ER

_S

W3

8U

SE

R_

SW

48

US

ER

_L

ED

18

US

ER

_L

ED

28

US

ER

_L

ED

38

US

ER

_L

ED

48

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5113

42-0

001

Mo

nd

ay,

No

vem

ber

24

, 2

00

817

32

B

OM

AP

-L13

7 E

VM

US

ER

SW

ITC

HE

S L

ED

S

SILKSCREEN:

USER SWITCHES

USER CONTROLLED LEDS

R14

533

0

RN

24

RP

AC

K4

-1K1234

5 6 7 8

RN

23

RP

AC

K4

-10K

1234 5

678

R1

47

330

R1

4433

0R

146

330

DS

3L

ED

_G

RN

DS

4L

ED

_G

RN

SW

3

LO

W P

RO

FIL

E D

IP-4

1 2 3 4

8 7 6 5

DS

1L

ED

_G

RN

DS

2L

ED

_G

RN


A-19

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

UA

RT

2_T

XD

UA

RT

2_

RX

D

DS

K_

3V3

DS

K_3

V3

DS

K_

3V3

GN

D_E

_RS2

32

GN

D_E

_RS2

32

GN

D_E

_RS2

32

GN

D_E

_RS

232

GN

D_E

_RS

232

GN

D_E

_RS2

32

UA

RT

2_T

XD

5

UA

RT

2_R

XD

5

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5113

42-0

001

Mo

nd

ay,

No

vem

ber

24

, 2

00

818

32

B

OM

AP

-L13

7 E

VM

RS

232

SILKSCREEN:

UART

L31

uH

C1

301

0pF

R1

5010

K

L2

BL

M2

1PG

221

SN

1D

C1

321

0pF

P1D

B9

M

5 9 4 8 3 7 2 6 1

10 11

R1

49

10K

+C

12

81

0u

F

C1

34

1u

F

C1

35

1u

F

U2

8

MA

X32

21C

PW

RG

4

T_I

N11

R_O

UT

9

VC

C15

GN

D14

V+

3

V-

7

C1+

2

C1-

4

C2+

5

C2-

6

FO

RC

EO

N12

FO

RC

EO

FF

16

R_I

N8

T_O

UT

13

EN

1IN

VA

LID

10

C1

271

uF

C12

91

0p

F

C1

331

uF

L5

BL

M2

1PG

221

SN

1D

R1

48

10K C

131

10

pF

C1

36

1u

F

L41

uH



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

EM

IFA

_D0

EM

IFA

_D7

EM

IFA

_D1

EM

IFA

_D3

EM

IFA

_D4

EM

IFA

_D5

EM

IFA

_D2

EM

IFA

_D6

EM

IFA

_A

2

EX

P_E

MIF

A_

D0

EX

P_E

MIF

A_

D7

EX

P_E

MIF

A_

D1

EX

P_E

MIF

A_

D3

EX

P_E

MIF

A_

D4

EX

P_E

MIF

A_

D5

EX

P_E

MIF

A_

D2

EX

P_E

MIF

A_

D6

EX

P_E

MIF

A_A

2

EM

IFA

_A

1

EX

P_E

MIF

A_A

1

DS

K_

3V

3

DS

K_3

V3

DS

K_3

V3

EM

IFA

_D

08

EM

IFA

_D

18

EM

IFA

_D

28

EM

IFA

_D

38

EM

IFA

_D

48

EM

IFA

_D

58

EM

IFA

_D

68

EM

IFA

_D

78

EM

IFA

_A2

8

EX

P_

EM

IFA

_D0

29E

XP

_E

MIF

A_D

129

EX

P_

EM

IFA

_D2

29E

XP

_E

MIF

A_D

329

EX

P_

EM

IFA

_D4

29E

XP

_E

MIF

A_D

529

EX

P_

EM

IFA

_D6

29E

XP

_E

MIF

A_D

729

EX

P_

EM

IFA

_A2

29

MM

C_S

D_

CM

D20

MM

C_

SD

_DA

TA

020

MM

C_

SD

_DA

TA

120

MM

C_

SD

_DA

TA

420

MM

C_

SD

_DA

TA

520

MM

C_

SD

_DA

TA

620

MM

C_

SD

_DA

TA

720

BO

OT

_DIS

AB

LE2

,3,1

4,1

6,3

1

BO

OT

_D

ISA

BL

En

2,3

,4,5

,8,1

6,2

7,3

1

EX

P3_

SE

L_M

EM

D0_

72

9

MM

C_S

D_C

LK

20E

MIF

A_A

18

MM

C_S

D_W

P20

MM

C_

SD

_IN

S20

EM

IFA

_CS

4n8

EM

IFA

_CS

5n8

EX

P_

EM

IFA

_A1

29

EX

P_E

MIF

A_

CS

4n29

EX

P_E

MIF

A_

CS

5n29

MM

C_

SD

_DA

TA

320

MM

C_

SD

_DA

TA

220

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

B

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5113

42-0

001

Mo

nd

ay,

No

vem

ber

24

, 2

00

819

32

B

OM

AP

-L13

7 E

VM

SD

/MM

C C

AR

D M

UX

ING

FUNCTION TABLE

INPUTS INPUTS/OUTPUTS FUNCTION

S2 S1 S0 A1 A2

L L L Z Z Disconnect

L L H B1 Z A1 port = B1 port

L H L B2 Z A1 port = B2 port

L H H Z B1 A2 port = B1 port

H L L Z B2 A2 port = B2 port

H L H Z Z Disconnect

H H L B1 B2 A1 port = B1 port/A2 port = B2 port

H H H B2 B1 A1 port = B2 port/ A2 port = B1 port

U2

9 1G

08

1 24

5 3

C13

70

.1u

F

R1

533

60

C1

39

0.1

uF

R1

51

2K

C1

40.0

1u

FU

31

SN

74C

BT

LV

1621

2D

GG

R

S1

56

GN

D.2

19

1A1

2

11A

125

1B1

54

1B2

53

GN

D.1

8

VC

C.1

17

GN

D.3

38

GN

D.4

49

S2

55

2A1

4

3A1

6

4A1

9

5A1

11

6A1

13

7A1

15

8A1

18

9A1

21

10A

123

12A

127

1A2

3

2A2

5

3A2

7

4A2

10

5A2

12

6A2

14

7A2

16

8A2

20

S0

1

2B1

52

3B1

50

9B1

36

4B1

47

5B1

45

6B1

43

7B1

41

8B1

39

10B

134

2B2

51

3B2

48

4B2

46

5B2

44

6B2

42

7B2

40

8B2

37

11B

231

12B

229

9A2

22

10A

224

11A

226

12A

228

11B

132

12B

130

9B2

35

10B

233

C13

80

.1u

F

U3

0 1g02

1 24

5 3


A-21

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

MM

C_

SD

_D

AT

A0

MM

C_

SD

_D

AT

A6

MM

C_

SD

_D

AT

A5

MM

C_

SD

_D

AT

A4

MM

C_S

D_C

LK

MM

C_

SD

_D

AT

A2

MM

C_

SD

_D

AT

A3

MM

C_

SD

_D

AT

A1

MM

C_S

D_

CM

D

MM

C_

SD

_D

AT

A7

DS

K_3

V3

DS

K_

3V3

DS

K_3

V3

DS

K_

3V

3D

SK

_3

V3

MM

C_S

D_

CL

K19

MM

C_

SD

_C

MD

19

MM

C_

SD

_DA

TA

21

9

MM

C_

SD

_DA

TA

31

9

MM

C_

SD

_DA

TA

01

9M

MC

_S

D_D

AT

A1

19

MM

C_

SD

_DA

TA

41

9M

MC

_S

D_D

AT

A5

19

MM

C_

SD

_DA

TA

61

9M

MC

_S

D_D

AT

A7

19

MM

C_

SD

_WP

19M

MC

_S

D_I

NS

19

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5113

42-0

001

Mo

nd

ay,

No

vem

ber

24

, 2

00

820

32

B

OM

AP

-L13

7 E

VM

SD

/MM

C C

AR

D I

NT

ER

FA

CE

SD

/MM

C C

on

nec

tor

6 in

1M

MC

+, M

MC

Mo

bile

, SD

,M

MC

, min

iSD

, RS

-MM

C

R1

65N

O-P

OP

R1

671

0K

U3

3 TP

D6

E0

01R

SE

IO1

1

IO2

2

IO3

3

IO4

6

IO5

7

IO6

8

VCC10 GND 5

NC

.44

NC

.99

R1

625

1KR

160

51K

R1

585

1K

U3

2 TP

D6

E0

01R

SE

IO1

1

IO2

2

IO3

3

IO4

6

IO5

7

IO6

8

VCC10 GND 5

NC

.44

NC

.99

R1

57

51K

+C

141

10

UF

P2

MH

C-W

21-6

01

#1_M

MC

+/M

MC

M/R

SM

MC

/MM

C/S

D1

#2_M

MC

+/M

MC

M/R

SM

MC

/MM

C/S

D2

#3_M

MC

+/M

MC

M/R

SM

MC

/MM

C/S

D3

#4_M

MC

+/M

MC

M/R

SM

MC

/MM

C/S

D4

#5_M

MC

+/M

MC

M/R

SM

MC

/MM

C/S

D5

#6_M

MC

+/M

MC

M/R

SM

MC

/MM

C/S

D6

#7_M

MC

+/M

MC

M/R

SM

MC

/MM

C/S

D7

#8_M

MC

+/M

MC

M/S

D8

SD

_WP

14

CD

15

GN

D1

27

GN

D2

28

#10_

MM

C+/

MM

CM

10

#1_m

iniS

D16

#2_m

iniS

D17

#3_m

iniS

D18

#4_m

iniS

D19

#5_m

iniS

D20

#6_m

iniS

D21

#7_m

iniS

D22

#8_m

iniS

D23

#9_m

iniS

D24

#10_

min

iSD

25

#11_

min

iSD

26

#9_M

MC

+/M

MC

M/S

D9

#11_

MM

C+/

MM

CM

11

#12_

MM

C+/

MM

CM

12

#13_

MM

C+/

MM

CM

13

R1

555

1K

R1

6810

K

R1

595

1KR

15

65

1K

C1

42

0.1

uF

R1

61

51K

R1

64

NO

-PO

PR

16

6N

O-P

OP

R1

63

51K

R1

54

51K



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

JTAG_TCK

JTAG_RTCK

JTA

G_T

DI

JTA

G_T

DO

JTA

G_T

CK

JTA

G_T

RS

Tn

JTA

G_T

MS

JTAG_TMS

JTAG_TDO

JTAG_TRSTn

JTA

G_R

TC

K

JTA

G_E

MU

0

JTA

G_T

RS

Tn

JTA

G_T

DI

JTA

G_T

DO

GN

D

JTA

G_

EM

U1

DS

P_

TC

K

EM

U_S

TS

T_T

CK

JTA

G_T

CK

JTA

G_T

MS

T_T

CK

_RE

TD

SP

_R

TC

K

JTA

G_

EM

U0

T_E

MU

0D

SP

_E

MU

0

DS

P_

EM

U1

EM

U_S

TS

AR

M_R

ST

n

JTA

G_

RT

CK

T_T

MS

T_T

DO

T_T

DI

T_T

CK

T_T

CK

_RE

T

T_E

MU

1T

_EM

U0

T_T

RS

Tn

EM

U_S

TS

T_T

MS

T_T

RS

Tn

DS

P_T

MS

JTA

G_

TR

ST

nD

SP

_T

RS

T#

T_E

MU

1

JTAG_TDI

T_T

DO

JTA

G_T

DO

DS

P_

TD

O

DS

P_

TD

IT

_TD

I

JTA

G_

EM

U1

JTA

G_T

DI

JTA

G_T

MS

JTA

G_T

CK

JTA

G_R

TC

K

DS

K_

3V3

DS

K_

3V3

DS

K_3

V3

DS

K_3

V3

DS

K_3

V3

DS

K_3

V3

DS

K_3

V3

DS

K_3

V3

DS

K_

3V3

DS

K_3

V3

DS

K_

3V3

VC

C_

5V

DS

K_3

V3

DS

K_

3V

3

PO

NR

Sn

IN31

XR

Sn

31

DS

P_

RT

CK

10

DS

P_E

MU

010

AR

M_R

ST

n31

DS

P_T

CK

10

DS

P_T

MS

10

DS

P_

TR

ST

#10

DS

P_T

DI

10

DS

P_T

DO

10

DS

P_E

MU

110

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5113

42-0

001

Mo

nd

ay,

No

vem

ber

24

, 2

00

821

32

B

OM

AP

-L13

7 E

VM

TI1

4 P

IN/A

RM

20

PIN

JT

AG

EM

UL

AT

ION

JTAG MULTIPLEXERS

R1

71

33

C1

450

.1u

F

TP

35 TP1

U3

7

SN

74

AH

C1

G1

4D

CK

RG

4

3

4

5

2 1

U3

4

SN

74C

BT

LV

3257

PW

R

1A4

4B1

14

2A7

3B1

11

3A9

4A12

4B2

13

S1

1B1

2

OE

15

3B2

10

1B2

3

2B1

5

2B2

6

VC

C16

GN

D8

C14

4N

O P

OP

TP

36 TP1

U3

5

SN

74

LVC

1G3

2

1 24

5 3

R1

72

1.5

K

TP

37 TP1

R1

78

NO

-PO

P

C2

50

.1u

F

C1

46.1

uF

C1

49

.1 u

F

R3

80

0

J5

SA

MT

EC

-TS

M-1

10-

DV

1 3 5 7 9 11 13 15 17 19

2 4 6 8 10 12 14 16 18 20

R1

760

TP

38 TP1

R1

69

10K J4 14

Pin

Em

ula

tion

He

ader

TM

S1

TR

ST

n2

TD

I3

GN

D.1

4

TV

D5

GN

D.2

6

TD

O7

GN

D.3

8

RT

CK

9G

ND

.410

TC

K11

GN

D.5

12

EM

U0

13E

MU

114

R3

81

0

DS

5

Gre

en

U5

7

SN

74

LVC

1G

04

3

4

5

2 1

R1

77

0

C1

43

0.1

uF

R1

731

50

R3

82

0

US

B1

Em

bed

ded_

US

B

GN

D

3.3V

T_T

CK

_RE

TT

_TC

K

T_T

MS

T_T

DI

T_T

DO

T_E

MU

0T

_EM

U1

T_T

RS

Tn

DS

P_R

S_O

UT

_OD

n

RE

SE

T_I

Nn

5V

T_I

O_P

OW

ER

ON

n

T_T

PD

T_A

IN0

T_A

IN1

T_A

IN2

T_A

IN3

R17

910

K

C14

80

.1u

FR

174

10K

R3

830

R1

7510

K

U3

6

SN

74

CB

TL

V3

257P

WR

1A4

4B1

14

2A7

3B1

11

3A9

4A12

4B2

13

S1

1B1

2

OE

15

3B2

10

1B2

3

2B1

5

2B2

6

VC

C16

GN

D8

C1

47

0.1

uF

R17

0N

O P

OP


A-23

AIC

_D

OU

TA

IC_

DIN

AIC

_B

CL

KA

IC_

WC

LK

MIC

_BIA

S_H

S

DS

K_

3V

3

VC

C_

1V

8

DS

K_

3V3

DS

K_

3V3

GN

D_A

IC

GN

D_A

IC

GN

D_A

ICG

ND

_AIC

GN

D_A

IC

GN

D_A

IC

GN

D_A

IC

GN

D_A

IC

GN

D_A

ICG

ND

_AIC

GN

D_A

IC

GN

D_A

ICG

ND

_AIC

GN

D_A

IC

GN

D_A

IC

GN

D_A

IC

DS

K_3

V3

GN

D_A

IC

DS

K_3

V3

DS

K_

3V

3

AIC

3106

_RE

SE

Tn

31

T_

AIC

_WC

LK2

T_

AIC

_BC

LK

2

T_

AIC

_D

IN2

T_

AIC

_D

OU

T2

I2C

0_

SD

A4

,16

,24

,27

,28,

30

I2C

0_

SC

L4

,16

,24

,27

,28,

30

T_

AIC

_MC

LK2

MIC

_B

IAS

_H

S2

3

HA

ND

SE

T_M

IC_

P23

HA

ND

SE

T_

MIC

_N

23

HE

AD

SE

T_M

IC_P

23

HE

AD

SE

T_

MIC

_N

23

HE

AD

SE

T_S

PK

R_

P23

HE

AD

SE

T_

SP

KR

_N

23

HA

ND

SE

T_S

PK

R_

P23

HA

ND

SE

T_

SP

KR

_N

23

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

B

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5113

42-

0001

Mo

nd

ay,

No

vem

ber

24

, 20

08

2232

B

OM

AP

-L13

7 E

VM

AIC

31

06

AU

DIO

IN

TE

RF

AC

E

ISOLATE GROUNDS

AND CONNECT AT

SINGLE LOCATION

IN THE GROUND PLANE

R2

04

NO

-PO

P

TP

7T

ES

T P

OIN

T1

R1

8747

K

R1

99N

O-P

OP

L7B

LM2

1PG

221

SN

1D

C1

60

1u

F

TP

10T

ES

T P

OIN

T1

R2

03

NO

-PO

P

+

C1

551

0u

F

TP

11T

ES

T P

OIN

T1

R2

0922

C1

61

22

0pF

TP

40T

ES

T P

OIN

T1

C1

57

.1u

F

+

C1

741

0u

F,6

.3V

R1

9320

K

R1

910

TP

39T

ES

T P

OIN

T1

C1

66

.1u

F

C1

54.1

uF

C1

65

.1u

F

R1

80

5.6

K

C1

53.1

uF

TP

9T

ES

T P

OIN

T1

R1

9510

R1

9610

R2

1022

C1

712

20p

F

+

C1

683

3uF

,6.3

V

TP

12T

ES

T P

OIN

T1

R2

08

2K

R2

06

2K

L10

BLM

21P

G2

21S

N1D

R2

02

20K

R18

620

K

C15

6.1

uF

C16

4.1

uF

TP

8T

ES

T P

OIN

T1

+

C1

693

3uF

,6.3

VP

4

Mic

In 3 4 2 1

56

C17

2.1

uF

C1

63

.1u

F

R1

84

330

R1

82

5.6

K

P5

Hea

dph

one

Out

3421

56

L6

BL

M21

PG

221

SN

1D

R1

81

5.6

K

R2

01N

O-P

OP

C17

0.1

uF

P6

Lin

e O

ut

3421

56

R1

92

20K

P3L

ine

In

3 4 2 1

56

L11

BL

M2

1PG

22

1SN

1D

L12

BL

M2

1PG

22

1SN

1D

R1

83

5.6

K

C15

2.1

uF

+

C1

621

0u

F

L14

BL

M21

PG

221

SN

1D

+

C1

50

10u

F

L8

BL

M21

PG

221

SN

1D

R1

883

30

R1

85

20K

R2

00

NO

-PO

P

R1

89

10K

R1

98

NO

-PO

P

R1

9410

R2

05N

O-P

OP

C1

75

.1u

F

C1

58

.1u

F

L13

BL

M21

PG

221

SN

1D

L9B

LM21

PG

221

SN

1D

R1

9710

C1

59

.1uF

+

C1

731

0u

F,6

.3V

U3

9

24.

576

MH

z

VC

C4

OU

T3

GN

D2

EN

1

U38

TV

L320

AIC

3106

HP

LOU

T18

HP

LCO

M19

LIN

E1L

-4

LIN

E1R

+5

MIC

BIA

S13

WC

LK39

DO

UT

41

MC

LK37

SD

A2

RIG

HT

_LO

+31

LEF

T_L

O+

29

LEF

T_L

O-

30

DIN

40

LIN

E2L

+7

LIN

E1R

-6

HP

RC

OM

22H

PR

OU

T23

LIN

E2L

-8

DR

VD

D.1

16

DR

VD

D.2

17

AV

DD

_DA

C25

AV

SS

_AD

C15

AV

SS

_DA

C26

RE

SE

T33

DR

VD

D.3

24

DV

SS

42

IOV

DD

44

RIG

HT

_LO

-32

SC

L1

LIN

E1L

+3

BC

LK38

TPAD 49

MIC

3R14

MIC

3L11

DV

DD

.136

DR

VS

S.1

20

DR

VS

S.2

21

MO

NO

_LO

+27

MO

NO

_LO

-28

GP

IO2

34G

PIO

135

SE

LEC

T43

MF

P0

45

MF

P1

46

MF

P2

47

MF

P3

48

MIC

DE

T12

LIN

E2R

+9

LIN

E2R

-10

R2

072K

R1

900

C1

67

22

0pF

C1

51

.1uF



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

MIC

_B

IAS

_H

S

MIC

_B

IAS

_H

S

MIC

_B

IAS

_HS

MIC

_B

IAS

_HS

GN

D_A

IC

GN

D_A

IC

GN

D_A

ICG

ND

_AIC

GN

D_A

IC

GN

D_A

IC

VC

C_

5V

GN

D_A

ICG

ND

_AIC

GN

D_A

IC

GN

D_A

IC

GN

D_A

IC

MIC

_B

IAS

_H

S22 MIC

_B

IAS

_H

S2

2

HA

ND

SE

T_

MIC

_P

22

HA

ND

SE

T_

MIC

_N22

HA

ND

SE

T_

SP

KR

_P2

2

HA

ND

SE

T_

SP

KR

_N

22

HE

AD

SE

T_M

IC_

P22

HE

AD

SE

T_

MIC

_N22

HE

AD

SE

T_S

PK

R_P

22H

EA

DS

ET

_S

PK

R_

N22

MIC

_B

IAS

_H

S22 MIC

_B

IAS

_H

S22

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

B

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5113

42-0

001

Mo

nd

ay,

No

vem

ber

24

, 2

00

823

32

B

OM

AP

-L13

7 E

VM

AIC

31

06

RJ9

-4/

PH

ON

O IN

TE

RF

AC

ES

R2

252

.2K

C1

86

0.4

7uF

+C

18

32

2uF

C1

81

0.2

2uF

P8

RJ9

-4

1234

5

6

C1

820

.47

uF

R2

200

C1

77

0.2

2uF

R2

31

0

R2

121

R2

112

.2K

C1

85

0.4

7uF

C1

880

.01u

F

R2

131

0K

1%

R2

30

0

C1

950

.47

uF

C1

780

.47

uF

C1

800

.22

uF

C1

91

0.2

2u

F

C1

940.

22

uF

C1

93

0.2

2u

F

R2

22

0

R2

170

C1

79

18

pF

R2

261

0K

1%

C1

870

.01

uF

TIP

RING

SLEEVE

P14

PH

ON

OJA

CK

_ST

5 2 1

U4

0

TP

A48

61D

SH

UT

DO

WN

1

BY

PA

SS

2

IN+

3

IN-

4

VO

15

VD

D6

GN

D7

V02

8

C1

760

.22

uF

R22

8N

O-P

OP

C1

840

.1u

F

R2

19

10K

R2

18

10K

C1

92

0.4

7u

FC

19

00

.22

uF

TIP

RING

SLEEVE

P15

PH

ON

OJA

CK

_ST

5 2 1

R21

520

K

R2

16N

O-P

OP

R2

29

0

R21

41

0K 1

%

C1

96

0.0

1uF

R2

210

R2

27

10

K 1

%

R3

90

0

R23

20

R2

24

10K

C1

970

.01

uF

C18

90

.1u

F


A-25

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

P1

AN

EN

P1

FF

C

P1S

PD

P1D

PX

P2S

PD

P2D

PX

HW

PO

VR

AD

VF

C

P2M

DIX

P2

MD

IXD

ISP

2F

FC

RX

P1

RX

P2

TXM

2TX

P2

RX

M2

RX

M1

TXP

1TX

M1

P1

LED

2

P2

LED

2

P1

LED

3

P2

LED

3

P2

AN

EN

DS

K_3

V3

DS

K_3

V3

DS

K_

3V3

DS

K_

3V3

DS

K_

3V3

DS

K_3

V3

RX

P1

26

RX

P2

26

RX

M1

26

TXM

226

RX

M2

26

TXP

226

TXP

126

TXM

126

P2

LED

326

P1

LED

226

P1

LED

326

P2

LED

226

B_R

MII

_MD

IO_

D3

EN

ET

_RE

SE

T31B_

RM

II_

MD

IO_

CL

K3

B_

RM

II_

MH

Z_

503

B_

RM

II_

RX

D[0

]3

B_

RM

II_

RX

D[1

]3 B

_R

MII_

TX

EN

3

B_

RM

II_T

XD

[0]

3B

_R

MII

_TX

D[1

]3

B_

RM

II_

CR

S_D

V3

I2C

0_

SD

A4

,16

,22

,27

,28

,30

I2C

0_

SC

L4

,16

,22

,27

,28

,30

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

B

SP

EC

TR

UM

DIG

ITA

L I

NC

OR

PO

RA

TE

D

5113

42-0

001

Mo

nd

ay,

No

vem

ber

24

, 2

00

824

32

B

OM

AP

-L13

7 E

VM

KS

Z8

89

3MQ

L E

TH

ER

NE

T/P

HY

/SW

ITC

H

NOT

POPULATE FOR RMII

Differential Pair

Differential Pair

Differential Pair

Differential Pair

PS1 = 0, PS0 = 1 (I2C slave mode)

R23

31

K

R3

330

C2

00N

O-P

OP

TP

16T

ES

T P

OIN

T1

R2

434

9.9

R2

3422

0

R2

38

49

.9

R2

4022

0

R2

532

K

R24

5N

O-P

OP

R26

5N

O-P

OP

R3

890

R2

44N

O-P

OP

R2

76

NO

-PO

P

R2

712

KR

26

92K

R2

67N

O-P

OP

R2

500

R25

7N

O-P

OP

R2

79N

O-P

OP

R2

59

2K

R24

92K R

282

NO

-PO

P

R2

3922

0

R2

81

NO

-PO

P

R2

54

2K

R2

62N

O-P

OP

R2

663

.01K

R25

6N

O-P

OP

R26

1N

O-P

OP

R2

75

2K

U4

2

50.0

00 M

Hz

VC

C4

EN

1G

ND

2

OU

T3

R23

74

9.9

C1

98

0.0

1u

F

R2

63

2K

TP

14T

ES

T P

OIN

T1

R2

602K

R2

55

NO

-PO

P

Y3

NO

-PO

P

TP

13T

ES

T P

OIN

T1

C1

99N

O-P

OP

R2

72N

O-P

OP

R2

46N

O-P

OP

R2

51N

O-P

OP

R2

70N

O-P

OP

R2

3522

0

TP

15T

ES

T P

OIN

T1

R2

68

2K

R2

832

KR

288

NO

-PO

P

R25

2N

O-P

OP

R2

85

NO

-PO

P

R27

310

K

R2

424

9.9

R2

47

NO

-PO

P

R2

77N

O-P

OP

R2

414

9.9

R2

862

K

U4

1A

KS

Z88

93M

QL

P1L

ED

21

P1L

ED

12

P1L

ED

03

P2L

ED

24

P2L

ED

15

P2L

ED

06

AD

VF

C12

P2A

NE

N13

P2S

PD

14

P2D

PX

15

P2F

FC

16

P2L

ED

320

LED

SE

L123

P1L

ED

325

RM

II_E

N26

HW

PO

VR

27

P2M

DIX

DIS

28

P2M

DIX

29

P1A

NE

N30

P1S

PD

31

P1D

PX

32

P1F

FC

33

PW

RD

N36

FX

SD

144

RX

P1

45

RX

M1

46

TX

P1

48

TX

M1

49

RX

M2

52

RX

P2

53

TX

M2

55

TX

P2

56

ISE

T61

PS

010

1

PS

110

0

SP

IS_N

99

SD

A98

SC

L97

SP

IQ96

MD

IO95

MD

C94

SC

ON

F0

89

SC

ON

F1

88

SC

RS

87

SC

OL

86

SM

RX

D0

85

SM

RX

D1

84

SM

RX

D2

83

SM

RX

D3

82

SM

RX

DV

81

SM

RX

C80

SM

TX

C/R

EF

CLK

77

SM

TX

ER

76

SM

TX

D0

75

SM

TX

D1

74

SM

TX

D2

73

SM

TX

D3

72

SM

TX

EN

71

LED

SE

L070

RS

T_N

67

X2

66

X1

65

R2

87N

O-P

OP

R2

80

NO

-PO

PR

274

NO

-PO

P

R2

58

NO

-PO

P

R2

84

NO

-PO

P

R2

64

2KR2

48

2K

R2

362

.2K

R27

8N

O-P

OP



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

EN

ET

_VD

DIO

EN

ET

_VD

DC

EN

ET

_1V

2

EN

ET

_VD

DA

TR

EN

ET

_VD

DA

EN

ET

_VD

DA

PE

NE

T_1

V2

EN

ET

_1V

2

DS

K_3

V3

DS

K_3

V3

DS

K_3

V3

DS

K_3

V3

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5113

42-0

001

Mo

nd

ay,

No

vem

ber

24

, 2

00

825

32

B

OM

AP

-L13

7 E

VM

KS

Z88

93

MQ

L E

TH

ER

NE

T P

OW

ER

C2

07

0.1

uF

C2

09

0.1

uF

L21

BL

M21

PG

221

SN

1D12

+C

20

3

10

0uF

C2

18

0.0

01u

F

R2

93

1K

L22

BL

M2

1PG

221S

N1D

12

R2

911

K

R2

99

NO

-PO

PC

219

0.1

uF

+C

21

7

10

uF

/ 1

6V

C2

13

0.1

uF

C2

22

0.1

uF

C2

08

0.1

uF

R2

9010

0

R2

96

NO

-PO

P

C2

16

0.1

uF

R2

95

NO

-PO

P

U4

1B

KS

Z8

893M

QL

DG

ND

.17

NC

.11

11

NC

.99

NC

.10

10

VD

DIO

.18

VD

DC

.122

DG

ND

.221

NC

.17

17

NC

.18

18

NC

.19

19

NC

.24

24

NC

.34

34

NC

.35

35

VD

DA

.138

AG

ND

.137

AG

ND

.447

VD

DA

TX

50

AG

ND

.342

VD

DA

.243

AG

ND

.658

TE

ST

159

TE

ST

260

VD

DA

RX

51

AG

ND

.239

VD

DA

.357

AG

ND

.554

VD

DA

P63

AG

ND

.864

AG

ND

.762

UN

US

ED

.68

68

UN

US

ED

.69

69

DG

ND

.378

VD

DIO

.279

DG

ND

.490

VD

DC

.291

UN

US

ED

.102

102

UN

US

ED

.93

93U

NU

SE

D.9

292

SC

AN

EN

128

TE

ST

EN

127

UN

US

ED

.126

126

UN

US

ED

.125

125

UN

US

ED

.124

124

VD

DC

.312

3

DG

ND

.612

2

UN

US

ED

.121

121

UN

US

ED

.120

120

UN

US

ED

.119

119

UN

US

ED

.118

118

UN

US

ED

.117

117

UN

US

ED

.116

116

UN

US

ED

.115

115

UN

US

ED

.114

114

UN

US

ED

.113

113

UN

US

ED

.112

112

UN

US

ED

.111

111

UN

US

ED

.110

110

UN

US

ED

.109

109

UN

US

ED

.108

108

VD

DIO

.310

7

DG

ND

.510

6

UN

US

ED

.105

105

UN

US

ED

.104

104

UN

US

ED

.103

103

MU

X1

40

MU

X2

41

R2

94N

O-P

OP

+C

20

2

10

uF

+C

21

4

47

uF

C2

05

0.1

uF

+C

220

10

uF

R3

031K

L20

BL

M2

1P

G22

1SN

1D1

2

+C

22

1

10

uF

C2

24

0.1

uF

R3

01N

O-P

OP

R3

02

1K

R2

92

10K

+C

20

1

10

uF

R2

891K

L19

BL

M2

1P

G22

1SN

1D

12

R2

97N

O-P

OP

+C

212

10

uF

L23

BL

M2

1PG

221S

N1D

12

R2

98N

O-P

OP

C2

15

0.0

1u

F

C2

10

0.1

uF

R3

00

NO

-PO

P

+C

21

1

10

uF

C2

06

0.1

uF

C22

3

0.1

uF

C20

4

0.1

uF


A-27

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

TXP

1

RX

M1

TXP

2

RX

M2

TXM

1

RX

P1

TXM

2

RX

P2

GN

D_E

_EN

ET

GN

D_E

_EN

ET

DS

K_3

V3

EN

ET

_V

DD

AT

R

GN

D_E

_EN

ET

GN

D_E

_EN

ET

DS

K_3

V3

EN

ET

_V

DD

AT

R

RX

P1

24

RX

P2

24

RX

M1

24

TXM

22

4

RX

M2

24

TXP

22

4

TXP

12

4

TXM

12

4

P2

LED

32

4

P1

LE

D2

24

P1

LE

D3

24

P2

LED

22

4

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5113

42-0

001

Mo

nd

ay,

No

vem

ber

24

, 2

00

826

32

B

OM

AP

-L13

7 E

VM

KS

Z88

93M

QL

ET

HE

RN

ET

PO

RT

S

SILKSCREEN:

ETHERNET

SILKSCREEN:

ETHERNET

Differential Pair

Differential Pair

Differential Pair

Differential Pair

C2

32

0.1

uF

P9

RJ4

5 H

AL

O H

FJ1

1-2

450E

-L2

1

TX

D-C

T4

NC

17

GN

D8

TX

D+

1

TX

D-

2

RX

D+

3

RX

D-

6R

XD

-CT

5

SH2 SH2SH1 SH1

LED

2-12

LED

2+11

LED

1-10

LED

1+9

MH1 MH1

MH2 MH2

R3

11

49.9

R3

05

49.9

R30

44

9.9

C22

6

100

0p

F 2

kV

C2

29

0.1

uF

P10

RJ4

5 H

AL

O H

FJ1

1-2

450E

-L2

1

TX

D-C

T4

NC

17

GN

D8

TX

D+

1

TX

D-

2

RX

D+

3

RX

D-

6R

XD

-CT

5

SH2 SH2SH1 SH1

LED

2-12

LED

2+11

LED

1-10

LED

1+9

MH1 MH1

MH2 MH2

R3

07

49.9

R30

84

9.9

R31

04

9.9

C23

0

100

0p

F 2

kV

C2

25

0.1

uF

+C

23

1

10

uF

R30

64

9.9

+C

22

7

10

uF

C2

28

0.1

uF

R3

09

49.9



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

T_

AX

R1[

6]T

_A

XR

1[7]

T_

AX

R1[

8]T

_A

XR

1[9]

T_

AX

R1[

10]

T_

AX

R1[

11]

T_A

MU

TE

0

T_A

CLK

X0

EX

P1_

AF

SX

0

T_

AC

LK

R0

T_

AF

SR

0

T_A

CL

KR

1

T_A

FS

R1

T_

AX

R1[

1]T

_A

XR

1[2]

T_

AX

R0

_11

/AX

R2_

0/G

PIO

3_11

T_A

MU

TE

1

VC

C_

5V

VC

C_

5V

VC

C_

5VV

CC

_5

V

DS

K_

3V3

T_

AX

R1[

10]

2T

_A

XR

1[11

]2

T_

AX

R1[

8]2

T_

AX

R1[

6]2

T_

AX

R1[

7]2

T_

AX

R1[

9]2

EX

P_A

CLK

X1

2

EX

P_A

XR

1[0]

2

T_A

CL

KX

02

,6

T_A

MU

TE

02

EX

P_A

XR

0[5]

3

EX

P_A

XR

0[0]

3E

XP

_AX

R0[

1]3

EX

P_A

XR

0[3]

3E

XP

_AX

R0[

4]3

EX

P_A

XR

0[2]

3

EX

P_A

HC

LKR

03

EX

P_A

HC

LKX

12

EX

P_A

FS

X1

2

T_

AC

LKR

02

T_

AF

SR

02

T_

AC

LKR

12

T_

AF

SR

12

T_A

XR

1[1

]2

T_A

XR

1[2

]2

EX

P_A

XR

1[5]

2

EX

P_S

PI1

_SO

MI

5

SE

L_E

NE

Tn

_MC

AS

P0

3,1

4

EX

P_A

XR

0[6]

3E

XP

_AX

R0[

7]3

EX

P_

AX

R0[

8]3

EX

P1_

AM

UT

E2

8A

HC

LK

R2

8

SE

L_S

PI1

_EX

P1

5

EX

P1

_SP

I1_S

IMO

5E

XP

1_S

PI1

_CLK

5

T_

AX

R0

_11/

AX

R2_

0/G

PIO

3_11

2E

XP

1_A

XR

0_1

58

EX

P1_

AX

R0

_12

8

EX

P1_

AX

R0

_14

8E

XP

1_A

XR

0_1

38

EX

P_A

XR

0_10

4E

XP

_AX

R0_

94

EX

P_A

XR

1[3]

2E

XP

_AX

R1[

4]2

EX

P1_

SE

L_M

CA

SP

12

I2C

0_

SC

L4

,16

,22

,24

,28,

30I2

C0

_S

DA

4,1

6,2

2,2

4,2

8,3

0

T_A

FS

X0

2

BO

OT

_D

ISA

BLE

n2

,3,4

,5,8

,16,

19

,31

T_

AH

CL

KR

12

EX

P_R

ES

ET

n2

8,2

9,3

1

T_A

MU

TE

12

EX

P1

_SP

I1_E

NA

n5

EX

P1_

SP

I1_S

CS

n5

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5113

42-0

001

Mo

nd

ay,

No

vem

ber

24

, 2

00

827

32

B

OM

AP

-L13

7 E

VM

AU

DIO

/ E

XP

AN

SIO

N

CO

INN

EC

TO

R 1

Mounting holes 0.250 pad 0.125 drill

Z2

1Z

11

P11

QS

E-0

40-0

1-L-

D-A1

12

2

33

44

55

66

77

88

99

1010

1111

1212

1313

1414

1515

1616

1717

1818

1919

2020

2121

2222

2323

2424

2525

2626

2727

2828

2929

3030

3131

3232

3333

3434

3535

3636

3737

3838

3939

4040

4141

4242

4343

4444

4545

4646

4747

4848

4949

5050

5151

5252

5353

5454

5555

5656

5757

5858

5959

6060

6161

6262

6363

6464

6565

6666

6767

6868

6969

7070

7171

7272

7373

7474

7575

7676

7777

7878

7979

8080

8181

8282

8383

8484

8585

8686

8787

8888

MH

189

MH

290

U4

3S

N7

4C

BT

LV

1G1

25

3

4

5

2

1

C23

3.1

uF


A-29

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

VC

C_5

VV

CC

_5V

VC

C_

5VV

CC

_5V

EX

P2_

SP

I1_

CLK

5EX

P2_

SP

I1_S

IMO

5E

XP

2_S

PI1

_SO

MI

5

EX

P2

.SP

I0_C

LK

16

EX

P2.

SP

I0_S

OM

I16

EX

P2.

SP

I0_S

IMO

16

EQ

EP

0A16

EQ

EP

0B

16

SE

L_S

PI1

_EX

P2

5

EX

P_R

ES

ET

n2

7,2

9,3

1

EX

P_E

QE

P1A

2E

XP

_EQ

EP

1B2

SE

L_E

XP

2_T

IME

R4

,14

SE

L_E

XP

2_Q

EP

12

SE

L_E

XP

2_U

AR

T1

4,1

4

EX

P2_

UA

RT

1_T

XD

4E

XP

2_U

AR

T1_

RX

D4

EX

P2_

TM

P64

P0_

OU

T12

4E

XP

2_T

MP

64P

0_IN

124

I2C

0_

SC

L4

,16

,22

,24

,27,

30I2

C0_

SD

A4

,16

,22

,24

,27,

30

SE

L_E

XP

2_Q

EP

016

SE

L_S

PI1

_EX

P2_

B5

EX

P2

_SP

I1_E

NA

n5

EX

P2

_SP

I1_S

CS

n5

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

A

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5113

42-0

001

Mo

nd

ay,

No

vem

ber

24

, 2

00

828

32

B

OM

AP

-L13

7 E

VM

EX

PA

NS

ION

2


P12

QS

E-0

20-

01-L

-D-A1

12

2

33

44

55

66

77

88

99

1010

1111

1212

1313

1414

1515

1616

1717

1818

1919

2020

2121

2222

2323

2424

2525

2626

2727

2828

2929

3030

3131

3232

3333

3434

3535

3636

3737

3838

3939

4040

4141

4242

4343

4444

Z3

1Z

41



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

EX

P_E

MIF

A_A

1E

XP

_E

MIF

A_

A2

EX

P_E

MIF

A_D

12E

XP

_E

MIF

A_

D13

EX

P_E

MIF

A_D

10

EX

P_

EM

IFA

_D

15E

XP

_EM

IFA

_D14

EX

P_E

MIF

A_D

8

EX

P_

EM

IFA

_D0

EX

P_

EM

IFA

_D1

EX

P_

EM

IFA

_D4

EX

P_

EM

IFA

_D2

EX

P_

EM

IFA

_D6

EX

P_

EM

IFA

_D

9E

XP

_E

MIF

A_

D11

EX

P_

EM

IFA

_D7

EX

P_

EM

IFA

_D3

EX

P_

EM

IFA

_D5

VC

C_

5V

VC

C_5

V

VC

C_

5V

VC

C_

5V

EM

IFA

_B

A0

8

EM

IFA

_A3

8E

MIF

A_A

58

EM

IFA

_A9

8E

MIF

A_

A11

8

EX

P3_

EM

IFA

_CLK

8

EM

IFA

_A7

8

EM

IFA

_A

48

EM

IFA

_A

68

EM

IFA

_A

88

EM

IFA

_A1

08

EM

IFA

_A1

28

EM

IFA

_C

S2

n8

EX

P3

_EM

IFA

_CS

3n

8

EX

P_

EM

IFA

_CS

4n19

EM

IFA

_WA

IT0

8

EM

IFA

_S

DC

KE

8

EX

P_

EM

IFA

_D0

19E

XP

_EM

IFA

_D1

19E

XP

_E

MIF

A_D

219

EX

P_

EM

IFA

_D4

19E

XP

_E

MIF

A_D

619

EX

P_E

MIF

A_D

319

EX

P_E

MIF

A_D

519

EX

P_E

MIF

A_D

719

EX

P_R

ES

ET

n27

,28,

31

EX

P3

_EM

IFA

_WE

n_D

QM

08

EX

P3

_EM

IFA

_WE

n_D

QM

18

EX

P3_

SE

L_M

EM

8E

XP

3_S

EL_

ME

M_

CT

L8

EX

P3_

SE

L_M

EM

D0_

719 EX

P3_

SE

L_M

EM

D12

_D15

8,1

4E

XP

3_S

EL_

ME

MD

8_D

118

,14

EX

P3

_EM

IFA

_OE

n8

EX

P3_

EM

IFA

_W

En

8

EX

P_E

MIF

A_D

88

EX

P_E

MIF

A_D

98

EX

P_E

MIF

A_

D10

8E

XP

_EM

IFA

_D11

8E

XP

_EM

IFA

_D

128

EX

P_E

MIF

A_D

138

EX

P_E

MIF

A_

D14

8E

XP

_EM

IFA

_D15

8

EX

P_

EM

IFA

_CS

0n8

EX

P_

EM

IFA

_CS

5n19

EX

P3_

SE

L_M

EM

_C

TL2

8

EM

IFA

_A

08

EX

P_

EM

IFA

_A2

19E

MIF

A_

BA

18 EX

P_

EM

IFA

_A1

19

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

B

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5113

42-0

001

Mo

nd

ay,

No

vem

ber

24

, 2

00

829

32

B

OM

AP

-L13

7 E

VM

EX

PA

NS

ION

3


Z5

1

P13

QS

E-0

40-

01-L

-D-A1

12

2

33

44

55

66

77

88

99

1010

1111

1212

1313

1414

1515

1616

1717

1818

1919

2020

2121

2222

2323

2424

2525

2626

2727

2828

2929

3030

3131

3232

3333

3434

3535

3636

3737

3838

3939

4040

4141

4242

4343

4444

4545

4646

4747

4848

4949

5050

5151

5252

5353

5454

5555

5656

5757

5858

5959

6060

6161

6262

6363

6464

6565

6666

6767

6868

6969

7070

7171

7272

7373

7474

7575

7676

7777

7878

7979

8080

8181

8282

8383

8484

8585

8686

8787

8888

MH

189

MH

290


A-31

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

VC

C_

5V

VC

C_

5V

VC

C_

5V

VC

C_

5V

VC

C_

5V

VC

C_

5V

VC

C_

5V

VC

C_

5V

VC

C_

1V8

VC

C_

3V

3

VC

C_

1V2

ALT

_3V

3

VR

TC

CP

U_R

TC

_1V

8

VC

C_

5V

VL

DO

2

VC

C_

3V

3

VC

C_

5V

ALT

_3V

3

VC

C_

3V

3

VC

C_

1V8

DS

K_3

V3

CP

U_

3V3

DS

K_

1V8

CP

U_

1V

8

VC

C_

1V

2C

PU

_1

V2

VC

C_

5V

ALT

_3V

3V

LD

O2

VC

C_

5V

VC

C_

5V

SY

S_

RE

SE

Tn

31

I2C

0_

SC

L4

,16

,22

,24

,27,

28

I2C

0_

SD

A4

,16

,22

,24

,27,

28

EN

AB

LE_

1V

831

EN

AB

LE_

3V

331

EN

AB

LE_

1V

231

PB

_RE

SE

T31

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

B

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5113

42-0

001

Mo

nd

ay,

No

vem

ber

24

, 2

00

830

32

B

OM

AP

-L13

7 E

VM

CO

RE

PO

WE

R

. DEFLDO2 DEFLDO1 VLDO1 VLDO2

0 0 1.3 V 3.3 V

0 1 2.8 V 3.3 V

1 0 1.3 V 1.8 V

1 1 1.8 V 3.3 V

+C

24

32

.2u

F

C26

90

.1u

F

L16

2.2

uH

TP

18T

P-6

0

R3

24N

O-P

OP

+C

24

4

10

uF

R3

411K

+C

238

10

uF

C2

390

.001

uF

R3

151K

R3

180

.02

5

R34

2N

O-P

OP

R3

28

47K

R3

14N

O-P

OP

R3

191K

R3

381

0K

R3

8710

K

C23

50

.1u

F

R3

261

0K

TP

23T

P-6

0

1

R3

45

33

SW

4

PU

SH

BU

TT

ON

SW

A A1

B1

B

L18

2.2

uH

+C

245

2.2

uF

R3

29

10K

R3

21N

O-P

OP

TP

19T

P-6

0

1

TP

29

TP

1

L15

BLM

41P

750S

PT

R3

37N

O-P

OP

R3

3110

K

R3

30

NO

-PO

P

TP

20T

P-6

0

R3

40N

O-P

OP

R3

17

0

U4

4

TP

S65

023

DE

FD

CD

C3

1

VD

CD

C3

2

PG

ND

33

L34

VIN

CD

DC

35

VIN

DC

DC

16

L17

PG

ND

18

VD

CD

C1

9

DE

FC

DC

D1

10

HOT_RESETn 11

DEFLDO1 12

DEFLDO2 13

VSYSIN 14

VBACKUP 15

VRTC 16

AGND2 17

VLDO2 18

VINLDO 19

VLDO1 20

LOW

BA

Tn

21LD

O_E

N22

DC

DC

3_E

N23

DC

DC

2_E

N24

DC

DC

1_E

N25

TR

ES

PW

RO

N26

RE

SP

WR

ON

n27

INT

n28

SD

AT

29

SC

LK30

PWRFAILn31DEFDCDC232

VDCDC233PGND234

L235VINDCDC236

VCC37PWRFAIL_SNS38LOWBAT_SNS39

AGND140

PWR_PAD41

R3

20

NO

-PO

P

R3

39N

O-P

OP

R3

160

.02

5

TP

27T

P-6

01

R3

120

.02

5

+C

234

10

uF

TP

21T

P-6

0

1

TP

17T

P-6

0

1

+C

24

22

2u

F

L17

2.2

uH

TP

26T

P-6

0

+C

236

22

uF

R3

44

0

TP

24T

P-6

0

+C

23

72

2u

F

R3

321

0KC

267

NO

-PO

P

R3

230

.02

5

TP

25T

P-6

0

1

R3

22N

O-P

OP

R3

25

10K

R3

430

TP28

TP

1

+C

240

10

uF

C2

68

0.1

uF

TP

22T

P-6

0

+

C2

41

22

uF

R3

272K

R3

36N

O-P

OP

R3

130.

025



5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

DS

K_1

V2_

SY

S_

OK

AY

DS

K_1

V8_

SY

S_

OK

AY

DS

K_

3V

3_

SY

S_

OK

AY

DS

K_

1V

8_

SY

S_O

KA

Y

DS

K_3

V3_

SY

S_

OK

AY

DS

K_3

V3_

SY

S_

OK

AY

DS

K_1

V8_

SY

S_

OK

AY

DS

K_1

V2_

SY

S_

OK

AY

DS

K_1

V2_

SY

S_

OK

AY

DS

K_

3V

3_

SY

S_

OK

AY

CP

U_

RE

SE

T

CP

U_

RE

SE

T

ALT

_3V

3A

LT_3

V3

CP

U_

1V

2

ALT

_3V

3A

LT_3

V3

DS

K_1

V8

ALT

_3V

3A

LT_3

V3

DS

K_3

V3

ALT

_3V

3

ALT

_3V

3

ALT

_3V

3

ALT

_3V

3A

LT_3

V3

ALT

_3V

3

ALT

_3V

3

EN

AB

LE_

1V2

30

EN

AB

LE_

1V8

30

EN

AB

LE_3

V3

30

AIC

3106

_R

ES

ET

n22

EN

ET

_R

ES

ET

24

CP

U_R

ES

ET

10

,14

EX

P_R

ES

ET

n2

7,2

8,2

9

PO

NR

Sn

IN21

AR

M_

RS

Tn

21

XR

Sn

21

BO

OT

_D

ISA

BLE

2,3

,14

,16

,19

BO

OT

_D

ISA

BLE

n2

,3,4

,5,8

,16

,19

,27

PB

_R

ES

ET

30

SY

S_

RE

SE

Tn

30

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

B

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5113

42-0

001

Mo

nd

ay,

No

vem

ber

24

, 2

00

831

32

B

OM

AP

-L13

7 E

VM

PO

WE

R I

N

Reset

Threhold 0.84 Volts

Reset

Threhold 0.84 Volts

Reset

Threhold 0.84 Volts

U4

5

TP

S3

808G

09D

BV

RG

4

RE

SE

T1

GN

D2

MR

3

CT

4

SE

NS

E1

5V

DD

6

TP

301

U4

7 1G

08

1 24

5 3 TP

48

TP 1

R3

60

NO

-PO

P

TP

321

R3

65

NO

-PO

P

C2

560

.1u

F

R3

5733

C2

510

.1uF

C2

570

.1u

F

R3

470

C2

58

1u

F

C2

53

0.1

uF

C2

46

0.1

uF

R3

481

0K

1%

C2

470

.1uF

U4

6 1G08

1 24

5 3

C2

50

0.1

uF

U5

1S

N7

4A

HC

14

DC

KR

G4

3

4

5

2 1

C2

48

0.1

uF

C2

52

0.1

uF

R3

5833

R3

62

NO

-PO

P

U5

3S

N7

4A

HC

14

DC

KR

G4

3

4

5

2 1

R3

4910

K

R3

59

NO

-PO

P

C2

55

.1u

F

U4

8

TP

S3

808G

09D

BV

RG

4

RE

SE

T1

GN

D2

MR

3

CT

4

SE

NS

E1

5V

DD

6

R3

5233

R3

34N

O-P

OP

R3

61

NO

-PO

P

R3

504

.99K

C2

54

0.1

uF

C2

490

.1u

F

R3

3510

K

U5

2S

N7

4A

HC

14

DC

KR

G4

3

4

5

2 1

U4

9 1G08

1 24

5 3

R3

5520

K

R3

64

NO

-PO

P

U5

0

TP

S3

808G

09D

BV

RG

4

RE

SE

T1

GN

D2

MR

3

CT

4

SE

NS

E1

5V

DD

6

R3

632

.2K

R3

88

0

R3

561

0K

1%

R3

511

0K

1%

TP

47T

P1

R3

5310

K

R3

4610

K

TP

311

R3

5433


A-33

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

VC

C_

5V

VC

C_

3V

3

VC

C_

1V

2

VC

C_

5V

VC

C_

1V

8

AL

T_C

PU

_1V

2

VL

DO

2

VC

C_5

V

Siz

e:

Da

te:

DW

G N

OR

evi

sio

n:

Sh

eet

of

Titl

e:

Pa

ge

Co

nte

nts

:

B

SP

EC

TR

UM

DIG

ITA

L IN

CO

RP

OR

AT

ED

5113

42-0

001

Mo

nd

ay,

No

vem

ber

24

, 2

00

832

32

B

OM

AP

-L13

7 E

VM

PO

WE

R I

N

2.5

MM

JA

CK

SILKSCREEN:

5V IN

ALTERNATE 1.2V Power Supply

Vou

t = ((

R1+

R2)

/R2)

*1.

193


TP

46T

P1

R3

70

360

Z10

1

U5

4

TP

S79

901-

AD

J

EN

3

VO

UT

5

FB

4

VIN

1

GND 2

DS

9L

ED

GR

N

SW

6S

WIT

CH

3

1

6

4

52 78

Q1

FJV

31

09

R

3

1

2

R3

732

20K

1%

F1

F_4

.0A

12

C2

62

10u

F

R3

66

NO

-PO

P

R3

6736

0

TP

34T

P

R3

711

K

C2

60

10

uF

TP

41

TP

1

Z9

1

D1

SM

CJ6

A

R3

691

K

+C

259

47

uF

TP

42T

P1

DS

8L

ED

GR

N

Q2

FJV

310

9R

3

1

2

TP

43

TP

1

C2

61

5.6

pF

DS

7L

ED

GR

N

Z7

1

DS

6L

ED

GR

N

R3

721

5K

1%

TP

44T

P1

TP33

TP-3

0

Z8

1

R3

7422

0

TP45

TP

1

R3

6822

0

J6

RA

SM

712

SLE

EV

ES

HU

NT

CE

NT

ER



B-1

Appendix B

Mechanical Information

This appendix contains the mechanical information about the OMAP-L137EVM produced by Spectrum Digital.


B-2 OMAP-L137 EVM Technical Reference

TH

IS D

RA

WIN

G IS

NO

T T

O S

CA

LE

Printed in U.S.A., November 2008511345-0001 Rev A