2104 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 9, SEPTEMBER 2005

Briefs___________________________________________________________________________________________

Off-State Current and Performance Analysis forDouble-Gate CMOS With Non-Self-Aligned Back Gate

Keunwoo Kim, Hussein I. Hanafi, Jin Cai, and Ching-Te Chuang

Abstract—Numerical simulation-based study of double-gate (DG)field-effect transistors (FETs) leads to the possibly viable concept ofextremely scaled but nonself-aligned DG CMOS. Predictions of off-statecurrent, on-state current, and circuit performance, accounting forshort-channel effects and energy-quantization effects, in 25-nm DG FETssuggest that moderate back-gate underlap does not severely underminethe superior performance and leakage current of nanoscale DG CMOSrelative to those of bulk-Si CMOS. The reverse back-gate biasing schemefor leakage reduction in DG CMOS is shown to be much more efficientthan the reverse body biasing scheme in bulk Si even with moderateback-gate underlap.

Index Terms—Body biasing, double-gate (DG) field-effect transistors(FETs), gate underlap, off-state current, on-state current.

I. INTRODUCTION

In first-principle physics, double-gate (DG) field-effect transistors(FETs) appear more scalable than conventual bulk-Si, or silicon-on-insulator (SOI), technology because of the gate–gate charge couplingenabled by a thin Si-film channel [1]–[4]. Furthermore, DG CMOScan potentially offer high performance at low voltage because of itsnearly ideal subthreshold slope (or gate swing S) of the devices, alsoafforded by the gate–gate coupling [1]. The performance advantage canbe attained with asymmetrical (n+ and p+ polysilicon) as well as sym-metrical gate structures [2], [3]. Planar DG FET does not suffer fromthe device width quantization effects unlike FinFET, thereby offeringsimple design migration [1]. However, fabrication of extremely scaledplanar DG device having back-gate self-alignment is a formidable, ifnot impossible, task [5].

In this brief, we present a simulation-based study on 25-nm sym-metrical-gate and asymmetrical-gate DG FETs, which leads to the con-cept of a pragmatic, nonself-aligned planar DGCMOS technology that,irrespective of moderate back-gate underlap, can still yield high per-formance at low voltage with good control of short-channel effects(SCEs). The pragmatic design exploits the inherent beneficial featuresof both asymmetrical and symmetrical DG FETs [1], [2], as well as theflexibility in their structural design. Off-state current (Io�) reductionby reverse back-gate bias in a DG device is studied and compared withthe reverse body bias in bulk-Si counterpart [6]–[8].

II. 25-nm DG MOSFET

By using a two-dimensional (2-D) numerical device simulator [9]with physical model parameters calibrated against current state-of-artCMOS technology [1] to monitor the SCEs and a one-dimensional(1-D) self-consistent Poisson–Schrödinger solver [10] to account for

Manuscript received October 7, 2004; revised May 13, 2005. This work wassupported in part by DARPA under Contract NBCH30390004. The review ofthis brief was arranged by Editor S. Kimura.

The authors are with the IBM T. J. Watson Research Center, YorktownHeights, NY 10598 USA.

Digital Object Identifier 10.1109/TED.2005.854292

the energy-quantization effects [10], we investigate DG CMOS de-vices having a 25-nm effective channel length (Le� = 25 nm). Thelightly doped (1015 cm�3) Si-film thickness (tSi) is 9 nm, which istSi > Le�=3 to mitigate a higher source/drain series resistance andlower carrier mobility (�) for thinner film [11], [12]. The oxide thick-ness is 1 nm for front and back gates (toxf = toxb = 1 nm), which is thelimit for acceptable SiO2 gate tunneling leakage [13], [14]. We com-pared the asymmetrical-gate FET, having n+ and p+ polysilicon gates,with the symmetrical-gate counterpart, having near-mid-gap gate mate-rial with tailored work function for acceptable off-state current control(Io� � 10�7 A=�m in accordance with the International TechnologyRoadmap for Semiconductors [15]). Both devices, with aligned gates,showed [16] much better control of SCEs than a bulk-Si counterpart[17].The asymmetrical device has only one predominant channel, yet

its inversion-charge density (Qi) is comparable with that of thetwo-channel symmetrical device [2]. However, the larger channelcharge in the asymmetrical device is supported by higher transverseelectric field, which results in lower effective carrier mobility (�e� )due to surface scattering [18]. This seems to imply lower on-statecurrent (Ion), especially when the correlation between mobility andcarrier transport is recognized [19]–[21]. However, our simulationsshow nearly equal Ion in the asymmetrical and symmetrical devices.For the nFET

Ion = �WQi(0+)v(0+) (1)

where v is the electron velocity (which is almost equal to the thermallimit [19]); y = 0+ is a point just beyond the virtual source [21]. SinceQi is nearly the same in both devices

v(0+) = �e�Ey(0+) (2)

must be nearly the same; and, since the mobility is lower in the asym-metrical device Ey(0

+) the longitudinal electric field must be higher.The higher Ey is, indeed, consistent with the higher on-state Qi perchannel, which results in higher saturation drain voltage, VDS(sat) [11].Hence, Ion of the asymmetrical DG FET can be nearly equal to that ofthe symmetrical counterpart (having equal Io� ); and the self-alignedDG-device currents per width at VDD = 1:0 V are predicted to be� 15% higher than that of the bulk-Si counterpart [22], due, in part, tolower subthreshold slope (S) and the enhanced carrier transport in the(lightly doped) DG devices [21].

III. EFFECTS OF BACK-GATE UNDERLAP

The noted superiority of self-aligned DG FETs is anticipated. How-ever, whether it will ever be achieved in actual technology is not clearbecause of the mentioned process complexity. Thus, with new phys-ical insight on the performance of DG FETs [1]–[4], [23], we considerthe possibility of a high-performance, but pragmatic DG CMOS tech-nology in which only the front gate is self-aligned. Unlike in [3], thenonself-aligned back gate is not enlarged to ensure overlap with thesource/drain, thereby implying possible underlap [4].We study via sim-ulation the effects of such underlap in both the asymmetrical and sym-metrical scaled DG nFETs.

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 9, SEPTEMBER 2005 2105

Fig. 1. MEDICI predicted I � V characteristics (at V = 1 V), andnormalized I (relative to that in self-aligned device) with back-gate underlap(�L) in L = 25-nm asymmetrical and symmetrical DG nFETs at V =1:0 V; t = t = 1 nm, t = 9 nm.

With moderate back-gate underlap, we are first concerned with un-dermining Io� . For the ideal, self-aligned 25 nm DG nFETs, we canwrite [11]

Io� = �W

Le�VT�n(e�)Qi(0

+)

� exp�Vt(DIBL) +�Vt(QM)

VT(3)

where W is the device width, VT = kBT=q is the thermal voltage,and �n(e�) is the effective electron mobility. For the asymmetricaldevice, the drain-induced barrier lowering (DIBL)-induced Vt shift,�Vt(DIBL), is predicted to be 50 mV at VDS = 1:0 V by MEDICI[9]; and the Vt shift due to the quantization, �Vt(QM), is predicted tobe 100 mV by SCHRED [10]. With this latter shift and the MEDICIresults, (3) gives Io� � 1:5 � 10�7 A=�m. The gate work functionof the symmetrical device (�G = XSi + 0:28Eg(Si)) was henceforthspecified to yield the same Io� .

We used MEDICI to predict Io� in these devices with non-self-aligned back gates, shifted toward the drain causing underlap(�L) at the source side of the channel, which is the worst case from cir-cuit performance perspective due to lower Ion, higher Io� , and highergate-to-drain capacitance, compared with the underlap at the drain side[24]. Fig. 1 shows MEDICI-predicted normalized Io� with underlaprelative to Io� without underlap. MEDICI-predicted IDS–VGS curveis shown in the insert. Predicted Io�(underlap)=Io� , i. e., normalizedIo� for the nonself-aligned DG device with respect to Io� for theself-aligned DG device versus �L=Le� (with Le� = 25 nm) atVDS = 1:0 V is shown in Fig. 1 for both DG nFETs. For substantiveunderlap (> 10%), Io�(underlap) in asymmetrical DG device increasesconsiderably more than that of symmetrical counterpart. While thedegradations in S and DIBL are less in the asymmetrical DG deviceshown in Fig. 2(a) and (b), the reduced gate-gate coupling causes asignificant reduction in Vt of asymmetrical DG device, resulting inrapid increase of Io� with increasing underlap. Both S and DIBL

Fig. 2. MEDICI-predicted (a) subthreshold gate swing (S) and (b) DIBLversus back-gate underlap (�L) in L = 25 nm DG FETs; V = 1:0 V.

Fig. 3. MEDICI-predicted I with decreasing L for �L=L = 20%back-gate underlap in DG nFETs at V = 1:0 V, compared with self-alignedDG and bulk-Si devices.

increase with increasing �L=Le� . However, for �L=Le� < 30%,both devices show minimal increase of Io� , which suggests possibleviability of nonself-aligned DG FETs. Even with 40% underlap inFig. 1, the increases in Io� are less than an order-of-magnitude; andfor 20% underlap, the increases are less than a factor of two. Assuminga normal statistical distribution of �L=Le� in an actual technology,these increases in Io� , which are much less severe than that toleratedin bulk-Si CMOS [11], [17], seem acceptable.For a “nominal” 20% back-gate underlap, Fig. 3 shows MEDICI-

predicted Io� for decreasing Le� in the DG nFETs as compared withbulk Si at VDS = 1:0 V. For a 20% reduction of Le� , which is atypical designation of minimum channel length (Lmin) for the worst-case process [11], Io� in both DG devices is increased by less than anorder-of-magnitude even for 20% underlap. This is much better thanwhat is commonly accepted in bulk-Si CMOS [16], and indicates thatimperfect DG devices could be much scalable than bulk-Si technology.Note, in Fig. 3, that Io� for bulk-Si nFET with 1 nm gate-oxide thick-ness is increased by a factor of � 85� as Le� is scaled from 25 to19 nm. The bulk-Si device is optimized by engineering channel/halo

2106 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 9, SEPTEMBER 2005

Fig. 4. MEDICI-predicted variation of I and I (relative to those inself-aligned device) with 20% back-gate underlap (�L=L = 20%) inL = 25 nm DG FETs at V = 1:0 V.

Fig. 5. MEDICI-predicted variation of I (relative to that in self-aligneddevice) with back-gate underlap (�L) in L = 25 nm DG FETs atV = 1:0 V.

doping profiles with halo doping density (� 5 � 1018 cm�3) to sup-press SCEs. Note also that both DG devices and bulk-Si device areoptimally designed in 25-nm channel length, and hence the leakagecurrents of DG devices are relatively larger for L > 25 nm than thatof bulk-Si counterpart due to less SCEs. Fig. 4 shows MEDICI-pre-dicted normalized Ion and Io� for 20% underlap with respect to thoseof self-aligned DG devices versus VDD. As can be seen, the ratios ofIon and Io� exhibit weak dependence on VDD in both DG devices.Asymmetrical DG device has lower DIBL as depicted in Fig. 2(a), butits threshold voltage (Vt) is decreased by back-gate underlap due toreduced gate–gate coupling [2].

We are also concerned with Ion in DG devices having moderateback-gate underlap. MEDICI predictions of normalized Ion with re-spect to Ion in self-aligned device (Ion(underlap)=Ion versus�L=Le� )at VDD = 1:0 V for both 25 nm DG nFETs are shown in Fig. 5. Herewe see the advantage for the asymmetrical device; Ion(asym) hardlychanges, even for substantive underlap. This is a result of counteractingeffects of less gate-gate coupling (or reduced Vt) [2] and enhancedSCEs [16] (see Fig. 2). However, Ion(sym) is reduced significantly withincreasing �L=Le� , i. e., by 18% for �L=Le� = 40%. In this case,the reduced back channel overwhelms the worsening SCEs (see Fig. 2).

IV. GATE DELAY

An unloaded fan-out of 1 (FO1) nine-stage inverter ring oscillatorwas simulated using MEDICI [9] to assess the impact of the back-gate underlap on circuit performance. Fig. 6 shows MEDICI-predicted

Fig. 6. MEDICI-predicted delay of unloaded fan-out of 1 (FO1) nine-stagering oscillator versusV for 25 nm self-aligned asymmetrical and symmetricalDG devices and those with 20% back-gate underlap, compared to bulk-Sicounterpart; the device width is 1 �m for nFETs and 2 �m for pFETs. Theenlarged drain overlap length for �L=L = 20% in source underlap versusdelay at V = 1:0 V is inserted.

Fig. 7. MEDICI-predicted I versus delay of unloaded FO1 nine-stage ringoscillator (at L = 25, 23, 21, and 19 nm) for self-aligned asymmetrical andsymmetrical DG devices and those with 20% back-gate underlap, compared tobulk-Si counterpart; the device width is 1 mm for nFETs and 2 mm for pFETs.

delay versus VDD for 25-nm self-aligned asymmetrical and symmet-rical DG devices and those with 20% back-gate underlap, comparedwith bulk-Si counterpart. For no underlap, both DG devices show com-parable delay for VDD = 0:7–1:0 V. For 20% underlap, asymmet-rical DG CMOS is� 5% faster than symmetrical counterpart for VDDrange shown in the figure since Ion for symmetrical device is reducedby underlap as indicated in Fig. 4. However, symmetrical DG CMOSwith the underlap is still faster than bulk-Si counterpart by � 10% atVDD = 1:0V where Io� for the bulk-Si CMOS is designed to be twicehigher (see Fig. 3). As VDD is reduced, DG CMOS circuit speed rel-ative to bulk Si is enhanced (� 20% at VDD = 0:7 V) due to lowerS. For heavy-loaded circuits where Cunderlap � Cload or larger FOcases, the underlap effect on circuit delay is decreased since �delay �CloadVDD=Ion (note: �delay � CVDD=Ie� for lightly-loaded circuitswhereDIBL andS is amore significant factor for circuit delay [24]). Asshown in the insert of Fig. 6, the oversized bottom gate underlap mustbe avoided since the larger gate-to-drain overlap capacitance signifi-cantly degrades the inverter ring-oscillator performance. Fig. 7 showsMEDICI-predicted Io� versus delay for the self-aligned asymmetrical

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 9, SEPTEMBER 2005 2107

Fig. 8. MEDICI-predicted I reduction ratio by reverse bias (V ) versusV (back-gate biasing for DG nFETs and body biasing for bulk-Si nFET) atL = 25 nm and V = 1:0 V.

and symmetrical DG devices and those with 20% back-gate underlapat VDD = 1:0 V for varying Le� = 25–19 nm, compared with thebulk-Si counterpart. For equal Io� , both DG devices improve circuitperformance by more than� 15% faster even with 20% underlap. Forequal delay, Io� could be reduced by more than a factor of 4 evenfor 20% back-gate underlap. In fabrication of DG devices, the backgate-to-drain overlap might be increased by the back gate-to-sourceunderlap, which could degrade the performance especially in lightly-loaded CMOS circuits [4], [11]. Note that the underlap in the drain sidecould not significantly degrade CMOS performance and power [4].

Fig. 8 shows MEDICI-predicted Io� reduction ratio by reverse bias(VGb), (back-gate biasing for DG devices and body biasing for bulkSi) with respect to Io� at VGb = 0 versus VGb at Le� = 25 nmand VDS = 1:0 V The reverse biasing (VGb) increases the thresholdvoltage in both DG devices more substantially than that of bulk Si,thereby more reducing Io� . Furthermore, the reverse back-gate bias insymmetrical device significantly reduces the charge density, therebydramatically reducing Io� . This implies that DG CMOS could miti-gate the limit of reverse body bias scheme at short channel length [6]when back gate is separately biased in DG technology. For optimalVGb = �0:3 V(30% of VDD [25]), Io� is reduced by � 2� for bulkSi, � 7� for asymmetrical DG, and � 35� for symmetrical DG. It isalso observed in Fig. 8 that back-gate underlap in DG devices does notsignificantly impact on the Io� reduction effect by back-gate biasing.Note that the reverse substrate biasing for conventional fully-depletedSOI is not effective for leakage reduction at Le� < 25 nm [7].

V. CONCLUSION

Scaled (25-nm) DG FET simulations, accounting for SCEs and en-ergy-quantization effects on Io� and Ion, have suggested that nonself-aligned back gates, yieldingmoderate underlap, do not significantly un-dermine the superior performance and leakage current of DG CMOS.Such a pragmatic DG technology appears to be viable for both asym-metrical and symmetrical DG devices. Indeed, in addition to the ef-fects considered, the underlap can result in additional gate overlap andparasitic capacitance. Nonetheless, the high Ion of DG FETs (per unitwidth), which is � 3-times that of bulk-Si counterpart at low VDD (=0:5V) due to low S and the enhanced carrier transport [16], would ap-pear to yield very high speed even when the devices are imperfect. Re-verse back-gate biasing technique for leakage reduction appears muchmore effective, especially in symmetrical DG technology even withback-gate underlap.

ACKNOWLEDGMENT

The authors would like to thank J. G. Fossum, University of Florida,Gainesville, and W. E. Haensch at IBM for helpful discussion.

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