Oct. 5, 2001 Agrawal, Kim and Saluja 1

Partial Scan Design With Guaranteed Combinational ATPG

Vishwani D. AgrawalVishwani D. AgrawalAgere SystemsAgere Systems

Processor Architectures and Compilers ResearchProcessor Architectures and Compilers Research

Murray Hill, NJ 07974Murray Hill, NJ 07974

va@agere.comva@agere.com

Yong C. Kim and Kewal K. SalujaYong C. Kim and Kewal K. SalujaUniversity of Wisconsin, Dept. of ECEUniversity of Wisconsin, Dept. of ECE

Madison, WI 53706Madison, WI 53706

kimy@ece.wisc.edukimy@ece.wisc.edu and and saluja@engr.wisc.edusaluja@engr.wisc.edu

October 5, 2001October 5, 2001

Oct. 5, 2001 Agrawal, Kim and Saluja 2

Problem Statement Partial scan design has less DFT overhead, but is Partial scan design has less DFT overhead, but is

less desirable than full-scan because it requires less desirable than full-scan because it requires sequential ATPG.sequential ATPG.

Problem: To devise a combinational ATPG method Problem: To devise a combinational ATPG method for general for general acyclicacyclic (cycle-free) circuits; (cycle-free) circuits; cycliccyclic structures can be made acyclic by partial scan.structures can be made acyclic by partial scan.

FF1

FF2 FF2

A cyclic circuit Acyclic partial scan circuit

Oct. 5, 2001 Agrawal, Kim and Saluja 3

Overview

1. Combinational ATPG for general acyclic circuits1. Combinational ATPG for general acyclic circuits Background: Previous results and relevant ideasBackground: Previous results and relevant ideas Balanced model for combinational ATPGBalanced model for combinational ATPG Single-fault model for multiple-faultsSingle-fault model for multiple-faults Results Results

2. Special subclasses of acyclic circuits2. Special subclasses of acyclic circuits Background: Definitions and ATPG propertiesBackground: Definitions and ATPG properties ExamplesExamples Results Results

3. Conclusion3. Conclusion

Oct. 5, 2001 Agrawal, Kim and Saluja 4

Previous Work: ATPG Models for Acyclic Sequential Circuits

Iterative array model (Putzolu and Roth, Iterative array model (Putzolu and Roth, IEEETC, IEEETC, 1971) 1971)

Duplicated fan-in logic model (Miczo, 1986)Duplicated fan-in logic model (Miczo, 1986) Duplicated logic model (Kunzmann and Wunderlich, Duplicated logic model (Kunzmann and Wunderlich,

JETTAJETTA, 1990), 1990) Balanced structure (Gupta, Balanced structure (Gupta, et alet al., ., IEEETCIEEETC, 1990), 1990) Pseudo-combinational model (Min and Rogers, Pseudo-combinational model (Min and Rogers,

JETTAJETTA, 1992), 1992)

Oct. 5, 2001 Agrawal, Kim and Saluja 5

Two Relevant Results

Theorem (Bushnell and Agrawal, 2000): Theorem (Bushnell and Agrawal, 2000): A test for a testable non-flip-flop fault in a A test for a testable non-flip-flop fault in a cycle-free (acyclic) circuit can always be found cycle-free (acyclic) circuit can always be found with at most with at most ddseqseq+1 time-frames.+1 time-frames.

Balanced circuit (Gupta, Balanced circuit (Gupta, et alet al., ., IEEETCIEEETC, 1990): , 1990): An acyclic circuit is called An acyclic circuit is called balancedbalanced if all paths if all paths between any pair of nodes have the same between any pair of nodes have the same sequential depth. A combinational ATPG sequential depth. A combinational ATPG procedure guarantees a test for any testable procedure guarantees a test for any testable fault in a balanced circuit.fault in a balanced circuit.

Oct. 5, 2001 Agrawal, Kim and Saluja 6

An Example

FF

Unbalanced nodes

s-a-0

FF replaced by buffer

s-a-0

s-a-0

a

b

a1

b1

a0

b0

Balanced model

0

X

1

1

Combinational

vector

0

1/0 1/0

11/0

Test sequence: 11, 0X

dseq = 1

s-a-0

s-a-0

Multiple fault

Single fault

Oct. 5, 2001 Agrawal, Kim and Saluja 7

A Combinational ATPG System for General Acyclic Sequential Circuits

Generate a balanced model, map faults

Generate a test vector for a target fault using combinational ATPG

Simulate the comb. model to drop detected faults

No

More faults to be detected?

Yes

Obtain a test sequence from comb. vectors

Oct. 5, 2001 Agrawal, Kim and Saluja 8

A Single-Fault Model for a Multiple-FaultY. C. Kim, V. D. Agrawal, and K. K. Saluja, “Multiple Faults: Y. C. Kim, V. D. Agrawal, and K. K. Saluja, “Multiple Faults: Modeling, Simulation and Test,”Modeling, Simulation and Test,” 15 15thth International Conf. on International Conf. on VLSI Design, VLSI Design, January 2002January 2002..

Multiple stuck-at fault: lines a and b stuck-at 1 and line c stuck-at 0.

A

B

C

b

c

as-a-1

s-a-1

s-a-0

An equivalent single stuck-at fault: output of AND gate stuck-at 1

s-a-1

A

B

C

b

c

a

Oct. 5, 2001 Agrawal, Kim and Saluja 9

Proof of Correctness

Fault equivalence: Faulty output functionsFault equivalence: Faulty output functions

AAmfmf = 1 = 1

BBmfmf = 1 = 1

CCmfmf = 0 = 0

A

B

C

b

c

as-a-1

s-a-1

s-a-0

Fault equivalence: Faulty output functionsFault equivalence: Faulty output functions

AAsfsf = a = a + + 1 = 11 = 1

BBsfsf = b = b ++ 1 = 1 1 = 1

CCsfsf = c = c ·· 0 = 0 0 = 0 s-a-1

A

B

C

b

c

a

Circuit equivalence: Fault-free output functionsCircuit equivalence: Fault-free output functions

A = a + a A = a + a ··bb · ·!c = a!c = a

B = b + a B = b + a ··bb · ·!c = b!c = b

C = c C = c ··!(a !(a ··bb · ·!c) = c !c) = c ·· (!a (!a + !+ !bb + + c) =c c) =c ··(!a (!a + !+ !b) + c = cb) + c = c

s-a-1

A

B

C

b

c

a

Oct. 5, 2001 Agrawal, Kim and Saluja 10

Acyclic Circuit Comb. ATPG Example

An example An example Acyclic circuitAcyclic circuit with with 44 FFs FFs

6

2

5

43

X7FF2

1A

BC

FF1

FF3

FF4Y

D Q

D Q

D Q

D Q

D

s-a-1 s-a-1

6

2

5

43

X: W(X) = 27

BC

FF1

FF3

FF4Y

D Q

D Q

D Q

D

FF21A D Q

s-a-1 s-a-1FF2

1 D Q

s-a-1

00

11

Step 2: Balance with respect to PO Step 2: Balance with respect to PO XX..

6

2

5

43

X: W(X) = 27

B2

C2

FF1

FF3

FF4Y

D Q

D Q

D Q

D1

FF21 D Q

s-a-1 s-a-1FF2

1 D Q

s-a-1

00

1 1

A0

B0

A1

B1

Step 2: Apply DAS to PI Step 2: Apply DAS to PI AA and and BB..

6

2

5

43

X7

B2

C2

FF1

FF3

FF4Y: W(Y) = 2

D Q

D Q

D Q

D1

FF21 D Q

s-a-1 s-a-1FF2

1 D Q

s-a-1

00

1 1

A0

B0

A1

B1

Step 2: Balance with respect to PO Step 2: Balance with respect to PO YY..

6

2

5

43

X7

B2

C2

FF1

FF3

FF4 Y

D1

FF21

s-a-1 s-a-1

FF21

s-a-1

00

1 1

A0

B0

A1

B1

Step 3: Replace FFs with buffers.Step 3: Replace FFs with buffers.

6

2

5

43

X7

B2

C2

FF1

FF3

FF4 Y

D1

FF2

s-a-1

s-a-1

FF20

1

10

A0

B0

11

A1

B1

Example of Example of multiple fault multiple fault modeling.modeling.Step 1: Levelization, assign weights to POs.Step 1: Levelization, assign weights to POs.

6

2

5

43

X: W(X)=27FF2

1A

BC

FF1

FF3

FF4Y: W(Y)=2

D Q

D Q

D Q

D Q

D

s-a-1 s-a-1

Oct. 5, 2001 Agrawal, Kim and Saluja 11

ISCAS ’89 Benchmark Circuit: S5378

Circuit statisticsCircuit statistics))

Number of gates: 2,781Number of gates: 2,781 Number of FFs: 179Number of FFs: 179 Number of faults: 4,603Number of faults: 4,603

ATPG: Partial-scan S5378 Original Full-scan

Sequential Combinational Scan-FFs 0 179 30 30 Overhead 0 % 15.7 % 2.6 % 2.6 % Fault Eff. 70.9 % 100.0 % 99.7 % 99.7 % ATPG Time 5,533 s+ 1 s * 1,268 s+ 23 s*

ATPG run on Sun Ultra Sparc 10 workstationATPG run on Sun Ultra Sparc 10 workstation

*TetraMax (comb. ATPG) *TetraMax (comb. ATPG) ++Gentest (seq. Gentest (seq. ATPG)ATPG)

Oct. 5, 2001 Agrawal, Kim and Saluja 12

Acyclic Partial-Scan ISCAS’89 Circuits:Test Generation Results

CircuitName FC FE TGT(s) FC FE TGT(s)

s5378 93.69 99.71 1268.0 93.69 99.71 23.3s9234 93.16 99.94 426.0 93.16 99.94 85.7s13207 97.13 99.97 1008.0 97.13 99.97 55.0s15850 96.65 99.97 856.0 96.66 99.97 140.8s35932 89.80 100.00 569.0 89.80 100.00 79.4s38417 99.25 99.54 861.0 99.25 99.55 98.2

Sequential ATPG* Combinational ATPG

FC: cov. (%), FC: efficiency (%), TGT: CPU s Sun Ultra 10*Gentest for seq. and TetraMAX for comb. ATPG

(Hitec produced equivalent FC, FE and TGT within 10% of Gentest)

Oct. 5, 2001 Agrawal, Kim and Saluja 13

Acyclic Partial-Scan ISCAS’89 Circuits:Circuit Statistics

Circuit Total Scan Scan FFs Max MF name FFs FFs (%) depth PI Gate %s5378 179 30 16.8 19 3.21 6.50 2.1s9234 228 152 66.7 4 1.40 2.14 4.2

s13207 669 310 46.3 22 2.08 3.32 1.5s15850 597 441 73.9 29 3.27 6.98 1.4s35932 1728 306 17.7 34 2.33 3.80 1.4s38417 1638 1080 69.9 9 1.13 1.64 1.1s38584 1425 1115 78.2 35 2.32 4.13 0.3

Model Size

Oct. 5, 2001 Agrawal, Kim and Saluja 14

Acyclic

Background: Subclasses of Acyclic Circuits

Internally balanced (IB) circuit:Internally balanced (IB) circuit: Becomes Becomes balancedbalanced by splitting of PI fanouts (Fujiwara, by splitting of PI fanouts (Fujiwara, et al., et al., IEEETC, IEEETC, 2000)2000)

Strongly balanced (SB) circuitStrongly balanced (SB) circuit:: A balanced circuit A balanced circuit having the same depth from a PO to all reachable PIs having the same depth from a PO to all reachable PIs (Balakrishnan and Chakradhar, (Balakrishnan and Chakradhar, VLSI DesignVLSI Design’96)’96)

Sequential

IB SBB

Combinational

Balanced (B) circuitBalanced (B) circuit:: All paths between any pair of All paths between any pair of nodes (PIs, POs, gates or FFs) have the same nodes (PIs, POs, gates or FFs) have the same sequential depthsequential depth (Gupta, (Gupta, et al., IEEETC, et al., IEEETC, 1990)1990)

Oct. 5, 2001 Agrawal, Kim and Saluja 15

Examples of Acyclic Subclasses

An example An example AcyclicAcyclic circuit with 4 FFs circuit with 4 FFs

6

2

5

43

X7FF2

1A

BC

FF1

FF3

FF4Y

D Q

D Q

D Q

D Q

D

6

2

5

43

X7FF2

1A

BC

FF1

FF4Y

D Q

D Q

D Q

D

FF3out

FF3in

An An Internally BalancedInternally Balanced structure, requires structure, requires 11 scan FF scan FF

6

2

5

43

X71A

BC

Y

D

FF3out

FF3in

FF2out

FF2in

FF1in

FF1out

FF4out

FF4in

AA Combinational (Full-scan) Combinational (Full-scan) requires requires 4 4 scan FFsscan FFsA A BalancedBalanced structure, requires structure, requires 22 scan FFs scan FFs

6

2

5

43

X71A

BC

FF1

FF4Y

D Q

D Q

D

FF3out

FF3in

FF2out

FF2in

A A Strongly BalancedStrongly Balanced structure, requires structure, requires 33 scan FFs scan FFs

6

2

5

43

X71A

BC

FF4YD Q

D

FF3out

FF3in

FF2out

FF2in

FF1in

FF1out

Oct. 5, 2001 Agrawal, Kim and Saluja 16

Number of Scan FFs for Acyclic Subclasses

Circuit No scanName FFs Acyclic IB B SB Comb.s5378 179 30 91 96 163 179s9234 228 152 201 209 220 228s13207 669 310 420 451 542 669s15850 597 438 529 534 563 597s35932 1728 306 1728 1728 1728 1728s38417 1636 1115 1224 1232 1476 1636s38584 1452 1115 1431 1431 1447 1452Total 6729 3618 5809 5866 6336 6729

Average 0% 53.4% 78.3% 78.9% 87.2% 100.0%

Scan FFs

IB: Internally balanced, B: Balanced, SB: Strongly balanced

Oct. 5, 2001 Agrawal, Kim and Saluja 17

Comb. ATPG Coverages for Acyclic Subclasses

FC Acyclic IB B SB Comb.s5378 93.69 98.77 98.78 98.81 98.87s9234 93.16 93.47 93.47 93.95 93.95

s13207 97.13 98.43 98.46 98.87 98.87s15850 96.66 96.68 96.68 97.51 97.51s35932 89.80 89.81 89.81 89.81 89.82s38417 99.25 99.46 99.47 99.53 99.68s38584 95.46 95.52 95.52 95.54 95.57Average 96.98 97.43 97.43 97.55 97.56

ATPG: TetraMAX

Gentest and Hitec produced similar coverages

Oct. 5, 2001 Agrawal, Kim and Saluja 18

ATPG CPU Seconds for Acyclic Subclasses

Circuit Acyclic IB B SB Comb.s5378 23.3 0.6 0.6 0.4 0.2s9234 85.7 66.7 64.6 64.6 64.6

s13207 55.0 21.8 20.0 26.5 26.5s15850 140.8 115.6 113.7 113.2 112.3s35932 79.4 70.1 70.0 70.8 70.8s38417 98.2 24.2 24.2 24.8 24.8s38584 239.6 30.1 30.2 28.9 28.0

Average 103.1 47.0 46.2 47.0 46.8

ATPG: TetraMAX (on Sun Ultra workstation)

Gentest and Hitec show similar proportions

Oct. 5, 2001 Agrawal, Kim and Saluja 19

Test Lengths for Acyclic Subclasses

Circuit

Name VL CC VL CC VL CC VL CC VL CC

s5378 1,230 371 912 83 912 88 580 95 580 104

s9234 1,680 256 1,138 236 1,138 238 727 161 766 175

s13207 3,126 9,701 2,328 1,040 2,328 1,051 1,238 673 1,355 909

s15850 5,780 25,331 1,785 946 1,785 955 1,192 673 1,192 713

s35932 7,548 2,311 2,319 4,012 2,319 4,012 2,320 4,014 2,319 4,012

s38417 8,632 9,628 4,863 7,143 4,863 7,168 3,329 4,918 3,384 5,541

s38584 12,231 13,641 7,722 11,055 7,722 11,055 3,645 5,279 3,627 5,271

CombinationalAcyclic Internally Bal. Balanced Strongly Bal.

VL: Number of combinational ATPG vectors

CC: Sequential test clock cycles (x1,000) for scan sequences

Oct. 5, 2001 Agrawal, Kim and Saluja 20

Conclusion

Using a balanced circuit model and combinational Using a balanced circuit model and combinational ATPG, we can generate tests for any acyclic ATPG, we can generate tests for any acyclic sequential circuit with equal or higher fault coverage sequential circuit with equal or higher fault coverage and efficiency than obtained by sequential ATPG.and efficiency than obtained by sequential ATPG.

The proposed ATPG procedure provides comparable The proposed ATPG procedure provides comparable fault coverage and efficiency with significantly lower fault coverage and efficiency with significantly lower DFT (partial-scan) overhead as compared to DFT (partial-scan) overhead as compared to internally balanced, balanced, strongly balanced and internally balanced, balanced, strongly balanced and combinational subclasses.combinational subclasses.

The multiple fault model has new applications to The multiple fault model has new applications to diagnosis, logic optimization, multiply-testable faults, diagnosis, logic optimization, multiply-testable faults, and bridging faults (see and bridging faults (see VLSI DesignVLSI Design’02 paper). ’02 paper).

Oct. 5, 2001 Agrawal, Kim and Saluja 21

Papers Y. C. Kim, V. D. Agrawal and K. K. Saluja, Y. C. Kim, V. D. Agrawal and K. K. Saluja,

“Combinational Test Generation for Acyclic “Combinational Test Generation for Acyclic Sequential Circuits using a Balanced ATPG Model,” Sequential Circuits using a Balanced ATPG Model,” Proc. 14Proc. 14thth Int. Conf. VLSI Design Int. Conf. VLSI Design, Jan. 2001, pp. 143-, Jan. 2001, pp. 143-148.148.

Y. C. Kim, V. D. Agrawal and K. K. Saluja, Y. C. Kim, V. D. Agrawal and K. K. Saluja, “Combinational Test Generation for Various Classes “Combinational Test Generation for Various Classes of Acyclic Sequential Circuits,” of Acyclic Sequential Circuits,” Proc. Int. Test ConfProc. Int. Test Conf., ., Oct. 2001.Oct. 2001.

Y. C. Kim, V. D. Agrawal and K. K. Saluja, “Multiple-Y. C. Kim, V. D. Agrawal and K. K. Saluja, “Multiple-Faults: Modeling, Simulation and Test,” Faults: Modeling, Simulation and Test,” Proc. 15Proc. 15thth Int. Conf. VLSI DesignInt. Conf. VLSI Design, Jan. 2002., Jan. 2002.

Oct. 5, 2001 Agrawal, Kim and Saluja 22

Thank Thank youyou