BIST vs. ATPGBIST vs. ATPG

Introduction Introduction

ATPGATPG – – AAutomatic utomatic TTest est PPattern attern GGenerationeneration

BISTBIST – – BBuilt-uilt-IIn n SSelf elf TTestest

Common scan Common scan architecturearchitecture

logic test methodologies are based on a logic test methodologies are based on a full scan infrastructure full scan infrastructure all storage elements are connected togetherall storage elements are connected together

Test patterns are pre-generated using a Test patterns are pre-generated using a gate-level representation of the design gate-level representation of the design netlist netlist

Common scan Common scan architecturearchitecture

Patterns are stored in tester memory and Patterns are stored in tester memory and scanned into the circuit using parallel scanned into the circuit using parallel scan chainsscan chains

Common scan Common scan architecturearchitecture

Applying a test pattern consists of:Applying a test pattern consists of:1)1) scanning in the pattern datascanning in the pattern data

2)2) applying one or more functional clock applying one or more functional clock cyclescycles

3)3) scanning out the captured response data scanning out the captured response data

Common scan Common scan architecturearchitecture

The number of scan chains is limited by: The number of scan chains is limited by: Chip I/OChip I/O Tester channels Tester channels On-chip routing congestion On-chip routing congestion

Common scan Common scan architecturearchitecture

BIST improves the scan infrastructure by BIST improves the scan infrastructure by adding:adding: An on-chip pattern generatorAn on-chip pattern generator

Feeds the scan chains Feeds the scan chains

An on-chip result compressor An on-chip result compressor compresses the scanned out responses of all compresses the scanned out responses of all

patterns into a final signature patterns into a final signature

Where similarity ends…Where similarity ends…

ATPG – uses an on-chip pattern ATPG – uses an on-chip pattern generator as a decompressor generator as a decompressor

BIST – uses an on-chip pseudo-random BIST – uses an on-chip pseudo-random pattern generator (pattern generator (PRPGPRPG))

Breaking the myths!!!Breaking the myths!!!

Myth#1:Myth#1:

ATPG achieves better fault ATPG achieves better fault coverage than logic BISTcoverage than logic BIST

Why is that?Why is that?

BIST uses random test patterns:BIST uses random test patterns: Lower stuck@ faults coverageLower stuck@ faults coverage Designs will require a large number of Designs will require a large number of

random patterns random patterns

Solution Solution

Designs can be modified by inserting Designs can be modified by inserting scan-accessed test points to increase scan-accessed test points to increase their random pattern testabilitytheir random pattern testability

Breaking the myth Breaking the myth

Empirical evidence shows that when 1 Empirical evidence shows that when 1 test point is added per 1,000 gates (1% test point is added per 1,000 gates (1% overhead):overhead): stuck@ fault coverages achieved with stuck@ fault coverages achieved with

deterministic ATPG can be obtained with a deterministic ATPG can be obtained with a reasonable number of random patterns reasonable number of random patterns (50K to 100K range)(50K to 100K range)

Breaking the myth Breaking the myth

Chip quality really depends on physical Chip quality really depends on physical defect coveragedefect coverage True defect coverage is proportional to the True defect coverage is proportional to the

number of times each modeled fault is number of times each modeled fault is detecteddetected

Large number of random patterns results in Large number of random patterns results in significantly greater defect coverage than significantly greater defect coverage than that achieved by the limited number of that achieved by the limited number of deterministic patterns deterministic patterns

Myth#2:Myth#2:

ATPG approaches easily ATPG approaches easily scale with growing chip scale with growing chip

sizessizes

What is the problem?What is the problem?

ATPG tools typically operate on the fully ATPG tools typically operate on the fully flattened netlistflattened netlist ever-growing CPU requirementsever-growing CPU requirements growing test pattern volumesgrowing test pattern volumes significant impact on the design cycle significant impact on the design cycle

What is the problem?What is the problem?

Cores can be dealt with separately by Cores can be dealt with separately by fully isolating them with scan cellsfully isolating them with scan cells

The resulting overhead is typically The resulting overhead is typically prohibitiveprohibitive pattern volume reductions represent only in pattern volume reductions represent only in

a one-time improvementa one-time improvement

Solution Solution

Hierarchical cores are made self-testable Hierarchical cores are made self-testable independently of other coresindependently of other cores

Some patented techniques allow isolation Some patented techniques allow isolation of the core during test using little or no of the core during test using little or no overheadoverhead

SolutionSolution

Design changes in one Design changes in one core do not affect the core do not affect the logic BIST capabilities logic BIST capabilities inserted in other coresinserted in other cores

A core with logic BIST A core with logic BIST can be reused “as-is” can be reused “as-is” without any modifications without any modifications to the existing logic BIST to the existing logic BIST capabilities capabilities

More advantagesMore advantages

BIST does not require the storage of any test BIST does not require the storage of any test pattern data or require external control of pattern data or require external control of clocksclocks

it can be reused during board and system level it can be reused during board and system level testing. testing. reduces board and system manufacturing test reduces board and system manufacturing test

development costsdevelopment costs helps time-to-market through faster hardware debughelps time-to-market through faster hardware debug

When a chip fails functionally in the system, it can be When a chip fails functionally in the system, it can be debugged more reliably by running BISTdebugged more reliably by running BIST

More advantagesMore advantages

BIST can also be used for dynamic burn-BIST can also be used for dynamic burn-inin Parallel execution of logic BIST on all Parallel execution of logic BIST on all

devices on a burn-in board can be achieved devices on a burn-in board can be achieved using only the low-speed IEEE 1149.1 using only the low-speed IEEE 1149.1 interface for board-level access. Pre burn-in interface for board-level access. Pre burn-in tests can even be applied using the burn-in tests can even be applied using the burn-in board, eliminating a test insertion board, eliminating a test insertion

Conclusion Conclusion

ATPG continues to try to provide ATPG continues to try to provide techniques to meet the testing challenges techniques to meet the testing challenges of complex designsof complex designs

BIST capabilities originally developed to BIST capabilities originally developed to address these high-end design test has address these high-end design test has become field hardened and field proven become field hardened and field proven solutions solutions