7/23/2019 Novel Level-up Shifters for High Performance and Low Power

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Abstract--This paper presents novel level-up shifters called

Dual Step Level-up Shifter (DSLS) and Stacked Dual Step Level-

up Shifter (SDSLS) which are simpler, yet more efficient than

conventional level-up shifters. We compare the proposed designs

with two existing designs: a conventional level-up shifter and

Contention-Mitigated Level Shifter (CMLS). The delay of the

proposed designs is less than that of a conventional level-up

shifter and CMLS by up to 4.86% and 6.51%, respectively. The

power consumption of the proposed designs is less than that of a

conventional level-up shifter and CMLS by up to 6.68% and

5.40%, respectively. DSLS and SDSLS act as a power gating

circuit as well as a level-up shifter. Thus, we conclude that our

proposed designs are very effective for low power designs.

I.

INTRODUCTION

Delay and power consumption are important in mobile

application processors (APs), since the market size of mobile

devices such as smart phones and tablet PCs is growing fast

[1]. Low power design techniques with multiple voltage

supplies are commonly used in the mobile APs where a high

voltage region is used for high performance and a low voltage

region is used for low power consumption to reduce the

dynamic power consumption [2], [3]. When two blocks in

different voltage regions are interacting with each other, we

need to have an interface to adjust the voltage levels. Such

interface logic is called level shifters. Among level shifters, a

level-up shifter has the worse delay and power consumption,since a level-up shifter is more complicated than a level-down

shifter. Therefore, active studies have been conducted to

improve level-up shifters. In this paper, we propose novel

level-up shifters called Dual Step Level-up Shifter (DSLS) and

Stacked Dual Step Level-up Shifter (SDSLS) which are

simpler, yet more efficient than conventional ones.

II.

DSLSAND SDSLS

"This research was supported by the MKE(The Ministry of

Knowledge Economy), Korea, under the ITRC(Information

Technology Research Center) support program supervised by the

NIPA(National IT Industry Promotion Agency)" (NIPA-2012-

H0301-12-1011)

Fig. 1 (A) and (B) show a conventional level-up shifter and

a conventional level-down shifter, respectively. The

conventional level-up shifter which consists of 10 transistors is

more complicated than the conventional level-down shifter.

The conventional level-up shifter is complicated mainly

because of its differential signaling structure. Since it takes

more effort to level up to a high voltage region, the

conventional level-up shifter stably levels up voltage by the

differential signaling structure. Thus, the conventional level-up

shifter has large delay and power consumption. For high

performance and low power consumption, Dual Step Level-up

Shifter (DSLS) and Stacked Dual Step Level-up Shifter

(SDSLS) are proposed.

Fig. 2 (A) shows the proposed DSLS. DSLS has a stepping

level-up structure where each inverter of the buffer structure issupplied by different voltages. The supply voltage of the back

inverter which consists of P3 and N2 is VDDH. On the other

hand, the supply voltage of the front inverter which consists of

P2 and N1 is lower than VDDH. As shown in Fig. 2 (B), when

the input is VDDL, P2 stays ON due to the low voltage so that

some current flows along the path of P1, P2 and N1. Thus, the

voltage of the VX is VDDH-IR, because of the voltage drop in P1

transistor channel.

Fig. 3 shows the amount of current and the amount of

voltage drop at node VX according to the change in VDDL in

Fig. 2 (A) when VDDHis set to 1.0V.From Fig. 3, we confirm

Novel Level-up Shifters for High Performance and Low Power

Mobile Devices

Dong-Ik Jeon and Kwang-Soo Han and Ki-Seok Chung

Department of Electronics and Computer Engineering, Hanyang University, Republic of Korea

P2 P3

N1 N2

VDDH

P1

IN OUT

VX

Front Back

(A) Structure of DSLS

IN (VDDL)

P2 P3

P1 (R)

N1N2

OUT

VDDH

VDDH- IR

Some Amount

of Current (I)

(B) Pull-down Operation of DSLS

Fig. 2. Dual Step Level-up Shifter (DSLS)

IN

OUT

VDDL

VDDH

VDDHP1 P2

N1 N2

VDDL

VDDH

(A) Conventional Level-up Shifter

P2 P3

N1 N2

IN OUT

VDDL

(B) Conventional Level-down Shifter

Fi . 1. Conventional Level Shifters

Fig. 3. Some Amount of Current and Voltage Drop in VXof DSLS

978-1-4673-1363-6/13/$31.00 2013 IEEE

2013 IEEE International Conference on Consumer Electronics (ICCE)

181

Novel Level up Shifters for igh Performance and Low Power

obile evices

7/23/2019 Novel Level-up Shifters for High Performance and Low Power

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that the voltage drop in VXis adequate so that DSLS may be

used for a level-up shifter by employing a stepping level-up.

However, due to significant amount of current, DSLS is not

appropriate to be used in low power designs with multi-VDD.

Therefore, we employ transistor stacking [4] in the DSLS to

reduce the leakage power consumption while maintaining the

good delay characteristics of DSLS.

Fig. 4 shows the proposed SDSLS which reduces the

amount of current. However, the amount of current strongly

influences the voltage drop in VXfor a stepping level-up. From

Fig. 5, the voltage drop of SDSLS in VXis bigger than DSLS.

The reason is that P2 has a huge resistance, since the gate of

P2 is driven by VDDL. However, VXof SDSLS does not change

according to the change in IN due to a huge resistance in P2.

Therefore, we can maximize the performance of the level-up

shifter by applying DSLS when the input voltage is more than

0.8V and applying SDSLS when the input voltage is less than

0.8V.

Fig. 6 shows that DSLS and SDSLS can act as a power

gating circuit, if the gate of PMOS (P1) which is always-on is

driven by the control signal instead of the ground. Thus,

applying the power gating in DSLS and SDSLS can cut off the

signal from the previous block to the next block. This is very

effective in low power designs such as a multi-voltage system.

III.

SIMULATION

To evaluate the quality of the proposed design, we

compared the proposed design with two existing designs: a

conventional level-up shifter and CMLS [5]. We designed a

simple mobile AP system with multiple supply voltages. We

set the supply voltage of a cache memory to 0.7V and the

supply voltage of a register to 1.0V. We used SDSLS as level-

up shifters in the system design, since the voltage differencebetween a cache memory and a register is 0.3V.

Table I shows that the delay of the proposed design is less

than that of a conventional level-up shifter and CMLS by up to

4.86% and 6.51%, respectively. The power consumption of the

proposed design is less than that of a conventional level-up

shifter and CMLS by up to 6.68% and 5.40%, respectively.

IV.

CONCLUSION

Recently, low power consumption has become one of the

most critical design issues. Designing a system with supply

voltages is one of the most popular low power design

techniques. For two regions with different voltage domains to

interact properly, level shifters are required. In this paper, we

proposed novel level-up shifters called Dual Step Level-up

Shifter (DSLS) and Stacked Dual Step Level-up Shifter

(SDSLS). In order to maximize the performance, we can use

DSLS when the input voltage is more than 0.8V. On the other

hand, we can use SDSLS when the input voltage is less than

0.8V. DSLS and SDSLS can act as a power gating circuit as

well as a level-up shifter. Therefore, we conclude that our

proposed designs are very effective for low power designs.

V. REFERENCES

[1]

A. P. Chandrakasanet.al., Minimizing power consumption in digital

CMOS circuits, Proceedings of the IEEE, vol.83, no.4, pp.498-523,

1995.

[2] A. Gayasen, K. Lee, N. Vijaykrishnan, M. Kandemir, M.J. Irwin, and T.

Tuan, A Dual-VDD Low Power FPGA Architecture, Field-

Programmable Logic and ApplicationsFPL, pp. 145-157, 2004

[3]

Sarvesh H. Kulkarni, Dennis Sylvester, Power distribution techniques

for dual VDD circuits, ASP-DAC '06 Proceedings of the 2006 Asia

and South Pacific Design Automation Conference, pp. 838-843, 2006

[4]

Siva Narendra, Vivek De, Dimitri Antoniadis, Anantha Chandrakasan,

Shekhar Borkar, Scaling of stack effect and its application for leakage

reduction, International Symposium on Low Power Electronics and

Design - ISLPED , pp. 195-200, 2001

[5]

Canh Q. Tran, Hirosh Kawaguchi, Takayasu Sakurai, Low-power

High-speed Level Shifter Design for Block-level Dynamic Voltage

Scaling Environment, IEEE International Conference on Integrated

Circuit Design and Technology - ICICDT , 2005

Front Back

P3 P4

N1 N2

VDDH

P1

IN OUT

VX

P2

Fig. 4. Stacked Dual Step Level-up Shifter (SDSLS)

Fig. 5. Some Amount of Current and Voltage Drop in VXof SDSLS

P2 P3

N1 N2

VDDH

P1

IN OUT

VX

Control

(A) Applying the Power Gating in DSLS (B) Applying the Power Gating In Stacked DSLS

P3 P4

N1 N2

VDDH

P1

IN OUT

VX

P2

Control

Fig. 6. Some Amount of Current and Voltage Drop in VXof SDSLS

TABLEI

COMPARISON OF LEVEL-UP SHIFTERS

Conventional CMLS SDSLS

Rising [ns] 34.90 34.97 33.09

Falling [ns] 10.37 11.10 9.989

Delay Average 22.64 23.04 21.54

Power [mW] 214.1 211.2 199.8

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