Non Determinism

8/12/2019 Non Determinism

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Non-Determinism In C and RTL Models

ICCAD 2006 Ira Chayut, Verification Architect


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2006 NVIDIA Corporation Slide 2

C Models in a Variety of Languages

C Model == Reference Model

Reference Model could be in C, C++, Perl, Python,

Java, Verilog, SystemVerilog, SystemC, emulation,silicon rendition of the Device Under Test (DUT),etc.

The DUT can be any implementation,this presentation assumes a Verilog RTL DUT


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Validation vs. Verification

Validation: answers the question:Does the mo del prod uce the cor rec t ou tp ut?

Verification: answers the question:Does the DUT behavior m atch th at of thereference m od el?


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A Typical Verification Example

Stimulus is applied to the C model and the DUT.The outputs are then compared.


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Causes of Mismatches

Errors in:DUTC model

stimuluschecker codecompiler or simulator

Differences in the way models handle time


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Determinism / Non-Determinism

According to Wikipedia:In a determinis t ic s ys tem, every act ion , or c ause , prod uc esa react ion , or effect , and every react ion , in turn , becom esthe cause of s ub sequent react ion s . The to ta l i ty of thesecascading events can theoret ica lly sho w exact ly how thesys tem wi l l ex i s t a t any m om ent in t ime .

Thus, a non-deterministic system is one whereknowing the state of a model and the stimulus, we

cannot precisely know the next state and outputAt Nvidia the term non -determinism is used forsituations where the C model cannot predict theDUTs behavior


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Causes of Non-Determinism

Independence between C model and DUT

Architectural vagueness

Efficiency

Points of arbitration (including memories and

caches)


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Time and Non-Determinism

Timed-events are thelargest cause of non-determinism, including:

Memory accessesCache fills/hits/misses

Time-outs

Multiple clock domains

Clock jitter in silicon


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Non-Determinism Work-Arounds

Hints from DUT

Cycle-accurate C models

Smart checkers

Dont verify non -deterministic cases


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Non-Determinism Example

MUX selects stimulusuntil:

FIFO full, or

Timer reaches time-out

C model does not haveconcept of time

RTL sees time-outs thatC model does not

!=


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Hints from DUT

DUT simulation:

provides hints tountimed C model

gates the C model

weakens theindependent checkby C model

==


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Cycle-Accurate C Model

Slows C model runs

Slows C modeldevelopment

Problem modeling jitter between asyncclock domains

Weakens theindependent checkof C model


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Smart Checkers

Match out-of-order transactions

Ignore dont care bits

Recognize acceptable extra transactions

Score-board transactions to catch spurious

transactions

Statistical analysis needed sometimes


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Dont Verify Non -Deterministic Cases

Some cases too difficultto test

Verify later-stage

resultsValidate DUT

Validate in silicon

Avoid non-deterministicdesigns


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Conclusions

C model and DUT behavior may vary for somestimulus, but both behaviors are correct

Time-based behavior is especially problematic

When non-determinism cannot be avoided:Smart checkers

Cycle-accurate C modelsDUT hintsValidate DUT or silicon

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Non Determinism