IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 4, APRIL 2001 803

IV. CONCLUSION

Using a porous silicon layer as the semi-insulating substrate for�-SiC high temperature photo-sensing device has been demonstratedsuccessfully with a M–S–M photoconductor. The high resistivity andthe flexibility of the porous silicon retard the transportation and thegeneration of the leaky current thus improving the high temperatureoptical performance of the�-SiC device. Experimentally, a 40mA/cm2 current density etched PS layer possesses a resistivity around7�107 -cm and with a porosity suitable for growing good�-SiClayer to fabricate high temperature optical-sensing devices.

REFERENCES

[1] K. H. Wu, Y. K. Fang, J. J. Ho, W. T. Hsieh, W. H. Chang, and J.D. Hwang, “A high optical-gain�-SiC bulk-barrier phototransistor forhigh-temperature application,”IEEE Photonics Technology Letters, vol.10, no. 11, pp. 1611–1613, Nov. 1998.

[2] T. L. Lin, L. Sadwich, K. L. Wang, Y. C. Kao, R. Hull, C. W. Nieh, D.N. Jamieson, and J. K. Liu, “Growth and characterization of molecularbeam epitaxial GaAs layers on porous silicon,”Appl. Phys. Lett., vol.51, no. 14, pp. 814–816, 1987.

[3] K. Maehashi, M. Sato, S. Hasegawa, H. Nakashima, T. Ito, and A. Hiraki,“Initial stage of GaAs molecular beam epitaxy growth on porous Si,”Jpn. J. of Applied Physics, vol. 30, no. 4B, pp. L683–L685, April 1991.

[4] R. L. Smith and S. D. Collins, “Porous silicon formation mechanisms,”J. Appl. Phys., vol. 71, no. 8, p. R1, 1992.

[5] V. Lemamn and U. Gosele, “Porous silicon formation-A quantum wireeffect,” Applied Physic Letter., vol. 58, p. 856, 1991.

[6] J. D. Hwang, Y. K. Fang, Y. J. Song, and D. N. Yaung, “Epitaxialgrowth and electrical characteristics of�-SiC on Si by low-pressurerapid thermal chemical vapor deposition,”Jpn. J. Appl. Phys., vol. 34,pp. 1447–1450, 1995.

[7] S. I. Long and S. E. Buther,GaAs Digital IC Design, ch. 1.

Noise Modeling and Characterization for 1.5-V 1.8-GHzSOI Low-Noise Amplifier

Wei Jin, Weidong Liu, Chaohe Hai, Philip C. H. Chan, andChenming Hu

Abstract—SOI technology is a promising candidate for radio-frequencyand microwave applications. In this work, SOI low-noise amplifiers (LNA)operating at 1.8-GHz under 1.5-V power supply are reported for the firsttime and the high-frequency noise characteristics are studied. A physicalSOI thermal noise model is applied, and all the major noise sourcesassociated with the transistors are modeled. SPICE simulation results ofthe circuit noise agree well with the measurement data. LNA composedof floating-body SOI devices offers better performance than that withbody-tied devices.

Index Terms—Induced gate noise, low-noise amplifier (LNA), SOIMOSFET, thermal noise.

I. INTRODUCTION

CCMOS is competing against bipolar and GaAs in the radio-fre-quency integrated circuits (RFIC) arena for wireless commu-

nications. SOI technology earns more credit for the Si-based CMOSfamily attributed to its excellent RF performance. SOI promises betterdevice characteristics than bulk technology, and the buried oxide re-duces substrate noise coupling in high-frequency circuits. Noise per-formance is one of the major concerns in RFIC. In this paper we studythe noise characteristics of partially-depleted (PD) SOI low-noise am-plifiers composed of floating-body (FB) devices and body-tied (BT)devices, respectively. LNAs operating at 1.8-GHz under 1.5-V powersupply are reported for the first time. The circuits under study showbetter performance in terms of gain and noise figure (NF) than mostof the reported LNAs [1]–[6]. To simulate the noise characteristics ofthe circuits, BSIMPD2.1 model [7] and a physical SOI thermal noisemodel [8] are applied in SPICE [9], and all the major thermal noisecomponents in the device are considered. In Section II, the LNA designmethodology is discussed and the fabrication process features are pre-sented. The measurement data of the circuit performance are presentedin Section III, and the comparison of the LNAs under study with otherreported circuits is made. In Section IV, a detailed high-frequency noisemodel for LNA is presented and SPICE noise analyzes of LNAs withfloating-body and body-tied devices are performed. The simulation re-sults agree well with the experimental noise data.

II. LNA D ESIGN AND FABRICATION

Fig. 1 shows the block diagram for a generic RF receiver. Accordingto Friis Equation [10]

NFtotal = NF1 +NF1 � 1A1

+ � � �+NFN � 1

A1 � � �AN

(1)

where NF is the noise figure andAN is the gain of stageN , LNAmust have excellent noise performance itself while providing enough

Manuscript received November 22, 1999; revised March 10, 2000. This workwas supported by RGC Earmarked Grant HKUST 6025/97E. The review of thispaper was arranged by Editor C.-Y. Lu.

W. Jin and P. C. H. Chan are with the Department of Electrical and Elec-tronic Engineering, The Hong Kong University of Science and Technology,Clear Water Bay, Hong Kong (e-mail: eepchan@ust.hk).

W. Liu and C. Hu are with the Department of Electrical Engineering andComputer Science, University of California, Berkeley, CA 94720 USA.

C. Hai is with Microelectronics R&D Center, Chinese Academy of Science,Beijing, China.

Publisher Item Identifier S 0018-9383(01)00785-7.

0018–9383/01$10.00 © 2001 IEEE

804 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 4, APRIL 2001

Fig. 1. Block diagram of a typical RF receiver.

Fig. 2. Inductive degeneration technique for input impedance matching.

Fig. 3. Schematic of the SOI LNA under study. The on-chip devices includetransistorsM andM and source degeneration inductorL .

gain to overcome the noise in successive stages. However, the sourceimpedance designed for a minimum NF will lead to a poor gain,because the input impedance (50-) matching, a critical requirementfor LNA, is not satisfied. Among the many techniques for input50- matching, inductive source degeneration (Fig. 2) has beendemonstrated to exhibit minimum noise [3]. A single-transistorcommon-source LNA normally cannot provide the required high gain.Therefore, the cascode configuration as shown in Fig. 3 is selected.The cascoding transistor also improves the stability by isolating theMiller capacitance ofM1 from the output. Low-power dissipationis yet another advantage of the cascode topology, because the twotransistors share the same bias current.

To optimize NF and gain under a reasonable power budget, thechannel width of the device is given by [11]

W =1

3!0LCoxRs

(2)

where!0 is the center frequency of the LNA,Rs is the 50- sourceimpedance.

To determine the inductor values, examine the following equationfor Fig. 2:

Zin =gmCgs

Ls + s(Lg + Ls) +1

sCgs

=!TLs = 50 (at resonance): (3)

As a rule of thumb, the operation frequency of a narrow-band ampli-fier is typically 1/5 of the transistor unity-gain frequency (fT ), i.e.,

Fig. 4. Inductance and theQ-factor of the on-chip spiral inductors.

!T =!0 � 5. Hence, for 1.8-GHz Personal Communication Systems(PCS),Ls is less than 1 nH, which is easy to implement by an on-chipspiral inductor. The center frequency is determined by

f0 =1

2� (Lg + Ls)Cgs= 1:8GHz: (4)

Since the geometry of the transistor has been fixed, the gate inductanceLg is found to be around 7 nH. The largeLg has to be made off-chip,otherwise its quality-factor (Q) will substantially degrade the noise per-formance of the circuit. The channel-width of the cascoding device,M2, is designed to be the same as that ofM1. This is the trade-off be-tween the suppression of Miller effect ofM1 and the noise magnitudeof M2 [11].

The LNA circuits are fabricated on SIMOX wafer with conventionalsubstrate resistivity (20-cm). The buried-oxide thickness is 360 nm.The fabrication process uses 0.6�m PD SOI technology and the effec-tive channel length (Le� ) is 0.5�m. The front-gate oxide is 9 nm andthe Si film thickness is 150 nm. For circuit performance consideration,in addition to the TiSi2 salicide, metal-shunt is applied to the poly-gateto further reduce the gate resistance. LNAs comprised of floating-body(FB) and body-tied (BT) SOI devices are fabricated, respectively. InBT devices, the body is tied to the source through side-contact. AtVds = Vgs = 1:5 V, thefT of FB device is around 12-GHz while thatof BT device is roughly 11-GHz. On-chip spiral inductors are madeof the top layer of aluminum (metal-2) with a thickness of 3�m. Ontop of metal-1, a thick layer of oxide (2.3�m) is deposited to improvetheQ-factor of the inductor. Among the different device isolation tech-niques, LOCOS is applied to further increase the oxide thickness un-derneath the inductor. As shown in Fig. 4, spiral inductors made onSOI wafers exhibit a higherQ than on bulk wafers. This is because theburied-oxide reduces the parasitic capacitance to the substrate, leadingto less substrate loss.

To minimize the thermal noise coupling from the substrate resis-tance, the RF pad layout design employs the technique proposed by [6]as shown in Fig. 5. For conventional pad design, the entire pad (metal-2)is shorted to metal-1. Hence, the substrate noise will be coupled to thecircuit through the large capacitance (C2) between metal-1 and sub-strate. For RF input pad, a shielding layer of metal1 is underneath thepad, and only a small portion of the pad is routed to the circuit. As aresult,C2 is considerably reduced and the thermal noise due to the sub-strate resistance is minimized.

The die-photo of the floating-body SOI LNA is shown in Fig. 6.The two transistors have interdigitated gate structure and share thesource/drain to minimize parasitics. On-chip capacitors are connected

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 4, APRIL 2001 805

Fig. 5. Structure of RF pad. Only a small portion of the pad is shorted tometal-1, substrate noise coupling is minimized.

Fig. 6. Die-photo of the floating-body SOI LNA.

to the gate of the cascoding transistor to filter the noise from the biasingcircuitry.

III. CIRCUIT PERFORMANCE

The on-chip components include the two transistors and the sourcedegeneration inductor. The input and output impedance matching net-works and biasing circuitry are implemented externally by microstriplines on PCB [12]. The relative dielectric constant ("r) of the microstripline substrate is 4.1, the height of the dielectric is 55 mils and thewidth of the metal is 110 mils. Two types of SOI LNAs with iden-tical topology are characterized, one composed of FB devices whilethe other composed of BT devices.

Stability of the circuit is examined prior to the implementation of theimpedance matching network. The necessary and sufficient conditionsfor unconditional stability are given by [12]:

K =1� jS11j

2 � jS22j2+ jS11S22 � S12S21j

2

2jS12S21j> 1 (5)

B1 =1 + jS11j2 � jS22j

2 � jS11S22 � S12S21j2> 0: (6)

As shown in Fig. 7, the above conditions are satisfied in the SOI LNA.Fig. 8 shows that the input impedance matching for the FB LNA is

obtained atf0. In RFIC, normally the capacitive load (Cload) is theinput capacitance of the mixer. Suppose the value ofCload is in theneighborhood of 1 pF, then the inductive loadLload should be around8 nH. In this work,Lload is implemented by a bond-wire withQ-factoraround 20 atf0. The gain (S21) of LNA is measured by HP8510CNetwork Analyzer [13] and the results are shown in Fig. 9. The gain of

Fig. 7. Stability factorsK andB in FB SOI LNA.

Fig. 8. S in Smith chart of the FB SOI LNA. The input impedance matchingis achieved at the center frequencyf .

FB circuit is higher, which is attributed to the lower threshold voltageof FB devices than that of BT devices for the same channel doping. Itis critical to correct the misconception that the kink in the drain currentdegrades the output resistance of FB SOI devices. Strictly speaking,this is true at low frequency only. The floating-body in SOI MOSFETis a lowpass filter, the bias-dependent characteristic frequency of thefloating-body is typically below 1 MHz [14]. At high frequency, the ACfloating-body effect (FBE) is suppressed. Hence, the output resistanceof FB devices at the LNA operation frequency is as good as that of BTdevices, and the gain of FB LNA will not be affected by AC FBE.

Besides the power consumption, impedance matching, gain and NF,the linearity is also an important consideration of LNA. The small-signal linearity of the LNAs are measured in terms of the third-orderintercept point. Two-tone test (f0 = 1:8 GHz,f1 = 1:81 GHz) showsthat the input-referred IP3 of the FB SOI LNA is�10.5 dBm and thatof the BT SOI LNA is�11.2 dBm. The noise performance will bediscussed in Section IV together with the SPICE simulation results. Therecent researches on Si-based CMOS LNA are summarized in Table I.The LNAs in this work provide sufficiently high gains with low noisefigures.

806 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 4, APRIL 2001

TABLE ISUMMARY OF RECENT LNA RESULTS

Fig. 9. LNA gain vs. frequency. The circuit with FB devices has higher gain.

IV. LNA N OISE MODELING AND SPICE SIMULATION

An accurate dc model for the SOI device is indispensable for the cir-cuit noise model. In the SPICE simulation of this work, BSIMPD2.1model is implemented and a physical thermal noise model for SOIMOSFET is applied. In addition, all the parasitic resistances whichcontribute to the total output thermal noise are modeled, this includesthe poly-gate sheet resistance, drain/source series resistance, body re-sistance and inductor series resistance. The induced gate noise is alsoconsidered due to its significance at high frequency.

Thermal noise of an SOI device operated in saturation region is givenby [8]

Sid =4kIdsL2

e�

L

0

Tc1(x)

E1(x)dx+

L

L

Tc2(x)

E2(x)dx (7)

whereLsat length from the source to the point where velocity sat-

uration occurs.Tc1(E1) carrier temperature as a function of electric field in the

region where gradual channel approximation (GCA)holds, and

Tc2(E2) carrier temperature as a function of electric field in thevelocity saturation region.

However, the above physical model does not have a close form. There-fore, it cannot be implemented in SPICE. To make use of this model,

Fig. 10. Channel thermal noise of a floating-body SOI MOSFET.

the transistor thermal noise is first calculated by numerical integrationThen, the equivalent conductance for channel thermal noise is obtained:

geq =Sid4kT

(8)

whereT is the room temperature.geq is used by SPICE for transistorchannel thermal noise simulation. As shown in Fig. 10, the physicalchannel thermal noise model for FB SOI MOSFET fits the measure-ment data.

Gate is laid out as an interdigitated structure with contacts at bothends. The distributed gate resistance is given by [3]

Rg =RshW

12n2L(9)

whereRsh is the sheet resistance of the poly-gate andn is the numberof fingers.

The drain/source series resistance (Rds) can be modeled as

Rd; s =Rds

2n(10)

whereRds is the total source and drain series resistance characterizedby a single-finger device with channel width equal toWe�=n.

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 4, APRIL 2001 807

Fig. 11. External body-contact terminal is supported by BSIMPD2.1 model.

Fig. 12. Thermal noise of the body resistance in BT SOI and FB SOI devices.

For a body-tied SOI MOSFET, the body resistance from the contactsto the internal body exhibits thermal noise. BSIMPD2.1 model supportsan externally accessible body-contact terminal,P , as shown in Fig. 11.The effective body resistance is modeled as

Rb e� = Rb (11)

whereRb is the body resistance of a single-finger BT device withchannel widthWe�=n.

Fig. 12 shows the thermal noise due to the body resistance in BT andFB devices. For a BT device, the additional drain current noise due tothe body resistance is given by

�Sid1 = 4kTRb1 �1=j!Cdep

Rb1 + 1=j!Cdep

2

� g2mb1 (12)

whereRb1 is the body resistance andgmb1 is the body-transconduc-tance. Similarly, for a FB device we have

�Sid2 = 4kTRb2 �1=j!Cdep

zdiode +Rb2 + 1=j!Cdep

2

� g2mb2 (13)

wherezdiode is the small-signal impedance of the body-source diode.Since the body resistance in a BT device (Rb1) is much larger than thatin a FB device (Rb2), BT SOI device generates higher noise power forany given bandwidth.

All the parasitic resistances (thermal noise contributors) in abody-tied SOI LNA are shown in Fig. 13, including the inductanceseries resistance.

Finally, the induced gate noise must be considered as it becomessignificant at high frequency. The spectral density of the induced gatenoise is modeled as [15]:

Sig = 4kT�gg (14)

where� is around 4/3 and the noise gate conductance is given by

gg =!2C2

gs

5gd0(15)

Fig. 13. Thermal noise sources in body-tied SOI LNA.

Fig. 14. Induced gate noise in the input deviceM . For simplicity, g isneglected due to the largeQ of C at the operation frequency.

wheregd0 is the drain conductance atVds = 0. To examine the signif-icance of the induced gate noise, we need to figure out how much ofthe total output noise is attributed to the channel thermal noise and theinduced gate noise, respectively.

As a result of the feedback ofLs, the output noise due to the channelthermal noise ofM1 is given by [3]

So id1 =Sid1

1 +!TLs

Rs

2�

Sid14

(16)

whereSid1 is the channel thermal noise ofM1, andRs is the RF inputsource impedance, which is 50- in our measurement system. The in-duced gate noise ofM1 is shown in Fig. 14. For simplicity,gg is ne-glected as theCgs has a highQ-factor at the LNA operation frequency.The gate noise at the output can be derived as

So ig1 = Sig1!T!0

2R2

s + [!0(Lg + Ls)]2

(Rs + !TLs)2� 30 � Sig1 (17)

whereSig1 is the induced gate noise ofM1 at the input. For the cas-coding deviceM2 as shown in Fig. 15, the output noise due to thechannel thermal noise is

So id2 =Sid2

1 + gm2 zo11

sCgs

2

�

Sid2

1 +!T!0

2� Sid2 � 4% (18)

808 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 4, APRIL 2001

Fig. 15. Drain current noise and the induced gate noise in the cascoding deviceM .

Fig. 16. Noise figures of LNAs versus power supply.

Fig. 17. Noise figures of LNAs versus frequency.

wherezo1 is the output impedance ofM1. The output noise due to theinduced gate noise is

So ig2 =Sig2

1 +1

gmzo1+sCgs

gm

2� Sig2: (19)

In the above calculation, the poly-gate resistance, the source/drain se-ries resistance and the inductor series resistance are all neglected.

The channel thermal noise ofM1 andM2 are similar, as the twotransistors are identical in geometry and share the same dc current.Therefore, as indicated by (16)–(19), the noise contribution of the cas-coding device is much smaller than that of the input device. At the LNAoutput, the noise generated inM2 is substantially reduced as a resultof the negative feedback path formed byM1. Given the partial correla-tion between the induced gate and the channel thermal noise [15], one

can further derive from (16) and (17) and conclude that the total outputnoise will be underestimated by approximately 1/3 if only the channelthermal noise is considered.

SPICE simulation applies the physical channel thermal noise modeland taking into account the induced gate noise and all the noise sourcesdue to parasitic resistances. Figs. 16 and 17 show that the simulation re-sults agree well with the measured NF of the two types of SOI LNA’s.The noise figure of the circuit is measured by HP8970B [16] NoiseFigure Meter. BT circuit shows worse noise performance than FB cir-cuit, because the body-contact resistance in BT devices leads to highernoise. Since a highgm helps improve NF [3], NF decreases slightlywith the power supply as shown in Fig. 16. The noise figures of thetwo types of circuits versus frequency are plotted in Fig. 17. The de-pendence of NF on frequency is due to the induced gate noise and theimpedance of the matching network. Based on the simulation results,it is found that approximately 70% of the total noise is attributed tothe channel thermal noise of the SOI devices. The induced gate noise(mainly fromM1) is another major noise source which accounts forabout 25% of the total noise, and the remainder is due to the thermalnoise associated with all the parasitic resistances.

V. CONCLUSION

SOI LNAs composed of floating-body and body-tied devices, re-spectively, are reported for the first time. The cascode-topology cir-cuits operating at 1.8-GHz under 1.5-V power supply and are suitablefor PCS receivers. Detailed noise models for SOI LNAs are presented.Based on BSIMPD2.1 model and a physical thermal noise model forSOI MOSFET, SPICE simulation results agree well with the experi-mental data. FB SOI LNA provides higher gain and lower noise figurethan BT SOI LNA. Therefore, FB SOI devices are more suitable forfront-end amplifiers in RF receivers.

ACKNOWLEDGMENT

The authors would like to acknowledge Z. Zhang, HKUST, for thevaluable discussions on LNA and PCB design. The suggestions fromthe reviewers were much appreciated.

REFERENCES

[1] R. A. Johnsonet al., “Advanced thin-film silicon-on-sapphire tech-nology: Microwave circuit applications,”IEEE Trans. Electron Devices,vol. 45, p. 1047, May 1998.

[2] M. Harada, C. Yamaguchi, and T. Tsuchiya, “Investigation of a multi-gigahertz MOSFET amplifier with an on-chip inductor fabricated ona SIMOX wafer,” IEEE Trans. Electron Devices, vol. 45, p. 173, Jan.1998.

[3] D. K. Shaeffer and T. H. Lee, “A 1.5-V, 1.5-GHz CMOS low noise am-plifier,” IEEE J. Solid-State Circuits, vol. 32, no. 5, p. 745, 1997.

[4] D. K. Shaefferet al., “A 115-mW, 0.5-�m CMOS GPS receiver withwide dynamic-range active filters,”IEEE J. Solid-State Circuits, vol. 33,p. 2219, 1998.

[5] C.-Y. Wu and S.-Y. Hsiao, “The design of a 3-V 900-MHz CMOS band-pass amplifier,”IEEE Trans. Electron Devices, vol. 32, p. 159, Feb.1997.

[6] A. Rofougaran, J. Y. C. Chang, M. Rofougaran, and A. A. Abidi, “A 1GHz CMOS RF front-end IC for a direct-conversion wireless receiver,”IEEE J. Solid-State Circuits, vol. 31, p. 880, 1996.

[7] “BSIMPD2.1 manual,”, http://www-de-vice.eecs.berkeley.edu/~bsimsoi..

[8] W. Jin, P. C. H. Chan, and J. Lau, “A physical thermal noise model forSOI MOSFET,”IEEE Trans. Electron Devices, vol. 47, Apr. 2000.

[9] 94 720T. Quarles, A. R. Newton, D. O. Pederson, and A. Sangiovanni-Vincentelli, “Spice3 version 3F5 user’s manual,” Univ. Calif., Berkeley,CA, 1994.

[10] B. Razavi,RF Microelectronics. Englewood Cliffs, NJ: Prentice-Hall,1998.

[11] T. H. Lee,The Design of CMOS Radio-Frequency Integrated Circuits:Cambridge Univ. Press, 1998.

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 4, APRIL 2001 809

[12] G. Gonzalez,Microwave Transistor Amplifiers Analysis and Design, 2nded. Englewood Cliffs, NJ: Prentice-Hall, 1997.

[13] HP 8510C Network Analyzer Operating Manual. Palo Alto, CA,USA: Hewlett-Packard Company.

[14] W. Jin, P. C. H. Chan, S. K. H. Fung, and P. K. Ko, “Shot-noise-in-duced excess low-frequency noise in floating-body partially depletedSOI MOSFET’s,”IEEE Trans. Electron Devices, vol. 46, p. 1180, June1999.

[15] A. Van Der Ziel,Noise in Solid State Devices and Circuits. New York:Wiley , 1986.

[16] HP 8970B Noise Figure Meter Operating Manual. Palo Alto, CA:Hewlett-Packard Co., 1993.

New Approach for Defining the Threshold Voltage ofMOSFETs

J. A. Salcedo, A. Ortiz-Conde, F. J. García Sánchez, J. Muci,J. J. Liou, and Y. Yue

Abstract—The threshold voltage of MOSFETs has traditionally beendefined as the gate voltage required to cause the surface potential to beequal to twice the Fermi potential in the bulk of semiconductor. Such adefinition, although widely used for modeling long-channel MOSFET’s,becomes increasingly questionable for modern devices with diminishingchannel lengths. In this paper a new approach is proposed which definesthe threshold voltage based on the intersection of the two asymptotes ofthe surface potential for the depletion and strong inversion regions. Theapproach is tested in simulation environment for MOS devices having dif-ferent channel lengths, oxide thicknesses, and substrate doping concentra-tions.

Index Terms—Author, please supply index terms. E-mail key-words@ieee.org for info.

I. INTRODUCTION

The threshold voltage,VT , is a very important device parameter forthe design, modeling, simulation and utilization of MOSFET’s [1]–[5].It is common in the literature to defineVT as the gate voltage at whichthe surface potential at the Si–SiO2 interface becomes twice the Fermipotential in the bulk of semiconductor [2]. Attempts have been madein the past to improve this definition [6], [7]. For example, a defini-tion was reported recently [7] to take into account the effects of de-pletion charges in the channel of the MOSFET. Such a definition im-proves the accuracy of theVT model for long-channel devices, but itsimprovement is less significant for MOSFETs with a channel length inthe sub-micron range.

A new approach for defining the threshold voltage, which is valid forboth long- and short-channel devices, is proposed here. It is based on

Manuscript received October 28, 1999; revised March 22, 2000. This workwas supported in part by Venezuela’s “Consejo Nacional de InvestigacionesCientíficas y Tecnológicas” through Grant S1-98000567. The review of thisbrief was arranged by Editor C. Y. Yang.

J. A. Salcedo, A. Ortiz-Conde, F. J. García Sánchez, and J. Muci are withthe Departamento de Electrónica, Universidad Simón Bolívar, Caracas 1080-A,Venezuela (e-mail: salcedoj@ieee.org).

J. J. Liou is with the Department of Electrical and Computer Engineering,University of Central Florida, Orlando, FL 32816-2450 USA (e-mail: liou@pe-gasus.cc.ucf.edu).

Y. Yue is with Technology Development, Intersil Corporation, Melbourne,FL 32902 USA (e-mail: yny@bluesboy.mlb.semi.harris.com).

Publisher Item Identifier S 0018-9383(01)02376-0.

concept that the threshold occurs at the intersection of the two asymp-totes of surface potential for the depletion and strong inversion regions.The validity of the approach is verified using results simulated fromMOS devices with various doping densities, channel lengths, and oxidethicknesses. The values ofVT predicted by this new approach are com-pared with those predicted by existing definitions and obtained fromtwo extraction methods which determineVT from the drain currentversus gate voltage characteristics [8]–[13]. Quantum-mechanical ef-fects, which may be important for deep-submicron MOSFETs, will notbe considered in the present study.

II. THRESHOLDVOLTAGE DEFINITIONS FORLONG CHANNEL DEVICES

For an n-channel MOSFET, the relationship between the surface po-tential and the gate voltage can be written as follows [2], [3]:

VGS � VFB = S �"sCo

F 2( S)1=2

(1)

where the minus sign is used when the bands bend up, the plus signis used when the bands bend down,VGS is the gate-to-source voltage, S is the surface potential,Co is the oxide capacitance,VFB is theflatband voltage, andF is the Kingston function [2]:

F 2( S) �2

�2L2D

� (e�� + � S � 1) +nopo

(e� � � S � 1) :

(2)

Here,� = q=kT is the inverse of the thermal voltage,po andno are theequilibrium hole and electron densities, andLD is the extrinsic Debyelength

LD ="sq�po

1=2

: (3)

In (2), the termsexp(�� S), (� S � 1), and(no=po) [exp(� S)�� S�1] are associated with the accumulation, depletion, and inversioncharges, respectively.

The conventional definition states that the threshold voltage is thegate voltage which produces a surface potential equal to twice theFermi potential,�B , in the bulk of semiconductor. According to thisdefinition, the surface potential at threshold, dubbed here the thresholdsurface potential, ST , can be expressed as

ST � 2�B �1

�ln

pono

�2

�ln

NAni

; (4)

whereni is the intrinsic free-carrier concentration andNA is the sub-strate doping density.

This conventional definition for the threshold surface potential canbe derived as follows. Using the condition that� S is much largerthan unity at the onset of strong inversion, the second term inside thebrackets in (2), which is associated with the inversion charge, can beapproximated by

nopo

(e� � � S � 1) �nopoe� = e�( �2� ): (5)

For the onset of strong inversion, this term must be larger than unity.Hence, equating this to unity, (5) becomes

e�( �2� ) = 1; (6)

0018–9383/01$10.00 © 2001 IEEE