NATIONAL POLYTECHNIC INSTITUTECOMPUTING RESEARCH CENTER

IPN-CIC MICROSE Lab

Design of a Multimedia Extension for RISC Processor

Eduardo Jonathan Martínez Montes

Prof. Marco Antonio Ramírez Salinas

I. Adder1. Full adder2. Ripple carry adder3. Carry look ahead adder4. Best adder5. Adder-Substracter

Saturated/Wrapped 8 bits6. Adder-Substracter

Saturated/Wrapped 16 bits

II. Multiplier1. Multiplier 8x82. Multiplier 16x16

OUTLINE

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III. Vector operations1. Over view

IV. Vector formats1. OB format2. OH format

V. Prototype1. Instruction path2. Prototype3. Results

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ADDER Full adder

A full adder is an arithmetic circuit that is used to add three bits.

Logic diagram Block diagram

Boolean functions

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Ripple Carry Adder (part 1)

The carry propagation time is the major speed limiting factor.

ADDER

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Ripple Carry Adder (part 2)ADDER

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Ripple Carry Adder (part 3)

Features

Resources: 35 LE Fmax: 208.90 MHzSize: 16 bits

ADDER

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Carry Look Ahead Adder (part 1)

It improves speed by reducing the amount of time required to determine carry bits.

ADDER

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Carry Look Ahead Adder (part 2)ADDER

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Carry Look Ahead Adder (part 3)

Features

Resources: 57 LE Fmax: 223.51 MHzSize: 16 bits

ADDER

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Kogge Stone Adder (part 1)

It is widely considered the fastest adder design possible.

ADDER

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Kogge Stone Adder (part 2)

Black Cell Gray Cell

ADDER

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Kogge Stone Adder (part 3)

Features

Resources: 82 LE Fmax: 255.17 MHzSize: 16 bits

ADDER

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Best adder

Ripple Carry Adder

Carry Look Ahead Adder

Kogge Stone Adder

0 50 100 150 200 250 300

Adders Comparison

Fmax Logic Elements Size

ADDER

IPN-CIC MICROSE Lab 14

Adder-Substracter Saturated/Wrapped 8 bits

FeaturesOperations: Adder, Substracter Arithmetic: Saturated, Wrapped Size: 8 bits Unsigned IntegerResources: 59 LE Fmax: 247.46 MHz

ADDER

IPN-CIC MICROSE Lab 15

Adder-Substracter Saturated/Wrapped 16 bits

FeaturesOperations: Adder, Substracter Arithmetic: Saturated, Wrapped Size: 16 bits Signed IntegerResources: 113 LE Fmax: 197.55 MHz

ADDER

IPN-CIC MICROSE Lab 16

Multiplier 8x8

FeaturesOperations: Multiplier Arithmetic: Saturated, Wrapped Size: 8x8=16 bits Unsigned IntegerResources: 308 LE Fmax: 287.85 MHz

MULTIPLIER

IPN-CIC MICROSE Lab 17

Multiplier 16x16

FeaturesOperations: Multiplier Arithmetic: Saturated, Wrapped Size: 16x16=32 bits Signed IntegerResources: 1,723 LE Fmax: 222.82 MHz

MULTIPLIER

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VECTOR OPERATIONS Over view

Single Instruction Multiple Data, this architecture performs the same operation on multiple data elements in parallel.

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Over view (cont.)VECTOR OPERATIONS

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OB format

Unsigned. 64 bits vector 8 elements each one 8 bits Accumulator contains 8 24 bits elements.

VECTOR FORMAT

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HB format

Signed. 64 bits vector 4 elements each one 16-bits Accumulator contains 4 48-bits elements.

VECTOR FORMAT

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Instruction pathPROTOTYPE

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Prototype

FeaturesResources: 8,449 LE Fmax: 176.27 MHzADD, ADDL, ADDA SUB, SUBL, SUBAMUL, MULL, MULA LDC2, SDC2No LPM

PROTOTYPE

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Results

ldc2 $v3, 0($0) # $v3 = $s0 let $s0=64'h0102030405060708sdc2 $v3, 0($s0) # $s0 = $v3

ldc2 $v4, 0($0) # $v3 = $s0 let $s0=64'h0A0B0C0D0E0FAABBsdc2 $v4, 0($s0) # $s0 = $v3

ldc2 $v5, 0($0) # $v3 = $s0 let $s0=64'hAABBCCDDEEFF1122sdc2 $v5, 0($s0) # $s0 = $v3

PROTOTYPE

IPN-CIC MICROSE Lab 25

ldc2 $v4, 0($0) # $v3 = $s0 let $s0=64'h0A0B0C0D0E0FAABBsdc2 $v4, 0($s0) # $s0 = $v3

ldc2 $v5, 0($0) # $v3 = $s0 let $s0=64'hAABBCCDDEEFF1122sdc2 $v5, 0($s0) # $s0 = $v3

add.ob $v6,$v4,$v5 #$v6 = $v4+$v5

$V4 = 0A 0B 0C 0D 0E 0F AA BB+ $V5 = AA BB CC DD EE FF 11 22

----------------------------------------- $V6 = B4 C6 D8 EA FC FF BB DD

Saturated

PROTOTYPE Results (cont.)

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ldc2 $v4, 0($0) # $v3 = $s0 let $s0=64'h0A0B0C0D0E0FAABBsdc2 $v4, 0($s0) # $s0 = $v3

ldc2 $v5, 0($0) # $v3 = $s0 let $s0=64'hAABBCCDDEEFF1122sdc2 $v5, 0($s0) # $s0 = $v3

add.ob $v7,$v4,$v5(0) #$v7 = $v4+$v5(0)

$V4 = 0A 0B 0C 0D 0E 0F AA BB+ $V5(0) = 22 22 22 22 22 22 22 22

---------------------------------------------- $V7 = 2C 2D 2E 2F 30 31 CC DD

PROTOTYPE Results (cont.)

IPN-CIC MICROSE Lab 27

ldc2 $v4, 0($0) # $v3 = $s0 let $s0=64'h0A0B0C0D0E0FAABBsdc2 $v4, 0($s0) # $s0 = $v3

add.ob $v8,$v4,10 #$v8 = $v4+1010101010101010

$V4 = 0A 0B 0C 0D 0E 0F AA BB+ 0A 0A 0A 0A 0A 0A 0A 0A

---------------------------------------------- $V8 = 14 15 16 17 18 19 B4 C5

PROTOTYPE Results (cont.)

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ldc2 $v2, 0($0) # $v3 = $s0 let $s0=64'h0908070605040302sdc2 $v2, 0($s0) # $s0 = $v2

ldc2 $v3, 0($0) # $v3 = $s0 let $s0=64'h0102030405060708sdc2 $v3, 0($s0) # $s0 = $v3

mul.ob $v9,$v2,$v3 #$v9 = $v2*$v3

$V2 = 09 08 07 06 05 04 03 02X $V3 = 01 02 03 04 05 06 07 08

---------------------------------------------- $V9 = 09 10 15 18 19 18 15 10

PROTOTYPE Results (cont.)

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Q&A