NATIONAL POLYTECHNIC INSTITUTE COMPUTING RESEARCH CENTER

NATIONAL POLYTECHNIC INSTITUTECOMPUTING RESEARCH CENTER

IPN-CIC MICROSE Lab

Design and implementation of a Multimedia Extension for a RISC Processor

Eduardo Jonathan Martínez Montes

Prof. Marco Antonio Ramírez Salinas

I. Background1. Motivation2. Multimedia applications3. State of the art

II. Problem Description1. Overview2. SISD3. SIMD4. SISD vs SIMD5. Saturation arithmetic6. Example7. Instruction format

III. Objective1. Main objective2. Specific objectives

OUTLINE

IPN-CIC MICROSE Lab 2

IV. Hypothesis1. Multimedia support

• MDMX• Vector to vector arithmetic

V. Technical Merits1. Data path2. Vector units


BACKGROUND Motivation

Lagarto is a superscalar embedded processor, now in develop by the HPC research team of CIC-IPN.

The goal of this effort is to be used to help in the research and teaching.

This processor require the design and build many blocks, so that, this project is part of a bigger project.


BACKGROUND Motivation (cont.)


BACKGROUND Motivation (cont.)


BACKGROUND Multimedia applications

Photo edition

Video edition

Rendering

Video games


State of the art

1996 1998 2000 2002 2004 2006 2008 2010 2012

AVX2 - Intel2013

Sandy Bridge y Bulldozer - Intel y

AMD2011

Advanced Vector Extensions (AVX) -

Intel

2008

SSE4 - Intel2006

SSE y SSE2 - AMD2004

SSE3 - Intel2004

Advance 3DNow! (3DNow! 2) - AMD

2003

AltiVec - IBM2002

SSE2 - Intel2002

3DNow!. - AMD2000

Streaming SIMD Extensions (SSE)-

Intel

1999

Pentium II (MMX)- Intel1998

AltiVec - Motorola1997

1996

1996

BACKGROUND


PROBLEM DESCRIPTION Overview

Multimedia Extension is a vector machine that is embedded in situ with the main Superscalar Processor, it is used for deal with multimedia applications.

Lagarto processor

Main processor

Multimediaextension


PROBLEM DESCRIPTION SISD

Single Instruction Single Data is a term referring to a computer architecture In which a single processor executes a single instruction stream.


PROBLEM DESCRIPTION SIMD

Single Instruction Multiple Data is a class of parallel computer. It describes computers with multiple processing elements that perform the same operation on multiple data points simultaneously.These machines exploit data level parallelism.


SISD vs SIMDPROBLEM DESCRIPTION


Saturation arithmeticPROBLEM DESCRIPTION

It is a version of arithmetic in which all operations such as addition and multiplication are limited to a fixed range between a minimum and a maximum value.

If the result of an operation is greater than the maximum, it is set to the maximum. On the other hand, if it is below the minimum, it is clamped to the minimum value.

50+80=130150 + 170 = 255120-135=0


Example

Example: get negative image

PROBLEM DESCRIPTION


SISD Processing

Example (cont.)PROBLEM DESCRIPTION


SIMD Processing

Example (cont.)PROBLEM DESCRIPTION


Instruction format

Opcode fmt/sel vt vs vd function31:26 25:21 20:16 15:11 10:6 5:0

HYPOTESIS

Co-processor instructionCOP1=010001COP2=010010


Instruction format (cont.)


HYPOTESIS

Data format and item chooser



HYPOTESIS

Source 2

Source 1

Destination

Instruction format (cont.)



HYPOTESIS Instruction format (cont.)


OBJECTIVE Objectives

General Objective

Design a multimedia extension unit for a RISC processor (Lagarto).

Specific Objectives

Design a vector adder w/wo saturation arithmetic. Design a multiplier w/wo saturation arithmetic. Implement the complete Instruction set of the MIPS Digital

Media extension (MDMX).


HYPOTESIS MIPS Digital Media Extension

Lagarto II processor with:

MDMX supports video, audio, and graphics pixel processing.• MDMX is not part of the MIPS Instruction Set.• A processor that implements the MDMX must

implement the MIPS-V ISA MIPS MDMX is not intended for general purpose

computing.• Software support is via shared libraries and

assembly language only.


MDMX shares a register file with the Floating Point Unit.• Data is moved between the shared register file

and memory with existing Floating Point Load and Store double operations.

Registers are interpreted in two formats: Quad Half and Oct Byte format.

MDMX also shared the 8 Floating Point Condition Code bites.

MDMX has a private 192 bit accumulator register.

HYPOTESIS MIPS Digital Media Extensión (cont.)


Vector to vector arithmeticHYPOTESIS


Data pathTECHNICAL MERITS


TECHNICAL MERITS Vector units

Vector adder w/wo saturation arithmetic. Vector subs tractor w/wo out saturation arithmetic. Vector multiplier w/wo out saturation arithmetic. Instruction vector Queue. Vector Load/Store Queue.


Q&A

Documents

NATIONAL POLYTECHNIC INSTITUTE COMPUTING RESEARCH CENTER