Multilevel Approach to the Reliability-Aware Design of Analog and Digital Integrated Circuits

(MARAGDA)

TEC2013-45638-C3-R

Kick off meeting

Bellaterra, 24 October 2014

Objectives

1.Statistical characterization and modeling of variability and aging in advanced CMOS devices 2 Unfolding of an efficient reliability-aware circuit simulation methodology 3. Diagnosis of circuit performance degradation due to variability and aging

4.Introduction of new design methodologies aimed at high-performance, low-power, (time-dependent) variability-resilient circuits

5 Development of reliability-aware reactive design strategies 6 Exploration of new circuit and system architectures for resistive switching technologies

Work Packages

Tasks and sub-objectives relations

Deliverables & Milestones

Cronogram

1.Statistical characterization and modeling of variability and aging in advanced CMOS devices

1.1 Nanoscale analysis of the time-zero variability sources and aging mechanisms. UAB. 1.2 Characterization of the time-dependent variability in advanced devices. UAB. 1.3 Statistical evaluation of device performances and aging. UAB (RP), UPC, IMSE-US. 1.4 Characterization and modeling of variability in emerging devices. UAB (RP), UPC. 6 Exploration of new circuit and system architectures for resistive switching technologies

6.1 Fault tolerant strategies for emerging resistive switching technologies, memories and computing architectures. UPC (RP), UAB. 6.2 Duty-aware adaptive mechanisms and new architectures evaluation. UPC (RP), UAB.      

WP1

Adressed objectives

WP1 1st year

D111 Statistical information on the electrical properties of as-grown planar devices at the nanoscale.

D112 Statistical information on the spatial distribution and dependence on operation conditions (V, T) of the BTI, CHC aging and TDDB of planar devices at the nanoscale. D131 Device array structure (UAB, UPC, IMSE-US)

D152 Laws for the operation dependence of relevant design-parameters of RS devices. (UAB-UPC)

D153 First run of RS devices. Some RS devices already available

D161 GSL /high-k structures. GFETs. GSL/high-k structures already available

M1. First version of the circuit reliability simulation tool. Includes improved SPICE models for BTI and TDDB in planar MOSFETs and RS devices description.

1st IC

UAB, UPC

UAB

2 Unfolding of an efficient reliability-aware circuit simulation methodology

2.1 Compact modeling of device time-dependent variability. UAB (RP), IMSE-US. 2.2 Implementation of an efficient reliability simulation tool. UAB, IMSE-US (RP).

3. Diagnosis of circuit performance degradation due to variability and aging

3.1 Experimental analysis of the device time-dependent variability in a circuital environment. UAB, UPC (RP), IMSE-US. 3.2 Simulation of the effects of device aging on relevant circuit building blocks for digital, analog and mixed-signal applications. UAB, UPC, IMSE-US (RP). 3.3 Assessment of device TDV under RF operation. UAB, UPC (RP), IMSE-US.

WP2

Adressed objectives

WP2 1st year

M1. First version of the circuit reliability simulation tool. Includes improved SPICE models for BTI and TDDB in planar MOSFETs and RS devices description.

D211 Improved SPICE statistical description of the BTI and TDDB effects in planar MOSFETs(IMSE-US, UAB).

D221 Reliability simulation tool v1. (IMSE-US-UAB)

Something already done:

UAB, UPC, IMSE-US

UAB, UPC, IMSE-US

Simulation of RTN in SRAMs (T2.3)

Optimization of simulation engine + BTI model implementation (T2.1 + T2.2)

RF circuits !!

WP3 Adressed objectives4.Introduction of new design methodologies aimed at high-performance, low-power, (time-dependent) variability-resilient circuits

4.1 Performance model generation techniques spanning from devices (RF passives) to circuits and systems. IMSE-US. 4.2 Strategies to integrate TZV and TDV simulation into synthesis techniques. IMSE-US (RP), UAB, UPC. 4.3 Strategies to include degradation phenomena (layout effects, TZV, TDV) and SEU effects into performance models. IMSE-US (RP), UAB, UPC. 4.4 Composition techniques of performance models. IMSE-US. 4.5 Development of new design flows based on (hybrid) top-down and bottom-up techniques aimed at high-performance and efficient TZV- and TDV-resilient IC design. IMSE-US. 5 Development of reliability-aware reactive design strategies

5.1 Built-in circuit monitoring of circuit performances to deal with TZV and TDV. UPC. 5.2 Characterization of circuit reconfiguration ability to compensate TZV and TDV. IMSE-US (RP), UPC. 5.3 Development of design strategies and design of state-of-the-art AMS/RF integrated circuits in nanometric technologies robust to TZV and TDV. IMSE-US (RP), UPC. 5.4 Development of adaptation and reconfiguration techniques to deal with TZV and TDV in digital circuits. UPC.      

WP3 1st year

M2. Experimental demonstration of new adaptive mechanism in high performance digital systems on prototypes.

D311 Software prototype for efficient front generation. D312 Software prototype for unconventional fronts. D313 Conditions to guarantee correct front transformation. D314 Unconventional (L-Q-area) front of inductors in Si and LTCC technology. D315 Demonstration of transformation

D321 Criteria for evaluation of quality of layout instancesD322 Layout-aware performance models. D361 Conditions for performance model composition. D362 Demonstration of model composition

UPC

IMSE-USIMSE-US, UAB

IMSE-US

WP4

Adressed objectives

5 Development of reliability-aware reactive design strategies

5.1 Built-in circuit monitoring of circuit performances to deal with TZV and TDV. UPC. 5.2 Characterization of circuit reconfiguration ability to compensate TZV and TDV. IMSE-US (RP), UPC. 5.3 Development of design strategies and design of state-of-the-art AMS/RF integrated circuits in nanometric technologies robust to TZV and TDV. IMSE-US (RP), UPC. 5.4 Development of adaptation and reconfiguration techniques to deal with TZV and TDV in digital circuits. UPC.

6 Exploration of new circuit and system architectures for resistive switching technologies

6.1 Fault tolerant strategies for emerging resistive switching technologies, memories and computing architectures. UPC (RP), UAB. 6.2 Duty-aware adaptive mechanisms and new architectures evaluation. UPC (RP), UAB.

WP4 1st year

M2. Experimental demonstration of new adaptive mechanism in high performance digital systems on prototypes.

D411 Analysis of observable figures of merit. D431 Experimental evaluation with 65nm chip of Adaptive Clock mitigation techniqueD371 Synthesis tool v1. D152 Laws for the operation dependence of relevant design-parameters of RS devices. (UPC, UAB)

2nd IC

UPC, IMSE-US

UPC, UAB

Samples

MOSFETs

RS devicesCapacitors from IMB-CNM

MOSFETs from IMEC

FinFETs Requested to IMEC

Simple digital circuits, from IMEC

Graphene devices GSL/high-k structures from IMB-CNM

from IMEC (different technological options)

Circuits

Possibility of irradiation (U. Padova, Argentina)

Others

MARAGDA webpage ??

Logo ??

Next general meeting

Others

DATE Workshop ?? Deadline Monday 17th November 2014 VARI a DATE