M.tech Theis - - VLSI Architecture for Discrete Fractional Fourier Transform

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Text of M.tech Theis - - VLSI Architecture for Discrete Fractional Fourier Transform

VLSI ARCHITECTURE FOR DISCRETE FRACTIONAL FOURIER TRANSFORM A THESIS SUBMITTED IN PARTIAL FULFILMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF TECHNOLOGY IN INFORMATION TECHNOLOGY (MICRO ELECTRONICS) INDIAN INSTITUTE OF INFORMATION TECHNOLOGY, ALLAHABAD, U.P. 211012, INDIA JUNE, 2010Submitted By V. Naga Vara Prasad M. M. Tech. IT (MI) IIIT-Allahabad IMI2008007 Under the Supervision of Dr. K. C. Ray IIIT-Allahabad INDIAN INSTITUTE OF INFORMATION TECHNOLOGY ALLAHABAD (Deemed University) (A Centre of Excellence in Information Technology, Established by Govt. of India) Date: ______________ WE DO HEREBY RECOMMEND THAT THE THESIS WORK PREPARED UNDER OUR SUPERVISION BY V. NAGA VARA PRASAD M. ENTITLED VLSI ARCHITECTURE FOR DISCRETE FRACTIONAL FOURIER TRANSFORM BE ACCEPTED IN PARTIAL FULFILMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF TECHNOLOGY IN INFORMATION TECHNOLOGY (MICRO ELECTRONICS) FOR EXAMINATION. COUNTERSIGNED Prof. S. Sanyal, DEAN (ACADEMICS) Dr. K. C. Ray THESIS ADVISOR INDIAN INSTITUTE OF INFORMATION TECHNOLOGY ALLAHABAD (Deemed University) (A Centre of Excellence in Information Technology, Established by Govt. of India) CERTIFICATE OF APPROVAL* The foregoing thesis is hereby approved as a creditable study in the area of information technology carried out and presented in a manner satisfactory to warrant its acceptance as a pre-requisite to the degree for which it has been submitted. It is understood that by this approval the undersigned do not necessarily endorse or approve any statement made, opinion expressed or conclusion drawn therein but approve the thesis only for the purpose for which it is submitted. COMMITTEE ON FINAL EXAMINATION FOR EVALUATION OF THE THESIS * Only in case the recommendation is concurred in CANDIDATE DECLARATION This is to certify that Report entitled VLSI Architecture for Discrete Fractional Fourier Transform which is submitted by me in partial fulfillment of the requirement for the completion of M.Tech. In Information Technology (specialization in Microelectronics) to Indian Institute of Information Technology, Allahabad comprises only my original work and due acknowledgements has been made in the text to all other materials used. Date: V. Naga Vara Prasad M. M.Tech. IT: Microelectronics Enrollment No: IMI2008007 VLSI Architecture for Discrete Fractional Fourier Transform Indian Institute of Information Technology, Allahabad v|P a g e Abstract The conventional Fourier transform is recognized as a significant tool in wide areas of signal, image processing and communication. Its discrete version turned as an essential module in many applications with the advent of its hundreds of fast computation algorithms and DSP processors. This thesis has been adding an additional value to this integral transform with a novel architecture of its generalized form. This generalized Fourier transform attracted the attention of signal, image and optical processing communities. Researchers identified its benefits by finding wide range of applications such as orthogonal frequency division multiplexing, optimum filters, Image registration, Image encryption, Image water marking, modulation and demodulation, human emotion detection, Optimal receivers, biomedical signal detection etc. This thesis enables the real time implementation of their proposals for different applications. Unlike the ordinary Fourier transform, the fractional Fourier transform have multiple definitions. Among these definitions, many researches are recommended a definition which is defined based on Eigen Vector Decomposition (EVD) as a legitimate definition. With the study of its properties using MATLAB simulations, we ensured the usability of this definition based on EVD. In this thesis, we proposed architecture for discrete fractional Fourier transform, which consumes hardware complexity of O(4N). Where N is transform order. This proposed architecture has been simulated and synthesized using verilogHDL, targeting a FPGA device (XLV5LX110T). Hardware simulations are compared with the MATLAB simulations which show that the results are very close with some quantization error. The synthesized results have been represented in terms of hardware utilization and timing, which shows that the proposed architecture can be operated at maximum frequency of 217MHz. The proposed architecture is also compared with the existing architecture which shows that the proposed architecture in this thesis is better in terms of timing and area complexity. VLSI Architecture for Discrete Fractional Fourier Transform Indian Institute of Information Technology, Allahabad vi|P a g e Acknowledgement I would like to express my deep gratitude to Dr. K. C. Ray for the numerous inspiring discussions and constant support throughout this study. I am highly thankful to him that in spite of his demanding professional preoccupation he always made himself available for guidance to me in my thesis work. I am very thankful to Prof. M. Radhakrishna, H.O.D, Department of Microelectronics, IIIT-A. For his vision, motivation and whole-hearted support throughout my academics. I am deeply indebted to Prof. B.R Signh and Mr. Manish goswami for their feedback and valuable comments during our regular presentations which helped me a lot in this thesis work. VLSI Architecture for Discrete Fractional Fourier Transform Indian Institute of Information Technology, Allahabad vii|P a g e Contents Certificate of Approval Candidate Declaration Abstract Acknowledgement Table of Contents Chapter 1 Introduction.... 01 1.1 Motivation .. 01 1.2 Objective . 02 1.3 Literature Survey 03 1.4 Contribution to this Thesis... 05 1.5 Thesis outline. 05 Chapter 2 Mathematical background 07 2.1 Continuous fractional Fourier Transform 07 2.1.1 Linear Integral transform.. 08 2.1.2 Fractional Powers of Fourier Transform...... 10 2.1.3 Rotation in Time-Frequency Plane.. 12 VLSI Architecture for Discrete Fractional Fourier Transform Indian Institute of Information Technology, Allahabad viii|P a g e 2.2 Discrete Fractional Fourier Transform.... 12 2.2.1 Direct form DFrFT. 13 2.2.2 Improved sampling Type DFrFT. 13 2.2.3 Linear Combination Type DFrFT 13 2.2.4 Eigen vector Decomposition Type DFrFT 14 2.3 Illustration of Fractional Fourier Transform Properties using MATLAB Simulations... 17 2.4 CORDIC.. 22 Chapter 3 DFrFT using Discrete Hermite-Gaussian Functions. 25 Chapter 4 VLSI Architecture for Discrete Fractional Fourier Transform... 29 4.1 Architecture of discrete fractional Fourier Transform Level-I.............................................................................. 30 4.2 Architecture of discrete fractional Fourier Transform Level-II............................................................................ 35 4.3 Architecture of discrete fractional Fourier Transform Level-III........................................................................... 37 Chapter 5 Results and Discussion.................................................. 39 Chapter 6 Conclusion and future work. 56 References................................................................... 57 Appendix A Xilinx-ISE Simulation Results of Proposed DFrFT Architecture.................................................................... 61 Publications.... 67 VLSI Architecture for Discrete Fractional Fourier Transform Indian Institute of Information Technology, Allahabad ix|P a g e List of Figures Fig.1.1 Block diagram of Discrete Fractional Fourier Transform 02 Fig.2.1 Illustration of linearity Property using MATLAB Simulations for f1 (x) = sin(*x), f2 (x) = cos(*x).. 17 Fig.2.2 Illustration of Inverse Property using MATLAB simulations for sinusoidal signal... 18 Fig.2.3 Illustration of Index additive Property using MATLAB Simulations for sinusoidal signal.. 18 Fig.2.4 Illustration of Index and Integer Properties using MATLAB Simulations for sinusoidal signal.. 19 Fig.2.5 Illustration of Commutative Property using MATLAB Simulations for sinusoidal signal.. 20 Fig.2.6 Illustration of Associative Property using MATLAB Simulations for sinusoidal signal.. 21 Fig. 2.7 Graphical representation of CORDIC (a) Circular CORDIC (b) Linear CORDIC 23 Fig. 2.8 Normalized angle representation for CORDIC.... 24 Fig. 4.1 Block diagram of the DFrFT 29 Fig. 4.2a Calculation of Eigen values.. 31 VLSI Architecture for Discrete Fractional Fourier Transform Indian Institute of Information Technology, Allahabad x|P a g e Fig. 4.2b Architecture of Pipelined CORDIC 31 Fig. 4.2c Architecture of single stage pipelined CORDIC 32 Fig. 4.3 The Data flow for part II of level-I... 33 Fig. 4.4 Data flow Diagram of DFRFT.. 35 Fig. 4.5 Complex Multiplier with shifting operation. 36 Fig. 4.6 Signal Flow graph for level-III. 37 Fig. 5.1 Interpretation of fractional Fourier Transform in Time Frequency Representation............. 40 Fig. 5.2 Input Samples for MATLAB Simulation of DFrFT. 41 Fig. 5.3 MATLAB Simulation Result of DFrFT for =00. 41 Fig. 5.4 MATLAB Simulation Result of DFrFT for =300... 42 Fig. 5.5 MATLAB Simulation Result of DFrFT for =600... 42 Fig. 5.6 MATLAB Simulation Result of DFrFT for =900... 42 Fig