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StarCore DSP Evaluation Module
MSC711xEVMUG
Revision 0, April 2005
MSC711XEVM User’s Guide
Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.
Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part.
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. StarCore is a trademark of StarCore LLC. All other product or service names are the property of their respective owners.
© Freescale Semiconductor, Inc. 2004.
MSC711xEVMUGRev 04/2005
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5
A
MSC711xEVM Overview
Board Configuration and Installation
EVM Functional Description
EVM Memory Maps and Bus Mapping
EVM Schematics
3EVM Power and Connectors
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2
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5
A
MSC711xEVM Overview
Board Configuration and Installation
EVM Functional Description
EVM Memory Maps and Bus Mapping
EVM Schematics
3 EVM Power and Connectors
Contents
About This Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ixBefore Using This Manual—Important Note . . . . . . . . . . . . . . . . . . . . . . . . . . ixAudience and Helpful Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ixNotational Conventions and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ixOrganization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xRelated MSC711xEVM Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiAbbreviations and Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
1 MSC711xEVM Overview1.1 MSC711xEVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11.2 Board Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11.3 MSC711xEVM Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
2 Board Configuration and Installation2.1 Hardware Unpacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12.2 Hardware Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12.2.1 Board Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22.2.2 I2C EEPROM Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22.2.3 Switches and DIP Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32.2.4 EVM Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42.2.4.1 JP1-Host Terminal Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42.2.4.2 JP2-Not Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42.2.4.3 JP3-Ethernet PHY Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52.2.5 EVM Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52.2.5.1 TP1 - TP20 Signal Measurment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52.2.5.2 TP21-TP27 Voltage Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52.2.5.3 JS1-JS3 GND Bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62.2.6 EVM LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
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3 EVM Power and Connectors3.1 Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13.1.1 Required MSC711xEVM Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23.1.3 Power Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33.1.3.1 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33.1.3.2 Power Sequence Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33.1.4 EVM Power Connection Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33.2 EVM Interconnect Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43.2.1 Main Communication Port (P1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-53.2.2 RJ45 Ethernet Line Connector (P2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-53.2.3 In System Programming (ISP) Connector (P3). . . . . . . . . . . . . . . . . . . . . . . . . 3-63.2.4 Slave UART Port Connector (P4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73.2.5 SMD Header P5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83.2.6 Power-On Configuration Header (P6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-103.2.7 Stereo Phone Jack Connectors (P7, P8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-103.2.8 Host Debug OCE10 (SYS) Connector (P9) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-113.2.9 Host Interface (HDI) Connector (P10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
4 EVM Functional Description4.1 MSC711xEVM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14.2 Reset and Reset-Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24.2.1 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24.2.2 Power-On Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34.2.3 Hard Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34.2.4 External Port Hard Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44.2.5 Manual Hard Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44.2.6 Internal Sources Hard Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44.3 EVM Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44.4 TDM Interface and Stereo Codec. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-64.5 I2C Boot EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-74.5.1 EVM EEPROM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-74.5.2 EVM EEPROM Summary Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-74.6 JTAG/OCE10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-94.6.1 JTAG TAP Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-94.6.2 JTAG/OCE10 Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-94.6.3 Parallel Port Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-104.6.4 JTAG Operational LED LD7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
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4.7 DDR SDRAM Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-114.7.1 SSTL_2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-114.7.2 SSTL_2 Signals and Line Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-114.7.3 MSC711x_EVM DDR Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-134.8 Fast Ethernet (10/100 Base-T) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-144.8.1 VT6103 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
5 EVM Memory Maps and Bus Mapping5.1 Memory Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15.2 Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15.2.1 Extended Core Memory 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15.2.2 Extended Core Registers (ICache Array) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25.2.3 On-Chip Memory Outside Platform (M2, Boot ROM). . . . . . . . . . . . . . . . . . . 5-25.2.4 Extended Core Memory - 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25.2.5 Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35.2.6 Off-Chip Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35.3 Host Processor Interface (HDI16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35.3.1 HDI16 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45.3.1.1 Special MSC711x HDI16 Port Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45.3.1.2 HDI16 Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
A MSC711xEVM SchematicsA.1 MSC711xEVM Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1A.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2A.1.2 StarLite DDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3A.1.3 StarLite HDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4A.1.4 StarLite System and PIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5A.1.5 StarLite Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6A.1.6 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7A.1.7 CODEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8A.1.8 JTAG_Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9A.1.9 Parallel Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10A.1.10 Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11
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About This Book
This user’s guide describes engineering specifications for the MSC711x evaluation module (EVM) board. This EVM board targets any of the StarLite MSC711x family of DSP processors. Each of these is a highly integrated system-on-a-chip device containing a StarCoreTM SC1400 digital signal processing (DSP) cores.
The MSC711xEVM board is intended to serve as a platform for evaluating software developed for the StarLite processor environment. This manual lists and explains various features of the MSC711xEVM and describes how the board must be configured to test developed code for each processor.
Before Using This Manual—Important Note
The information in this manual is subject to change without notice, as described in the disclaimers on the title page of this manual. Before using this manual, determine whether it is the latest revision and whether there are errata or addenda. To locate any published errata or updates associated with this manual or this product, refer to the world-wide web site listed on the back cover of this manual or call your local distributor or sales representative.
Audience and Helpful Hints
This manual is for software developers and applications programmers who are developing products using the StarLite MSC711x device.
Notational Conventions and Definitions
This manual uses the following notational conventions:
mnemonics Instruction mnemonics appear in lowercase bold.
italics Book titles in text are set in italics. In addition, italics are used for emphasis and to highlight the main items in bulleted lists. Variables and equations are also italicized.
0x Prefix to denote a hexadecimal number.
0b Prefix to denote a binary number.
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Organization
Following is a summary and a brief description of the chapters of this manual:
Chapter 1, MSC711xEVM Overview. Descriptive overview of main board specifications and MSC711xEVM features.
Chapter 2, Board Configuration and Installation. Lists and explains necessary dipswitch and jumper configurations, test points and functional LEDs.
Chapter 3, EVM Power and Connectors. Describes board power connector and supplies. Describes all board peripheral connectors.
Chapter 4, EVM Functional Description. Describes the functionality of different segments of the board block diagram, such as I2C, EEPROM, and Fast Ethernet.
Chapter 5, EVM Memory Maps and Bus Mapping. Describes the MSC711x memory map and the memory mapping for the HDI16 bus.
Appendix A, MSC711xEVM Schematics. Contains the schematics for the MSC711xEVM.
REG[FIELD] Abbreviations or acronyms for registers appear in uppercase text. Following the register name, the bit or field name is enclosed in brackets. For example, ICR[8]:INIT refers to the Force Initialization bit (bit 8) in the host Interface Control Register.
Active high signals
Names of active high signals appear in small caps, sans serif, as follows: SIO1D[0–63], SIO1R, and GNDPA.
Active lowsignals
Signal names of active low signals appear in small capital letters in a sans serif typeface, with an overbar: SIOP1CS, SIOP1WE[0–1], and SIOP1HT0.
x A lowercase italicized x in a register or signal name indicates that there are multiple registers or signals with this name. For example, SIOxA refers to the SIO0A and SIO1A signals. MxCBCR refers to the M0CBCR and M1CBCR registers.
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Related MSC711xEVM DocumentationMSC711x Reference Manual
MSC7110 Technical Data Sheet
MSC7112 Technical Data Sheet
MSC7113 Technical Data Sheet
MSC7116 Technical Data Sheet
MSC7118 Technical Data Sheet
MSC7119 Technical Data Sheet
OCE10 On-Chip Emulator Reference Manual
AKM AK4550 Codec Data Sheet.
AKM AK4554 Codec Data Sheet.
SWITI Switching Device PEF24471 HTSI-XL Wired Communication Data sheet
VIA Technologies VT6103 Ethernet PHY Data Sheet.
Abbreviations and Acronyms
List of abbreviations and acronyms:
ALU - Arithmetic Logic Unit
BCSR - Board Control and Status Register
COP - Common On-chip Processor
CPM - Communication Processor Module
CW - Metrowerks CodeWarrior IDE for StarCore
DIP - Dual-In-Line Package
DMA - Direct Memory Access
DSI - Direct Slave Interface
DSP - Digital Signal Processor
EOnCE - MSC711x on-chip emulation is now actualized by OCE10.
EVM - Evaluation Module
GPCM - Memory Controller General Purpose Chip-select Machine
GPL - General Purpose Line (associated with a UPM)
HCW - Hardware Configuration Word
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HDI16 - Host Debug Interface 16 bit-wide
LSB - Least Significant Byte
lsb - least significant bit
Mbyte - Megabyte (1048576 bytes)
MII - Media Independent Interface
OCE10 - On-chip emulator. Provides a standard means of connecting a host computer running a debugger to a target system-on-chip.
PHY - Physical Layer
RMII - Reduced Media Independent Interface
SC711x - MSC711x family of devices.
SDRAM - Synchronous Dynamic Random Access Memory
SDRAM Machine - Memory Controller Synchronous Dynamic RAM Machine
SIU - System Interface Unit
SMII - Serial Media Independent Interface
SoC - System-on-chip.
TBD - To Be Defined
TDM - Time Division Multiplex
UART - Universal Asynchronous Receiver Transmitter
UPM - User Programmable Machine
UPM Machine - (Memory Controller) User Programmable Machine
ZD - Clock Zero Delay Buffer with internal PLL for skew elimination
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MSC711xEVM Overview 1This document is an operation guide for the MSC711x EVM board. It contains operational, functional and general information about the MSC711x evaluation module (EVM). This board is meant to serve as a platform for software and hardware development for the StarLite (MSC711x) family of processors. Each MSC711x chip is a highly integrated system-on-a-chip device containing a StarCore SC140 digital signal processor (DSP) core.
1.1 MSC711xEVM
This manual describes engineering specifications for the MSC711xEVM. Using its on-board resources and a debugger, a developer is able to download code, run it, set breakpoints, display memory and registers and connect proprietary hardware via the expansion connectors, to be incorporated into a desired system with the MSC711x processor.
The MSC711xEVM board is intended to serve as a platform for software development for the MSC711x processor environment. On-board resources and associated debugger enable developers to perform a variety of tasks:
• Download and run code,
• Set breakpoints,
• Display memory and registers,
• Connect proprietary hardware via the expansion connectors.
The MSC711x processor enables incorporation of these features into selected systems.
1.2 Board Specifications
Specifications for the MSC711xEVM board are provided in Table 1-1.
Table 1-1. MSC711xEVM Specifications
Characteristics Specifications
Power requirements. +5vdc @ 2A (Max.)
Microprocessor MSC711x @ 100MHz bus, 200 MHz CPU
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MSC711xEVM Overview
1.3 MSC711xEVM Features
The MSC711xEVM features are as follows:
• MSC711x as main DSP master.
• 32 Mbyte DDR SDRAM connected to the MSC711x - 32 bits wide.
• One 10/100 Base-T Ethernet port (MII) using VIA VT6103 connected to the MSC711x.
• One UART port connected to the MSC711x.
• 256Kbyte I2C EEPROM connected to the MSC711x.
• OCE10/JTAG connector for the MSC711x.
• One UART port connected to the Host.
• HDI16 host available thru Header.
• COP/JTAG connector for the MPC711x.
• On-board parallel to JTAG Command Converter - connected to the MPC711x.
• Single +5V Power Supply.
• Power on indication LEDs for 5V, 3.3V, and 2.5V voltages.
• HRESET Push button for the MPC711x
MemoryDDR SDRAM (MSC711x) 32 Mbyte (32 bits wide)
Operating temperature. 0oC - 70oC
Relative humidity. 5% to 90% (non-condensing)
Dimensions: 100mm X 150mm
Table 1-1. MSC711xEVM Specifications (Continued)
Characteristics Specifications
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Board Configuration and Installation 2This chapter contains unpacking instructions, hardware preparation, configuration and installation information for the MSC711xEVM board. The user can check the configuration of the EVM board against the factory settings shown in this manual to ensure proper board functionality.
Caution: Ensure that power is off or disconnected prior to reconfiguring an installed EVM board. Reconfiguring jumpers with the power on may damage system circuits.
2.1 Hardware Unpacking
The first step in preparing the hardware is to unpack the EVM board. When unpacking the MSC711xEVM board from its shipping carton refer to the packing list to verify that all items are present and in good condition.
Note: If the shipping carton is damaged upon receipt, request carrier's agent to be present during unpacking and inspection of equipment. Unpack equipment from shipping carton. Refer to packing list and verify that all items are present. Save packing material for storing and reshipping of equipment.
2.2 Hardware Preparation
EVM board parameters can be changed for the following conditions:
• Force PC connection (Laptop or Desktop) - via JP1.
• Main Power Supply On/Off Switch - via SW4.
• MSC711x Power-up configuration - via SW3.
• Selecting Switch Inputs (software options) - via SW1.
• Ethernet PHY isolate -via JP3.
MSC711xEVM Reference Manual, Rev. 0
Freescale Semiconductor 2-1
Board Configuration and Installation
2.2.1 Board Configuration
Caution: When configuring the board, avoid touching areas of integrated circuitry. Static discharge can damage circuits.
To select the desired configuration and ensure proper operation of the MSC711xEVM board, changes of the configuration jumper and DIP switch settings may be required before installation. The location of the EVM’s switches, indicators, DIP switches, configuration jumpers and connectors is shown inFigure 2-1 .
Figure 2-1. MSC711xEVM Top-side Part Location Diagram
The board has been factory tested and is shipped with DIP switch settings as described in the following paragraphs.
2.2.2 I2C EEPROM Configuration
The I2C EEPROM Configuration Bus ADDRESS is "000" - determined by pull down resistors. The Write Protection Mode for the EEPROM is disabled at the factory. However, "OPTION" pull up resistors are available on the EVM to change the default settings. You can enable Write Protection, and change the EEPROM address.
U3MSC711xEVM
P1
P2
P4 P7 P8
SW2
SW4
P11
JP1 JP2 JP3
Ethernet - TDM P5 P9
SW3
SW1
P3 P6 P10
LD1
LD2
LD3
3.3V 5V 2.5V
LED0 LED1 LED2 LED3
LD8 LD11 LD13
MSC711xEVM Reference Manual, Rev. 0
2-2 Freescale Semiconductor
Hardware Preparation
2.2.3 Switches and DIP Switches
EVM pushbuttons, switches and DIP subswitches are listed and described in Table 2-1. Switch locations are shown in Figure 2-1. The switches discussed in the table are shown with their factory default positions.
Table 2-1. EVM Switches
Designator and Purpose
Type Description
User ConfigurableDIP Switch
SW1
Starlite GPIO Inputs
Subwitches SW1-1 thru SW1-4 are inputs in the MSC711x. They are user configured by software as one of three signals at the pin.
SW1.1 - StarLite pin Y13 (T1RCK/IRQ0/GPIO).SW1.2 - StarLite pin V13 (T1RFS/IRQ1/GPIO).SW1.3 - StarLite pin W13 (T1RD/IRQ8/GPIO). SW1.4 - StarLite pin V13 (T1TCK/IRQ9/GPIO).
If the subswitch is in the “ON position, its related signal is at “0”. If the subswitch is in the “OFF” position, related signal is at “1”. Factory settings: All subswitches “ON”, signal at “0”.
PushbuttonSW2
MSC711x Hard Reset
HRESET
Press pushbutton SW2 for an MSC711x hard reset. The HRESET signal is de-bounced.
Power-up Configuration
DIP SwitchSW3
Subswitch SW3.1 is the Debug Request. When the subswitch is “ON”, the MSC711x is in Debug mode.
Subswitch SW3.2 disables the Software Watchdog Timer. This pin is sampled on the negation of PORESET.
Subswitch SW3.3 and SW3.4 define the Boot Mode of the MSC711x. Pins are sampled on the negation of PORESET.
If the subswitch is in the “ON position, its related signal is at “0”. If the subswitch is in the “OFF” position, related signal is at “1”. Factory settings: All subswitches “ON”, signal at “0”.
SW4
Main Power Switch
When the switch is “ON”, the EVM is powered from an external 12V power supply via the PX connector.
When the switch is “OFF” the external power supply is disconnected.
Toggling the switch turns the main power on and off.
ON
1
SW_IN1
SW_IN2
SW_IN3
23
4
SW_IN0
GPIO Inputs
ON
1
SWTE
BM1
23
4DBREQ
Power-up Settings
BM0
PCB
ON
OFF
Front panel
MSC711xEVM Reference Manual, Rev. 0
Freescale Semiconductor 2-3
Board Configuration and Installation
2.2.4 EVM Configuration Jumpers
The MSC711xEVM configuration jumpers and their settings are explained in the following sub-sections. Jumper locations are shown in Figure 2-1, MSC711xEVM Top-side Part Location Diagram, on page 2-2. The jumpers are shown with their factory default positions.
2.2.4.1 JP1-Host Terminal Connection
JP1 selects whether the host terminal connection to the MSC711xEVM is to be made for a Laptop or for a Desktop PC. Jumpering pins 1 and 2 forces a laptop connection to the EVM while a jumper on pins 2 and 3, or no jumper on JP1 at all, forces a desktop connection. The factory setting is pins 2 and 3 jumpered. The relative states of JP1 pins are illustrated below in .
Figure 2-2. JP1- Host Terminal Connection
When a jumper is present on pins 1 and 2 of JP1, this means there is a GND in JP1. This is a special mode for working with a laptop. When no jumper is present in JP1, or pins 2 and 3 are jumpered, the EVM is in Desktop mode (Default).
2.2.4.2 JP2-Not Used
The prototype boards still contain configuration jumper header JP2. This jumper will be removed in later versions and its setting has no effect on board operation.
Figure 2-3. JP2 - Not Used
1
OCE10 Header Parallel Port
Factory Setting
2 3 1 2 3
Parallel Port
1 2 3
(Laptop) (Desktop) (Desktop)
1
JP2 Open
2 1
JP3 Closed
2
MSC711xEVM Reference Manual, Rev. 0
2-4 Freescale Semiconductor
Hardware Preparation
2.2.4.3 JP3-Ethernet PHY Mode
Jumper JP3 to measure or set the MSC711x EE0 signal logic levels. If you wish to close JP3, place a jumper on pins 1 and 2, as shown below. The factory setting is “Open”.
Figure 2-4. JP3-Ethernet PHY Mode
2.2.5 EVM Testing
MSC711xEVM testing is detailed in the following sub-sections. The location of the various EVM test points and bridges is shown in Figure 2-1, MSC711xEVM Top-side Part Location Diagram, on page 2-2.
2.2.5.1 TP1 - TP20 Signal Measurment
TP1- TP20 allow testing for the I2C signals and the CPLD as shown in Table 2-2.
2.2.5.2 TP21-TP27 Voltage Measurement
EVM voltage test points reside, respectively, on the voltages shown in Table 2-3.
Table 2-2. Signal and CPLD Test Points
Test Point Connection
TP1 - TP13 Connected to the CPLD for R&D use only.
TP14 I2CSD - I2C Serial Data
TP15 I2CSCL - I2C Clock
TP16 - TP20 Connected to the CPLD for R&D use only.
Table 2-3. Voltage Test Points
Test Point Sampling Test Point Sampling
TP21 DDR VTT TP25 2.5V
TP22 DDR Vref TP26 5V
TP24 3.3V TP27 1.2V
1
Isolate Mode
JP3 Open
2 1
Ethernet PHY Enabled
JP3 Closed
2
Factory Setting
MSC711xEVM Reference Manual, Rev. 0
Freescale Semiconductor 2-5
Board Configuration and Installation
2.2.5.3 JS1-JS3 GND Bridges
The MSC711xEVM has three bridges designated as GND. The bridges assist in general measurements and act as logic analyzer connections.
Caution: Only use INSULATED GND clips when connecting to a GND bridge. Otherwise, permanent damage may occur to the MSC711xEVM. Non-insulated clips that come into contact with surrounding “HOT” points may cause short-circuits.
2.2.6 EVM LEDs
The MSC711xEVM operational LEDs are described in the following sub-sections. The LED locations are shown in Figure 2-1, MSC711xEVM Top-side Part Location Diagram, on page 2-2.
Table 2-4. ADS LEDs Functions
LED Function
LD1MSC711x Fast Ethernet Port Link
Indicator
Green LD1 lights when there is a physical link connection in the RJ45 connector P2.
LD2MSC711x Fast Ethernet Port
100Base-Tx Indicator
Green LD2 lights when the VT6103 on the MSC711x is enabled and is in 100 Mbps operation mode.
LD3MSC711x Fast Ethernet Port Full
Duplex Indicator
Red LD3 lights when the VT6103 on the MSC711x is enabled and is in Full Duplex operation mode.
LD4I2C EEPROM CLOCK:SCL
Red LD4 is connected to the Clock Line of the I2C BUS.
LD7External Debugger Connection
Indicator
When lit, green external debugger connection LD7 indicates that the parallel port cable is not attached to the EVM board. The user can connect to the board using third company external device via OCE10/JTAG connector P9. When the parallel cable is connected at P1, LD7 turns off and communication is made by an internal device.
LD83.3V Indicator
Green LD8, indicates the presence of the +3.3V supply on the board.
LD9I2C EEPROM DATA:SDA
Green LD9 is connected to the Data line of the I2C Bus.
LD115V Indicator
Green LD11, indicates the presence of the +5V supply on the board.
LD132.5V Indicator
Green LD13, indicates the presence of the +2.5V supply on the board.
LD14General Purpose LED 0 Indicator
General purpose red LD14 is user controlled by GPIO pin W14.
LD15General Purpose LED 1 Indicator
General purpose red LD15 is user controlled by GPIO pin V14.
MSC711xEVM Reference Manual, Rev. 0
2-6 Freescale Semiconductor
Hardware Preparation
LD16General Purpose LED 2 Indicator
General purpose red LD16 is user controlled by GPIO pin W12.
LD17General Purpose LED 3 Indicator
General purpose red LD17 is user controlled by GPIO pin W14.
Table 2-4. ADS LEDs Functions (Continued)
LED Function
MSC711xEVM Reference Manual, Rev. 0
Freescale Semiconductor 2-7
Board Configuration and Installation
MSC711xEVM Reference Manual, Rev. 0
2-8 Freescale Semiconductor
EVM Power and Connectors 3The location of the MSC711xEVM power, communication and expansion connectors is shown in Figure 3-1.
Figure 3-1. MSC711xEVM Connector Locations
3.1 Power
Power is supplied to the MSC711xEVM via EVM connector P11. P11 is a 2mm Power Jack RAPC722 providing connection to an external +5VDC @ 2A power supply.
U3MSC711xEVM
P1
P2
P4 P7 P8
SW2
SW4
P11
JP1 JP2 JP3
Ethernet - TDM P5 P9
SW3
SW1
P3 P6 P10
LD1
LD2
LD3
3.3V 5V 2.5V
LED0 LED1 LED2 LED3
LD8 LD11 LD13
MSC711xEVM Reference Manual, Rev. 0
Freescale Semiconductor 3-1
EVM Power and Connectors
3.1.1 Required MSC711xEVM Voltages
For normal operation, the MSC711xEVM requires the following voltages:
• 5V : (Main Power supply).
• 3.3V : (MSC711x I/O and for most of the components).
• 2.5V : (SSTL components: the DDR chip and the DDR interface in the MSC711x).
• VTT : (1.25V for DDR active termination).
• 1.2V : MSC711x core voltage.
The MSC711x chip evaluation maximum current demands are:
• 100mA for the I/O @ 3.3V.
• 240mA for the SSTL_IO +DDR @ 2.5V.
• 511mA for the core @ 1.2V.
3.1.2 Power Supply
The MSC711xEVM requires a power supply of +5V DC @ 2A max. To apply power directly to the EVM board, insert enclosed power supply plug into the board’s P11 power jack.
Figure 3-2. Power Supply Block Diagram.
The power supply is made up of five separate unrelated devices:
• The main 3.3V voltage produced from a LDO NATIONAL_LP3872_3V3, This module is capable of delivering 1.5A max current.
• The 2.5V is produced by an LDO device NATIONAL_LP3872_2V5 capable of handling 1.5A.
LDOe 3.3V
LDOe 2.5V
LDOe 1.2V
VTT and Vrefe 1.25V
PowerSequence
O O
O
O O
OO O
5VMain Power
3.3V
2.5V
1.2V
1.25VVTT
3.3V
2.5V
MSC711xEVM Reference Manual, Rev. 0
3-2 Freescale Semiconductor
Power
• The 1.2V is produced by a LDO device MIC29302BU from Micrel capable of handling 1.5A.
• The VTT / VREF is produced by a LDO device FAN1655MTF from Fairchild capable of handling 2.1A.
3.1.3 Power Sequence
The MSC711xEVM has 3 distinct power supplies: 1.2V core, 2.5V DDR I/O, 3.3V Standard I/O. It is extremely important to observe strict power-up sequence at the board level to avoid latch up forward biasing of ESD devices and excessive currents.
Caution: Improper power-up sequencing can lead to severe device damage.
From a time variant viewpoint, during power ramping up, at any instant, the 2.5V supply must maintain a differential of +0.7V or more below the 3.3V supply. Also, at any instant, the 1.2V supply must maintain a differential of +0.7V or more below the 2.5V supply. This restriction includes the power-up sequence.
3.1.3.1 Power-Up Sequence
The following must be the sequence for power-up:
1. Turn on highest supply first. (3.3V Standard I/O).
2. Turn on 2.5V DDR I/O supply.
3. Turn on last lowest supply 1.2V core.
3.1.3.2 Power Sequence Control Logic
The MSC711xEVM power sequence control logic circuit is a 3.3V monitor and an internal counter realized in the Altera CPLD device. These provide the necessary delays in power up sequence.
3.1.4 EVM Power Connection Procedure
Since the power sequencing is automatically provided by the CPLD device, to power-up the board, the user need only plug the external power into board connector P11, then toggle the power switch SW4. This powers the board up in the correct power up sequence.
MSC711xEVM Reference Manual, Rev. 0
Freescale Semiconductor 3-3
EVM Power and Connectors
3.2 EVM Interconnect Signals
The MSC711xEVM interconnects with external devices via the following connectors:
• P1 - 25 Pin D type female port, main communication port between the computer and the MSC711x in SPP mode.
• P2- RJ-45 100/10 Base-T Ethernet port
• P3 - In System Programming (ISP) for configuration of the CPLD
• P4 - D-type 9 Pin 900 female RS-232 port
• P5 - 36 Pin male header , connects to TDM and Ethernet signals.
• P6 - 10 Pin male header, connects to Power On configuration signals.
• P7 - Stereo Line In Phone Jack.
• P8 - Stereo Line OutPhone Jack.
• P9 - JTAG/OCE10
• P10 - HDI header
MSC711xEVM Reference Manual, Rev. 0
3-4 Freescale Semiconductor
EVM Interconnect Signals
3.2.1 Main Communication Port (P1)
EVM connector P1 is main communication port with the MSC711x. It is a 25 Pin female Dtype connector. Connector P1 signals are described in Table 3-1.
3.2.2 RJ45 Ethernet Line Connector (P2)
The Ethernet line connector (P2), a twisted-pair compatible connector, is implemented with a 90o, 8-pin, RJ45 connector. Connector P2 signals are described in Table 3-2.
Table 3-1. Connector P1 Signals
Pin Number EPP Function SPP Function
1 Write
2 DB0 RESET
3 DB1 TMS_IN
4 DB2 TCK_IN
5 DB3 TDI_IN
6 DB4 TRST_IN
7 DB5 DR_IN
8 DB6 IDENT
9 DB7
10 IRQ
11 Wait TD0_OUT
12 and 15 N.C.
13 Select 5V_OUT
14 Dstrobe
16 Reset
17 Astrobe
18 - 24 GND
25 IN
Table 3-2. P2: Ethernet Port Interconnect Signals
Pin No. Signal Name Description
1 TPTX(GRAY) Twisted-Pair Transmit Data positive output from the MSC711xEVM.
2 TPTX~(BROWN) Twisted-Pair Transmit Data negative output from the MSC711xEVM.
3 TPRX(YELLOW) Twisted-Pair Receive Data positive input to the MSC711xEVM.
4, 5 (RED,GREEN) Bob Smith terminated on the MSC711xEVM.
6 TPRX~(BLACK) Twisted-Pair Receive Data negative input to the MSC711xEVM.
7, 8 (BLUE,ORANGE) Bob Smith terminated on the MSC711xEVM.
MSC711xEVM Reference Manual, Rev. 0
Freescale Semiconductor 3-5
EVM Power and Connectors
3.2.3 In System Programming (ISP) Connector (P3)
Connector P3 is a 10-pin generic 0.050" pitch header connector providing in-system programming capability for the board CPLD device (for board programmable logic). P3 pinout is seen in Table 3-3.
Table 3-3. ISP Connector-Interconnect Signals
Pin No. Signal Name Attribute Description
1 TCK I ISP test port clock. This clock shifts in/out data to/from the programmable logic JTAG chain.
2 GND P Digital GND. Main GND plane.
3 TDO O ISP Transmit Data Output. Programmable logic of the JTAG serial data output driven by falling edge of TCK.????
4 VCC P Connect to 3.3V power supply bus for feeding an external programmer logic.
5 TMS I ISP Test Mode Select. This signal is qualified with TCK - changes the state of the programmable logic JTAG machine.
6 N.C. - Not Connected.
7 N.C. - Not Connected.
8 N.C. - Not Connected.
9 TDI I ISP Transmit Data In. Programmable logic of the JTAG serial data input.
10 GND P Digital GND. Main GND plane.
MSC711xEVM Reference Manual, Rev. 0
3-6 Freescale Semiconductor
EVM Interconnect Signals
3.2.4 Slave UART Port Connector (P4)
Port P4 is connected to the UART port on the MSC711x Device. This is implemented by an ICL3221 transceiver, which internally generates the required RS-232 levels using a single 3.3V supply. The transceiver is always enabled.
The slave UART RS-232 port connector (P4) is a 9-pin, 90o, female D-type shielded connector. The RS-232 pins can be switched to drive an expansion connector.
RS-232 ports' pins are shown in Figure 3-3. In this figure, TX (Output) is “Transmit Data” and RX (Input) is “Receive Data”..
Figure 3-3. MSC711x RS-232 Serial Ports' Connector
P4 signals are outlined in Table 3-4.
Table 3-4. UART RS-232 Interconnect Signals
Pin No. Signal Name Description
1, 4, 6, 7 8, 9
N.C. These pins are not connected in this port.
2 TX Transmit Data output from the MSC711xEVM.
3 RX Receive Data input to the MSC711xEVM.
5 GND Ground signal of the MSC711xEVM.
MSC711xEVM Reference Manual, Rev. 0
Freescale Semiconductor 3-7
EVM Power and Connectors
3.2.5 SMD Header P5
The SMD header, P5, is a 36 pin connection to both the TDM and the Ethernet signals. The pin out is shown in Figure 3-4.
Figure 3-4. SMD Header Signals
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
3635
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
TDM1_RCLK
TDM1_RFS
TDM1_RD
TDM1_TCLK
TDM1_TFS
TDM1_TD
TDM0_RCLK
TDM0_RFS
TDM0_RD
TDM0_TCLK
TDM0_TFS
TDM0_TD
MDC_H8
MDIO
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
ETH_TXD0
ETH_TXD1
ETH_TXD2
ETH_TXD3
ETH_TXER
ETH_TXCLK
ETH_TXEN
ETH_RXER
ETH_RXCLK
ETH_RXDV
ETH_RXD0
ETH_RXD1
ETH_RXD2
ETH_RXD3
ETH_COL
ETH_CRS
P5
SMD Header
MSC711xEVM Reference Manual, Rev. 0
3-8 Freescale Semiconductor
EVM Interconnect Signals
Table 3-5. HDI Header Signals
Pin No. Signal Name Attribute Description
1 GND p Digital GND. Main ground plane.
2
3 HD0 I/O Host Interface Bidirectional, three-stated Data Bus Port: HD (0 - 15)
4 HD1
5 HD2
6 HD3
7 HD4
8 HD5
9 HD6
10 HD7
11 HD8
12 HD9
13 HD10
14 HD11
15 HD12
16 HD13
17 HD14
18 HD15
19 GND P Digital GND. Main ground plane.
20
21 HA0 I Host Interface Address Line HA (0 : 3)
22 HA1
23 HA2
24 HA3
25 HCS1 I Host Chip Select 1. The HDI CS is determined by the logical OR between HCS1 and HCS2.
26 HCS2 I Host Chip Select 2. The HDI CS is determined by the logical OR between HCS1 and HCS2.
27 HACK I/O, T.S. Host Acknowledge or Receive Host Request Output.Host DMA Acknowledge/Host Receive RequestWhen the HDI16 is programmed to interface to a single host request, this pin is the host acknowledge Schmitt trigger input in host DMA mode (HACK). The polarity of the host DMA acknowledge is programmable.
MSC711xEVM Reference Manual, Rev. 0
Freescale Semiconductor 3-9
EVM Power and Connectors
3.2.6 Power-On Configuration Header (P6)
The signals received on the 10 Pin male header P6 are explained in Figure 3-5.
Figure 3-5. Header P6 - Power-On Configuration Signals
3.2.7 Stereo Phone Jack Connectors (P7, P8)
EVM connector P7 is the stereo line in phone jack, while connector P8 is the stereo line out phone jack.
2
4
6
8
10
1
3
5
7
9
EVENT4
EVENT3
EVENT2
EVENT1
EVENT0
DBREQ
nSC_NMI
nPORESET
nHRESET
X
+
+
+
+
+
+
+
+
+
+
P 6
CON10AP
MSC711xEVM Reference Manual, Rev. 0
3-10 Freescale Semiconductor
EVM Interconnect Signals
3.2.8 Host Debug OCE10 (SYS) Connector (P9)
Connector P9 is a Freescale standard DSP JTAG/OCE10 connector featuring a 14-pin, 90o 2-row header connector with key. Host debug accesses all processors joined by the JTAG chain via connector P9. This connector’s pinout shown in Table 3-6.
Caution: When driven by an external tool, pin 9 (HRESET) MUST be driven with an Open Drain gate. Failure to do so may result in permanent damage to the MSC711xEVM logic.
Table 3-6. JTAG/OCE10 Connector-Interconnect Signals
Pin No. Signal Name Attribute Description
1 TDIh I Transmit Data In. MSC711x’s JTAG serial data input - sampled on the rising edge of TCK.
2 GND P Digital GND. Main GND plane.
3 TDOhc O Transmit Data Output. DSP JTAG serial data output driven by falling edge of TCK.
4 GND P Digital GND. Main GND plane.
5 TCKhc I Test port clock. The clock shifts in/out data to/from JTAG logic. Data is driven on the falling edge of TCK and sampled both internally and externally on it’s rising edge.
6 GND P Digital GND. Main GND plane.
7 N.C. - Not Connected.
8 KEY - No pin in connector. Serves for correct plug insertion.
9 HRESET I/O,P.U. When asserted by external H/W Hard-Reset sequence is generated. During that sequence the MSC8103 asserts for 512 system clocks. Pulled-up on the ADS using a 1KW resistor.When driven by an external tool it MUST be driven with an Open Drain gate. Failure to do so may result in permanent damage to the MSC711x and/or to EVM logic.
10 TMSh I Test Mode Select. Signal is qualified with TCK in a same manner as TDI - changes the state of the JTAG machines. The line is internally pulled-up by the MSC8103.
11 VDD P Connect to 3.3V power supply bus via protection resistor. May be used for Command Convertor power.
12 N.C. - Not Connected.
13
14 TRSThb I Test port reset. When signal is active (low) it resets the JTAG logic. The line is pulled-down on the ADS with a 2.2KW resistor in order to provide continuous JTAG logic reset when the connector is unplugged.
MSC711xEVM Reference Manual, Rev. 0
Freescale Semiconductor 3-11
EVM Power and Connectors
A front view of Connector P9 is shown in Figure 3-6.
Figure 3-6. JTAG/OCE10 Connector, Front View
3.2.9 Host Interface (HDI) Connector (P10)
Signals related to the individual pins of header P10, the HDI connector, are shown in Figure 3-7.
Figure 3-7. Host Interface Connector Signals
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
3635
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
GND
HD1
HD3
HD5
HD7
HD9
HD11
HD13
HD15
GND
HA1
HA3
N.C.
GND
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
GND
HD0
HD2
HD4
HD6
HD8
HD10
HD14
GND
HA0
HA2
HCS1
HACK
HRW
3.3V
GND
HD12
HRESET
HCS2
PORESET
HDS
HREQ
P10
Host Interface Connector
MSC711xEVM Reference Manual, Rev. 0
3-12 Freescale Semiconductor
EVM Functional Description 4This chapter discusses the MSC711xEVM block diagram and the functionality it describes. The design details of the various modules that make up the MSC711xEVM are described. This includes software initialization of the board.
4.1 MSC711xEVM Block Diagram
The MSC711xEVM block diagram is shown in Figure 4-1.
Figure 4-1. EVM Block Diagram
HostHeader
JTAG Port14 Pin Connector
25 Pin9 Pin
CommandConverter
ModuleRS-232
DDR16 Meg x 16 bitDDR16 Meg x 16 bit
RJ45MII 10/100M
Ethernet PHY
LDO Regulators for:+2.5V, +3.3V, +1.2V
CODEC
Analog I/O
TDMHeader
OUTPUTS HEADER
I2CEEPROM
Stereo
CODEC
MSC711x Memory Bus
TDM/MAC
UART
TDMx2
HDI16
I2C
JTAG/OCE10
32 bitI2C Bus
HDI Bus
TDM Bus
Connection to:TimersInterruptsGPIO
MSC711xEVM Reference Manual, Rev. 0
Freescale Semiconductor 4-1
EVM Functional Description
4.2 Reset and Reset-Configuration
There are several reset sources on the MSC711xEVM that generate two types of reset:
• MSC711x Power On Reset (PORESET)
• MSC711x Manual Hard-Reset (HRESET)
All MSC711xEVM reset sources are fed into the MSC711x reset controller, which takes different actions depending on the source of the reset, as shown in Table 4-1.
4.2.1 Power-On Reset
The power on reset to the MSC711x initializes the processor state after power up. The entire MSC711x device is reset. PLL and clock synthesis states are reset. HRESET is driven and the SC1400 core is reset. System configuration is sampled from SW3. Configuration pins are configured only at the deassertion of PORESET.
A dedicated logic asserts PORESET input for a period long enough to include the MSC711x core voltages’ stabilization, which are powered by a different voltage regulator.
Table 4-1. Reset Sources
Reset Name Source Description
Power-On Reset (PORESET) Input Initiates the PORESET flow that resets the EVM and configures various aspicts of the MSC711x.
Hard-Reset (HRESET) SW2 Initiates the hard reset flow that configures various attributes of the MSC711x device.
Software Watchdog Reset Internal A software watchdog reset is initiated when the watchdog count reaches zero. The enabled software event then generates an internal hard reset sequence (HRESET).
Bus Monitor Reset Internal A bus monitor hard reset is asserted when the bus monitor count reaches zero. The enabled bus monitor event then generates HRESET.
JTAG Commands Internal When an EXTEST, CLAMP or HIGHZ JTAG command executes, JTAG logic generates an internal soft reset sequence.
MSC711xEVM Reference Manual, Rev. 0
4-2 Freescale Semiconductor
Reset and Reset-Configuration
4.2.2 Power-On Reset Configuration
At the rising edge of the Power-On signal, the MSC711x samples four pins to determine configuration. Those pins are BM0, BM1, SWTE and DBREQ. These are sampled only once after power-on reset.
4.2.3 Hard Reset
Hard-Reset (HRESET) signal may be generated on the EVM at the following sources:
• COP/JTAG Port
• OCE10/JTAG Port
• Manual Hard-Reset (SW2)
• Software Watchdog Reset
• Bus Monitor Reset
Hard-Reset, when generated, causes the MSC711x to reset all its internal hardware except for PLL logic and reacquire the hard-reset configuration from its current source. Since hard-reset resets also the refresh logic for dynamic RAMs, their content is lost as well.
HRESET is an open-drain signal and must be driven with an open-drain gate whenever an external source is driving it. Otherwise, contention will occur over that line, which might cause permanent damage to either board logic and/or to the MSC711x.
Table 4-2. Pwer-On Reset Configuration
Signal Description Settings
BM1 - BM0 Boot Mode: (SW3 - subswitches 3 and 4) Sampled on the rising edge of PORESET, these lines determine the boot mode.
0 - Boot from HDI16 port
1 - Boot from I2C2 - Reserved3 - Reserved
SWTE Software Watchdog Timer Enable: (SW3 - subswitch 2)Sampled on the rising edge of PORESET, this bit vlaue can override the timer functionality.
0 - Watchdog Timer disabled1 - Watchdog Timer enabled
DBREQ Debug Request: (SW3 - subswitch 1)
MSC711xEVM Reference Manual, Rev. 0
Freescale Semiconductor 4-3
EVM Functional Description
4.2.4 External Port Hard Reset
To provide convenient hard-reset capability for an OCE10/JTAG controller, an HRESET line appears at the OCE10/JTAG port connector. The COP/JTAG controller may directly generate hard-reset by asserting (low) this line. This HRESET effects only the MSC711x.
4.2.5 Manual Hard Reset
To allow run-time hard-reset on the EVM, manual HRESET is facilitated. The MSC711x has its own HRESET push-button (SW2).
4.2.6 Internal Sources Hard Reset
The MSC711x has two internal sources that can generate HRESET due to specific events:
• Software Watchdog Timer Reset
• Bus Timeout Monitor Reset
4.3 EVM Clock
The following paragraphs describe clocking on the MSC7116EVM. There are three main clock circuits on board:
• MSC711x System Clock (20MHz).
• CODEC clock (8.192MHz).
• CPLD clock (40MHz).
The MSC711x chip requires a reference clock input (CLKIN). From this clock input the internal clock synthesis module at the MSC711x core generates all the timing needs of the chip. The recommended CLKIN frequency is 20MHz.
MSC711xEVM Reference Manual, Rev. 0
4-4 Freescale Semiconductor
EVM Clock
The MSC711xEVM timing system is shown in Figure 4-2.
Figure 4-2. EVM Timing System
MSC711xEVM Reference Manual, Rev. 0
Freescale Semiconductor 4-5
EVM Functional Description
The MSC711x timing system has the clock synthesis module at its core. This module is composed of the following blocks:
• Phase lock loop (PLL) with associated multipliers and dividers
• AHB Bus Clock Divider
• APB Bus Clock Divider
• Timer Clock MUX
• Wakeup Control
• Control registers
Together, these blocks generate the clock signals used for core and peripheral clocking. An external input clock input provides a reference clock for the system.
The Core Clock is obtained by a pre-division of the input clock and multiplying the frequency in the PLL. The AHB clock is generated in a manner similar to the core clock, but with an additional division stage.
The SkyBlue clock is generated from the AHB clock. The APB clock is generated from the AHB clock. The timer clock can be derived from the external input clock or from the SkyBlue clock.
The control register is used for programming the clock synthesis module. The wakeup control block is used for waking the chip out of its low power modes.
4.4 TDM Interface and Stereo Codec
The MSC711x chip has 3 TDM ports: TDM0,TDM1 and TDM2.
The TDM2 port uses BI functional pins with the ETHERNET port and cannot be used if the ETHERNET port is working (in MII MODE).
The TDM0 port is used in the MSC711x_EVM board to connect to the AKM stereo codec (AK4554 or AK4550). The codec can sample the analog input stereo signal at a variable sampling rate that is determined automatically by the combination of 3 input clocks that are provided to the codec. For details, see the AKM AK4554 Codec Data Sheet in the system clock input section.
The MSC711x_EVM board has a 8.192MHz oscillator that is connected to pin EVENT0 in the MSX711x chip, This is the input for the Timer module that can divide the basic 8.192MHz frequency to 4.096MHz and 2.048MHz and bring it back to pin EVENT1 that is connected to the Master Clock pin at the codec (MCLK). For details, see Figure 4-2 and the schematics in Appendix A.
This gives the user the option to decide the codec sampling rate frequency (32KHz , 16KHz or 8KHz), or to determine another frequency according to the divider in the MSC711x timer unit.
MSC711xEVM Reference Manual, Rev. 0
4-6 Freescale Semiconductor
I2C Boot EEPROM
4.5 I2C Boot EEPROM
The MSC711x device can be booted from the HDI16 BUS or from external EEPROM with serial I2C interface. In the MSC711xEVM a serial EEPROM device such as the M24256-B from STmicroelectronics Co. is used. The memory of this standard 256KBit device is organized as 32Kx8. The device has the capability of hardware write-protecting its memory map. The device is fitted into an EVM socket to make it capable of being reprogrammed by an external programmer. Other replacement chips for the EVM serial I2C EEPROM are:
• Microchip 24LC256.
• ATMEL AT24C256.
• CATALYST CAT24WC256.
4.5.1 EVM EEPROM Operation
Visual indication of the EVM SCL and SDA line status is provided by corresponding Red and Green LED's (LDx and LDx, respectively). The I2C bus is connected to a two test points header.
The I2C EEPROM address is set to "000". The serial EEPROM I2C Bus clock is 400KHz.
4.5.2 EVM EEPROM Summary Description
The I2C compatible electrically erasable programmable read-only memory (EEPROM) device (M24256-B) is organized as 32K x 8 bits, as shown in .
Figure 4-3. I2C EEPROM Description
MSC711xEVM Reference Manual, Rev. 0
Freescale Semiconductor 4-7
EVM Functional Description
I2C EEPROM device pins are described in Table 4-3.
These devices are compatible with the I2C memory protocol. This is a two wire serial interface that uses a bi-directional data bus and serial clock. The memory carries a built-in 4- bit unique Device Type Identifier code (1010) in accordance with the I2C bus definition.
The memory behaves as a slave device in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a START condition, generated by the bus master. The START condition is followed by a Device Select Code and RW bit, as described in Figure 4-4, terminated by an acknowledge bit.
Figure 4-4. Device Select Code
When writing data to the memory, the memory inserts an acknowledge bit during the 9th bit time, following the bus master's 8-bit transmission.
When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a STOP condition after an Ack for WRITE, and after a No Ack for READ.
Table 4-3. EEPROM Device Pins and Signals
Pin Signal
E0, E1, E2 Chip Enable
SDA Serial Data
SCL Serial Clock
WC Write Control
VCC Supply Voltage
VSS Ground
MSC711xEVM Reference Manual, Rev. 0
4-8 Freescale Semiconductor
JTAG/OCE10
4.6 JTAG/OCE10
The JTAG /OCE10 test access port (TAP) connection, command converter and I2C Boot EEPROM are detailed in the block diagram represented in Figure 4-5.
Figure 4-5. Parallel Port Connection (JTAG )
4.6.1 JTAG TAP Connection
The OCE10’s JTAG interface requires a test access port (TAP) controller that includes OCE-10 -specific logic and support for three OCE-10-specific JTAG instructions. The JTAG connection on the MSC711x device can be provided via two ways:
• Direct connection to the appropriate header connector.
• Optional Host PC Parallel Port connection.
4.6.2 JTAG/OCE10 Header
The JTAG header provides connection between the MSC711x device and any external compatible JTAG converter such as a Wiggler etc.
Figure 4-6. JTAG/OCE10 Port Connector
ParallelPort
VoltageTransceiver
74LVX161284(Fairchild)
MSC711xDevice
JTAG
14pin OCE10 Header
MSC711xEVM Reference Manual, Rev. 0
Freescale Semiconductor 4-9
EVM Functional Description
Pins and signals of the the JTAG/OCE10 header are described in Table 4-4.
4.6.3 Parallel Port Connection
The MSC711xEVM is connected to the host PC parallel port via an on board JTAG converter operating in SPP mode.
Table 4-4. JTAG/OCE10 Header Pinout
Pin No. Signal Attribute Description
1 TDI I Transmit Data In. This is the JTAG serial data input of the ADS, sampled on the rising edge of TCK.
2 GND P Digital Ground. Main GND plane.
3 TDO O Transmit Data Output. This the MSC711x JTAG serial data output driven by Falling edge of TCK.
4 GND P Digital Ground. Main GND plane.
5 TCK I Test port Clock. This clock shifts in / out data to / from the MSC711xEVM JTAG logic. Data is driven on the falling edge of TCK and is sampled both internally and externally on it's rising edge.TCK is pulled up internally by the MSC711x.`
6 GND P Digital Ground. Main GND plane.
7 N.C. - Not Connected.
8 KEY - No pin in connector. Serve for correct plug insertion. Not Connected.
9 RESET I/O, P.U. In fact, HRESET. When asserted by external H/W, generates Hard-Reset sequence for the MSC711x. During that sequence, asserted by the MSC711x. for 512 system clocks. Pulled Up on the EVM using a 10K pullup.
Caution: When driven by an external tool, this signal MUST be driven with an Open Drain gate. Failure to do so might result in permanent damage to the MSC711x and / or to EVM logic.
10 TMS I Test Mode Select. This signal, qualified with TCK in a same manner as TDI, changes the state of the JTAG machines. This line is pulled up internally by the MSC711x.
11 VDD P Connect to 3.3V power supply bus. May be used for Command Convertor power.
12 N.C. - Not Connected
13 N.C - Not Connected
14 TRESET I Test Port Reset. When this signal is active (Low), it resets the JTAG logic of the MSC711x. This line is pulled-down on theEVM with a 1K resistor, to provide constant reset of the JTAG logic.
MSC711xEVM Reference Manual, Rev. 0
4-10 Freescale Semiconductor
DDR SDRAM Interface
4.6.4 JTAG Operational LED LD7
On the EVM, LD7 indicates the current JTAG operation.
When LD7 is lit, a parallel port cable is not attached to the EVM board. The user can connect to the board using a third company external device via the OCE10/JTAG connector (P9).
When the parallel cable is connected at P1, LD7 turns off and communication is made by an internal device.
4.7 DDR SDRAM Interface
The External Memory Interface in the MSC711x has the following characteristics:
• Page-mode DDR-RAM machine.
• Glueless interface to 100 MHz 14-bit page mode DDR-RAM.
• 64 MByte external address space (14-bit external address bus with 4 banks).
• 16-bit or 32-bit external data bus.
The MSC711xEVM uses a 32 bit external data bus. The most common DDR SDRAM device chip @16bit is 16M x 16bit = 256Mbit. Therefore, for the MSC711xEVM uses 2 DDR chips. The devices to be used are:
• MICRON: MT46V8M16
• HYNIX :HY5DU281622ET
4.7.1 SSTL_2 Interface
Previous SDR memory technology used LVTTL and a fixed voltage level for its signal interface. DDR SDRAM utilizes differential inputs and a reference voltage for all interface signals. This interface is called SSTL_2, which stands for “Stub Series Terminated Logic for 2.5 volts”.
The benefits of the SSTL_2 interface include symmetrical low and high logic levels, improved signal integrity and better noise immunity.
4.7.2 SSTL_2 Signals and Line Termination
The typical SSTL_2 interface includes series termination and a pull-up to the termination voltage (refer to Figure 6 1 : Typical SSTL_2 interface, with active termination.). The SSTL_2 interface uses a reference voltage and differential input to determine the logic levels. The reference voltage is defined to be half of the supply voltage and the termination voltage equals the reference voltage. (VDD = 2.5 volts, VREF = VTT = 1.25 volts).
MSC711xEVM Reference Manual, Rev. 0
Freescale Semiconductor 4-11
EVM Functional Description
This is an active termination, as shown in Figure 4-7.
Figure 4-7. Typical SSTL_2 Interface
MSC711xEVM Reference Manual, Rev. 0
4-12 Freescale Semiconductor
DDR SDRAM Interface
4.7.3 MSC711x_EVM DDR Connection
In the bi-directional data bus there is a problem because the source is changing all the time. The solution is to locate the MSC711x and the DDR chip as close as possible on the board and to put the termination resistor between them. The MSC711xEVM DDR Connection is shown in Figure 4-8.
Figure 4-8. DDR - MSC711x Connection
MSC711x DDR
DDR8M x 16bit= 128Mbit
DDR8M x 16bit= 128Mbit
VTTRegulator
RT
RT
Rs22Ω
Rs22Ω
Rs22ΩRs22ΩRs22ΩRs22ΩRs22ΩRs22Ω
Rs22ΩRs22Ω
Rs22ΩRs22Ω
ADDRESS [12:0]BA0, BA1
WE
CASRASCKECKCK
CSDM [1:0]
DQS [1:0]
VREF
DATA [31:0]16
132
22
RT is connectedin this form to allthe DDR lines
MSC711xEVM Reference Manual, Rev. 0
Freescale Semiconductor 4-13
EVM Functional Description
4.8 Fast Ethernet (10/100 Base-T)
A Fast Ethernet port 10/100-Base-T I/F is provided on the MSC7116_EVM. The Ethernet PHY used on the MSC7116_EVM is VT6103 by VIA. This is a physical layer single-chip transceiver for 100BASE-TX and 10BASE-TX operations.
The VT6103 connects to the Medium Access Control (MAC) layer through the Media Independent Interface (MII). The MSC711x port can be switched between 2 Ethernet modes: MII and RMII. But on the MSC711x_EVM only the MII mode is used.
The VT6103 uses a low power and high performance CMOS process. It contains the entire physical layer function of 100BASE-TX, as defined by IEEE802.3u. The VT6103 provides support for the auto-negotiation function, utilizing automatic media speed and protocol selection.
The magnetic used in the MSC7116_EVM is H1265 from PULSE. But there are another vendors for this magnetic, like Traxcom TRC88515.
The Fast Ethernet and Ethernet schemes are shown in Figure 4-9.
Figure 4-9. EVM Fast Ethernet and Ethernet
MSC711x VT6103
Magnetic
1 : 1 RJ45
RX [3..0]RXERRRXENRXCLKRXDV
TX [3..0]TXERRTXENTXCLKTXDV
MDCMDIOCOLCRSIRQ12PORESET
MII RX [3..0]MII RXERRMII RXENMII RXCLKMII RXDV
MII TX [3..0]MII TXERRMII TXENMII TXCLKMII TXDV
MDCMDIOCOLCRSMII INTRESET
RX+
RX-
TX-
TX-
PORESET
MSC711xEVM Reference Manual, Rev. 0
4-14 Freescale Semiconductor
Fast Ethernet (10/100 Base-T)
4.8.1 VT6103 Control
The VIA VT6103 ETHERNET PHY is controlled via a 2 wire interface: a clock (MDC), and a bidirectional data line (MDIO). This is in fact a bus, i.e., up to 32 devices may reside on it,. The protocol defines a 5-bit slave address field, which is compared with the slave address assigned to each device by hardware during device reset, according to the levels on some pins.
The MPC interfaces this port using the following two pins:
• MII_MDIO for MDIO.
• MII_MDC for MDC.
The MDIO port may interrupt a host in 2 ways: by driving low the MDIO line during IDLE time, or by using a dedicated interrupt line. This line (MDINT) is connected to the MSC711x IRQ X line in Fast Ethernet I/F and IRQ XX line in Ethernet I/F. It appears also at the expansion connectors.
MSC711xEVM Reference Manual, Rev. 0
Freescale Semiconductor 4-15
EVM Functional Description
MSC711xEVM Reference Manual, Rev. 0
4-16 Freescale Semiconductor
EVM Memory Maps and Bus Mapping 55.1 Memory Controllers
The MSC711xEVM memory controller supports an interface to external memory and peripheral devices on the system bus and enables interfacing with the HDI16 bus.
The MSC711x memory controller provides a glueless interface between the internal MSC711x bus and the external double data rate (DDR) SDRAM memory modules. It establishes this interface by translating internal bus accesses to the appropriate address, data and control signals for DDR SDRAMs.
5.2 Memory Maps
The MSC711x memory maps are discussed in the following sections. Both On and Off chip address space is discussed, although the Off chip address space is used for the DDR only. The memory maps defined in the following tables are only a recommendation. Users may choose to work with alternative memory mapping. The described mode is supported by Metrowerks’ CodeWarrior debug tool.
5.2.1 Extended Core Memory 1
When accessed by the SC1400 core, the MSC711x extended core memory address range is shown in Table 5-1.
Table 5-1. Extended Core Memory (M1)
Address Range Description Size
01800000 - 0182FFFF M1 memory, when accessed by the SC1400 core 192 KB
01830000 - 01F7FFFF Reserved —
MSC711xEVM Reference Manual, Rev. 0
Freescale Semiconductor 5-1
EVM Memory Maps and Bus Mapping
5.2.2 Extended Core Registers (ICache Array)
The MSC711x extended core register map is shown in Table 5-2.
5.2.3 On-Chip Memory Outside Platform (M2, Boot ROM)
The MSC711x outside platform on-chip memory map is shown in Table 5-3.
5.2.4 Extended Core Memory - 2
When accessed by the DMA (using the ADDMA bus), or accessed by the Ethernet MAC (using the AMENT bus), the address range of the MSC711x extended core M1 memory is shown in Table 5-4.
Table 5-2. Extended Core Registers, ICache Array
Address Range Description Size
00EFF000 - 00EFFFFF OCE10 Registers —
00F00000 - 00F1FFFF Instruction Cache RegistersExtended Core Interface Registers
—
00F20000 - 00F23FFF ICache Array Contents 16 KB
00F24000 - 00FFFFFF Reserved —
Table 5-3. On-Chip Memory, M2 Boot ROM
Address Range Description Size
01000000 - 0102FFFF M2 Memory 192 KB
01030000 - 013FFFFF Reserved —
01400000 - 01401FFF Boot ROM 8 KB
01402000 - 017FFFFF Reserved —
Table 5-4. Extended Core Memory (M1)
Address Range Description Size
00000000 - 0002FFFF M1 memory, when accessed by the DMA (using the ADDMA bus) or by the Ethernet MAC (using the AMENT bus).
192 KB
00030000 - 00EFFDFF Reserved —
MSC711xEVM Reference Manual, Rev. 0
5-2 Freescale Semiconductor
Host Processor Interface (HDI16)
5.2.5 Peripherals
You can access peripherals outside the platform using the ASTH, ASSB, and ASAPB buses at the following address ranges, as shown in Table 5-5.
5.2.6 Off-Chip Address Space
You can access off chip memory (DDR memory) using the ASEMI bus at the following address ranges, as shown in Table 5-6.
5.3 Host Processor Interface (HDI16)
The host processor (outsider host) is connected to the MSC711x chip through the HDI16 bus, via the EVM’s 36 pin male header P10. The host interface (HDI16) in the MSC711x chip is a 16-bit wide, full-duplex, double-buffered parallel port that can directly connect to the data bus of a host processor.
The HDI16 port in the MSC711x supports a variety of buses and gluelessly connects with a number of industry-standard microcomputers, microprocessors, and DSPs.
The HDI16 port is designed so that its host bus can be asynchronously accessed independent of the clocks on the chip. This is accomplished by dividing the HDI16 registers into two banks:
• "External Host register bank is accessible by an external host.
• "Chip register bank is accessible by the MSC711x device.
The HDI16 supports two classes of interfaces to external devices:
• "Host processor/Microcontroller (MCU) connection interface.
• "DMA controller interface.
Table 5-5. Peripheral Access
Address Range Description Size
01F80000 - 03FFFFFF TDM / HDI16 high speed ports (via ASTH bus) —
04000000 - 05FFFFFF IPBus peripheral registers (via ASSB bus) 32 KB
06000000 - 07FFFFFF APB peripheral registers (via ASAPB bus) 32 KB
Table 5-6. DDR Memory Access
Address Range Description Size
08000000 - 1FFFFFFF Reserved —
20000000 - FFFFFFFF External DDR memory (via ASEMI bus) —
MSC711xEVM Reference Manual, Rev. 0
Freescale Semiconductor 5-3
EVM Memory Maps and Bus Mapping
5.3.1 HDI16 Configuration
On the MSC711x device, the HLEND bit in the HPCR register must always be "0", which configures the HDI16 module for big endian operation. This is the default value out of reset.
5.3.1.1 Special MSC711x HDI16 Port Characters
The HDI16 port on the MSC711x is different from the MSC8101 HDI16 port. The main differences lie in the following features:
• "Bits on HD bus are numbered with bit 0 as the LSB.
• "Bits on HA bus are numbered with bit 0 as the LSB.
• "Bits in HDI16 registers are numbered with bit 0 as the LSB.
• "The Host Port Pin (HPE)does not exist as a pin on the MSC711x. Instead this signal is internally tied as asserted, i.e., host port is enabled! (to disable this port use the HEN bit in the HPCR register).
• "HDSP pin value is sampled only on reset.
• "H8BIT pin value is sampled only on reset.
• "Host Address Bus uses only 3 pins HA[2:0], pin HA(3) is not in use, it is internally asserted to '0'.
• "The reset configuration registers are not accessible by an external host and are not supported.
5.3.1.2 HDI16 Bus Signals
The HDI16 bus carries the following signals:
• HD[15:0] host data bus (in 16-bit mode).
• HD[7:0] host data bus (in 8-bit mode).
• HA[2:0] host address lines .
• HRW/HRD read/write select (HRW) or read strobe (HRD).
• HDS/HWR data strobe (HDS) or write strobe (HWR).
• HCS1 host chip-select 1.
• HCS2 host chip-select 2.
• HREQ/HTRQ host request (HREQ) or host transmit request (HTRQ).
• HACK/HRRQ host acknowledge (HACK) or host receive request (HRRQ).
• HDDS dual data strobe control input.
MSC711xEVM Reference Manual, Rev. 0
5-4 Freescale Semiconductor
Host Processor Interface (HDI16)
The HDI16 Bus connection to the host processor header are shown inFigure 5-1 .
Figure 5-1. HDI16 Bus Connection to Header P10
The Host I/F connector (P10) is a 36 pin, two row, header connector. The connection between the MSC711xEVM board and the Host Board is by a 36 line flat cable. The pins and signals of connector P10 are shown in Figure 5-2 and Table 5-6, respectively.
Figure 5-2. The Host I/F Connector.
MSC711x
HDI Header
HD[15:0]
HA[2-0],CS1*
HRW,HDS*
HRRQ*
MSC711xEVM Reference Manual, Rev. 0
Freescale Semiconductor 5-5
EVM Memory Maps and Bus Mapping
MSC711xEVM Reference Manual, Rev. 0
5-6 Freescale Semiconductor
MSC711xEVM Schematics AA.1 MSC711xEVM Schematics
Schematics for the MSC711xEVM board can be seen on the following pages and are listed in Table A-1.
Table A-1. MSC711xEVM Schematics
Schematic Title Page
Block Diagram A-2
StarLite DDR A-3
StarLite HDI A-4
StarLite System and PIO A-5
StarLite Power A-6
Ethernet A-7
CODEC A-8
JTAG_Master A-9
Parallel Port A-10
Power A-11
MSC711xEVM Reference Manual, Rev. 0
Freescale Semiconductor A-1
A.1.1 Block Diagram55
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3.3V
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2 X DDR 16 BIT
VIA VT6103 ETH PHY10 / 100
POWER
2.5V
1.2V
MII
HDI BUS
HDI HEADER 36 PIN
RJ-45
I2C BUSI2C EPROM
PARALEL PORT TOJTAG CONVERTER
JTAG
EOANCE_HEADER 14 PIN
TDM1, GPIO'S,NMIEVENTS,TIMERS HEADER
CODECCODECANALOG I/O
TDM0
MSC711xEVM Reference Manual, Rev. 0
A-2 Freescale Semiconductor
MSC711xEVM Schematics
A.1.2 StarLite DDR55
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DDRESS6
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DDRESS12
DDR_D
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DDRESS13
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QM0
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DDR_D
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A1
DDR_D
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DDR_D
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DDR_D
QM0
DDR_D
QS2
DDR_D
QS0
DDR_D
QM1
DDR_A
DDRESS13
DDR_D
ATA
11
DDR_D
ATA
25
DDR_D
ATA
21
DDR_D
ATA
12
DDR_D
ATA
13
DDR_D
ATA
13
DDR_D
ATA
2
D_D
QM1
DDR_D
ATA
26
DDR_D
ATA
22
nDDR_R
AS
DDR_C
KE
nDDR_W
EnD
DR_C
AS
nDDR_C
S0
D_D
QM2
DDR_A
DDRESS13
DDR_D
ATA
4
DDR_D
ATA
0
DDR_D
ATA
11
DDR_D
ATA
8
DDR_D
ATA
4
DDR_D
ATA
13
DDR_D
ATA
5
DDR_D
ATA
15
DDR_D
ATA
3
DDR_D
ATA
6
DDR_D
ATA
14
DDR_D
ATA
2DDR_D
ATA
1
DDR_D
ATA
10DDR_D
ATA
9
DDR_D
ATA
7
DDR_D
ATA
12DDR_A
DDRESS12
DDR_D
ATA
7
D_D
QS0
D_D
QS1
DDR_A
DDRESS13
DDR_D
ATA
14DDR_D
ATA
15DDR_D
ATA
16DDR_D
ATA
17DDR_D
ATA
18
DDR_B
A0
DDR_B
A1
DDR_D
ATA
5
DDR_A
DDRESS1
DDR_A
DDRESS3
DDR_A
DDRESS4
DDR_A
DDRESS2
DDR_A
DDRESS8
DDR_A
DDRESS9
DDR_A
DDRESS7
DDR_A
DDRESS5
DDR_A
DDRESS6
DDR_A
DDRESS10
DDR_A
DDRESS11
DDR_A
DDRESS0
DDR_D
ATA
0
D_D
QM3
DDR_D
ATA
6
DDR_D
ATA
16
DDR_D
ATA
28
DDR_D
ATA
19DDR_D
ATA
20DDR_D
ATA
21DDR_D
ATA
22
DDR_D
ATA
8
DDR_D
ATA
23
DDR_A
DDRESS1
DDR_D
ATA
24
DDR_A
DDRESS4
DDR_A
DDRESS3
DDR_A
DDRESS2
DDR_A
DDRESS5
DDR_A
DDRESS11
DDR_A
DDRESS8
DDR_A
DDRESS7
DDR_A
DDRESS6
DDR_A
DDRESS10
DDR_A
DDRESS9
DDR_A
DDRESS0
DDR_D
ATA
25
DDR_A
DDRESS0
DDR_A
DDRESS8
DDR_D
ATA
26
DDR_D
ATA
19
DDR_D
ATA
31
DDR_D
ATA
27DDR_D
ATA
28DDR_D
ATA
29DDR_D
ATA
30DDR_D
ATA
31
DDR_A
DDRESS12
DDR_D
ATA
11
DDR_D
ATA
17
DDR_D
ATA
29
DDR_A
DDRESS9
DDR_D
ATA
9
DDR_A
DDRESS[13:0]
DDR_A
DDRESS11
DDR_B
A0
DDR_B
A1
DDR_D
ATA
18
DDR_D
ATA
30
DDR_B
A0
nDDR_C
S0
DDR_A
DDRESS10
DDR_D
ATA
10
DDR_A
DDRESS4
DDR_A
DDRESS0
DDR_D
ATA
24
DDR_A
DDRESS7
nDDR_R
AS
nDDR_W
EnD
DR_C
AS
nDDR_C
S0
DDR_A
DDRESS3
DDR_D
ATA
22
DDR_D
ATA
30
DDR_D
ATA
21
DDR_D
ATA
25
DDR_D
ATA
27
DDR_D
ATA
19
DDR_D
ATA
28
DDR_D
ATA
31
DDR_D
ATA
17DDR_D
ATA
16
DDR_D
ATA
26
DDR_D
ATA
29
DDR_D
ATA
24DDR_D
ATA
23
DDR_D
ATA
20
DDR_D
ATA
18
D_D
QS3
D_D
QS2
DDR_D
ATA
27
DDR_A
DDRESS5
DDR_A
DDRESS1
DDR_C
KE
DDR_D
ATA
1
VTT
GND
VTT
VTT
VTT
GND
GND
VREF
GND
2V5
VREF
GND
GND
2V5
GND
2V5
GND
2V5
VREF
2V5
GND
2V5
GND
D_D
QM3
16
D_D
QM1
16D_D
QM0
16
D_D
QM2
16
D_D
QS3
16
D_D
QS0
16D_D
QS1
16D_D
QS2
16
DDR_B
A0
16DDR_B
A1
16
nDDR_R
AS
16nD
DR_C
AS
16nD
DR_W
E16
DDR_C
KE
16DDR_C
K16
nDDR_C
K16
nDDR_C
S0
16
DDR_D
QM0
DDR_D
QM1
DDR_D
QM3
DDR_D
QM2
DDR_D
QS0
DDR_D
QS3
DDR_D
QS2
DDR_D
QS1
Title
Size
Docum
ent Num
berRev
Date:
Sheet
of
PROTO
MSC711xE
VM: 711x_D
DR
Freescale Sem
iconductor Israel Ltd.
Metrow
erks Israel
A3
311
Wednesday, A
pril 06, 2005
Title
Size
Docum
ent Num
berRev
Date:
Sheet
of
PROTO
MSC711xE
VM: 711x_D
DR
Freescale Sem
iconductor Israel Ltd.
Metrow
erks Israel
A3
311
Wednesday, A
pril 06, 2005
Title
Size
Docum
ent Num
berRev
Date:
Sheet
of
PROTO
MSC711xE
VM: 711x_D
DR
Freescale Sem
iconductor Israel Ltd.
Metrow
erks Israel
A3
311
Wednesday, A
pril 06, 2005
C20
0.1uF
C20
0.1uF
18
RN5A
24.RN5A
24.
R92
22R1
R92
22R1
27
RN29B
24.RN29B
24.
45
RN15D
22RN15D
22
45
RN8D
24.RN8D
24.
18
RN26A
22RN26A
22
18
RN3A
24.RN3A
24.
27
RN25B
22RN25B
22
36
RN11C
24.RN11C
24.
45
RN29D
24.RN29D
24.
27
RN32B
24.RN32B
24.
18
RN9A
24.RN9A
24.
R93
22R1
R93
22R1
18
RN10A
24.RN10A
24.
36
RN8C
24.RN8C
24.
36
RN26C
22RN26C
22
18
RN12A
22RN12A
22
27
RN28B
24.RN28B
24.
45
RN7D
24.RN7D
24.
36
RN3C
24.RN3C
24.
27
RN30B
24.RN30B
24.
45
RN32D
24.RN32D
24.
27
RN9B
24.RN9B
24.
27
RN10B
24.RN10B
24.
36
RN12C
22RN12C
22
27
RN7B
24.RN7B
24.
18
RN24A
22RN24A
22
45
RN28D
24.RN28D
24.
R89
22R1
R89
22R1
45
RN30D
24.RN30D
24.
18
RN14A
22RN14A
22
45
RN25D
22RN25D
22
36
RN16C
22RN16C
22
45
RN11D
24.RN11D
24.
36
RN22C
22RN22C
22
36
RN24C
22RN24C
22
C24
0.1uF
C24
0.1uF
R32
22R1
R32
22R1
C15
0.1uF
C15
0.1uF
36
RN14C
22RN14C
22
18
RN6A
24.RN6A
24.
R86
22R1
R86
22R1
C107
0.1uF
C107
0.1uF
VDD1
1
VDD2
18
VDD3
33
VDDQ1
3
VDDQ2
9
VDDQ3
15
VDDQ4
55
VDDQ5
61
VREF
49
VSS1
34
VSS2
48
VSS3
66
VSSQ1
6
VSSQ2
12
VSSQ4
58VSSQ3
52
VSSQ5
64
DDR_DRAM POWER
U11B
MT46V
8M16
DDR_DRAM POWER
U11B
MT46V
8M16
27
RN27B
24.RN27B
24.
18
RN23A
22RN23A
22
C117
0.1uFC117
0.1uF
C30
0.1uF
C30
0.1uF
C120
0.1uF
C120
0.1uFR77
22R1
R77
22R1
27
RN16B
22RN16B
22
36
RN6C
24.RN6C
24.
C125
0.1uF
C125
0.1uF
36
RN23C
22RN23C
22
R88
22R1
R88
22R1
27
RN13B
22RN13B
22
C17
0.1uF
C17
0.1uF
18
RN27A
24.RN27A
24.
18
RN16A
22RN16A
22
27
RN21B
22RN21B
22
C23
0.1uF
C23
0.1uF1
8RN31A
24.RN31A
24.
45
RN13D
22RN13D
22
27
RN4B
24.RN4B
24.
18
RN21A
22RN21A
22
45
RN16D
22RN16D
22
C131
0.1uF
C131
0.1uF
R103
22R1
R103
22R1
45
RN5D
24.RN5D
24.
R97
22R1
R97
22R1
18
RN4A
24.RN4A
24.
18
RN29A
24.RN29A
24.
DQ0
2
DQ1
4
DQ2
5
DQ3
7
DQ4
8
DQ5
10
DQ6
11
DQ7
13
DQ8
54
DQ9
56
DQ10
57
DQ11
59
DQ12
60
DQ13
62
DQ14
63
DQ15
65
A0
29
A1
30
A2
31
A3
32
A4
35
A5
36
A6
37
A7
38
A8
39
A9
40
A10/A
P28
A11
41
BA0
26
BA1
27
CAS#
22WE#
21
RAS#
23
CS#
24
LDQS
16
UDQS
51
LDM
20
UDM
47
NC1
14
NC2/A
1317
NC2
25
NC/A12
42
NC3
43
NC4
53
DNU1
19
DNU2
50
CKE
44
CK
45
CK#
46
DDR_DRAM
U20A
MT46V
8M16
DDR_DRAM
U20A
MT46V
8M16
18
RN15A
22RN15A
22
27
RN22B
22RN22B
22
18
RN22A
22RN22A
22
27
RN26B
22RN26B
22
C14
0.1uF
C14
0.1uF
36
RN5C
24.RN5C
24.
18
RN11A
24.RN11A
24.
C124
0.1uF
C124
0.1uF
36
RN29C
24.RN29C
24.
18
RN32A
24.RN32A
24.
R102
120R102
120
36
RN15C
22RN15C
22
27
RN8B
24.RN8B
24.
45
RN26D
22RN26D
22
27
RN12B
22RN12B
22
36
RN28C
24.RN28C
24.
27
RN3B
24.RN3B
24.
36
RN32C
24.RN32C
24.
36
RN9C
24.RN9C
24.
36
RN21C
22RN21C
22
36
RN10C
24.RN10C
24.
18
RN8A
24.RN8A
24.
45
RN12D
22RN12D
22
R18
100ohmR18
100ohm
18
RN7A
24.RN7A
24.
27
RN24B
22RN24B
22
36
RN7C
24.RN7C
24.
18
RN17A
22RN17A
22
45
RN3D
24.RN3D
24.
18
RN30A
24.RN30A
24.
27
RN14B
22RN14B
22
C11
0.1uF
C11
0.1uF
18
RN25A
22RN25A
22
27
RN11B
24.RN11B
24.
45
RN9D
24.RN9D
24.
A0
Y5
A1
Y4
A2
V7
A3
W7
A4
Y6
A5
V6
A6
W6
A7
W5
A8
W4
A9
Y3
A10
V5
A11
V4
A12
W3
A13
V3
BA0
V8
BA1
Y7
RAS
C8
CAS
C9
WE
B8
CKE
B7
CK
A5
CK
A6
CS0
B3
CS1
C4
CS2
V9
CS3
W8
D0
K1
D1
L1
D2
M1
D3
L3
D4
N1
D5
M3
D6
N2
D7
P1
D8
K3
D9
J3
D10
J1
D11
H3
D12
H2
D13
G2
D14
H1
D15
F2
D16
P3
D17
P2
D18
R3
D19
R2
D20
T2
D21
U2
D22
T3
D23
U3
D24
C1
D25
C3
D26
E2
D27
D3
D28
D2
D29
F3
D30
C2
DQM0
C6
DQM1
A3
DQM2
B4
DQM3
C5
DQS0
B6
DQS1
C7
DQS2
A4
DQS3
B5
D31
E3
SSTLN
C1
V2
SSTLN
C2
B2
VREF2
N3
MSC7116DDR INTERFACE
U15A
MSC7116
MSC7116DDR INTERFACE
U15A
MSC7116
45
RN10D
24.RN10D
24.
18
RN28A
24.RN28A
24.
45
RN24D
22RN24D
22
C12
0.1uF
C12
0.1uF3
6RN30C
24.RN30C
24.
C122
0.1uF
C122
0.1uF
45
RN14D
22RN14D
22
36
RN25C
22RN25C
22
DQ0
2
DQ1
4
DQ2
5
DQ3
7
DQ4
8
DQ5
10
DQ6
11
DQ7
13
DQ8
54
DQ9
56
DQ10
57
DQ11
59
DQ12
60
DQ13
62
DQ14
63
DQ15
65
A0
29
A1
30
A2
31
A3
32
A4
35
A5
36
A6
37
A7
38
A8
39
A9
40
A10/A
P28
A11
41
BA0
26
BA1
27
CAS#
22WE#
21
RAS#
23
CS#
24
LDQS
16
UDQS
51
LDM
20
UDM
47
NC1
14
NC2/A
1317
NC2
25
NC/A12
42
NC3
43
NC4
53
DNU1
19
DNU2
50
CKE
44
CK
45
CK#
46
DDR_DRAM
U11A
MT46V
8M16
DDR_DRAM
U11A
MT46V
8M16
C130
0.1uF
C130
0.1uF
C25
1uF C25
1uF
C22
0.01uF
C22
0.01uF
27
RN6B
24.RN6B
24.
45
RN22D
22RN22D
22
C123
1uF C123
1uF
C28
0.01uF
C28
0.01uF
27
RN17B
22RN17B
22
R95
22R1
R95
22R1
C27
1uF C27
1uF
C18
0.01uF
C18
0.01uF
C114
1uF C114
1uF
C126
0.01uF
C126
0.01uF
45
RN6D
24.RN6D
24.
45
RN27D
24.RN27D
24.
R90
22R1
R90
22R1
VDD1
1
VDD2
18
VDD3
33
VDDQ1
3
VDDQ2
9
VDDQ3
15
VDDQ4
55
VDDQ5
61
VREF
49
VSS1
34
VSS2
48
VSS3
66
VSSQ1
6
VSSQ2
12
VSSQ4
58VSSQ3
52
VSSQ5
64
DDR_DRAM POWER
U20B
MT46V
8M16
DDR_DRAM POWER
U20B
MT46V
8M16
27
RN23B
22RN23B
22
C16
0.1uF
C16
0.1uF
C106
0.1uF
C106
0.1uF
36
RN27C
24.RN27C
24.
27
RN31B
24.RN31B
24.
45
RN23D
22RN23D
22
36
RN31C
24.RN31C
24.
R96
22R1
R96
22R1
R80
22R1
R80
22R1
45
RN31D
24.RN31D
24.
R19
100ohmR19
100ohm
C121
0.1uF
C121
0.1uF
C127
0.1uF
C127
0.1uF
R87
22R1
R87
22R1
R29
22R1
R29
22R1
C29
0.1uF
C29
0.1uF
18
RN13A
22RN13A
22R31
22R1
R31
22R1
45
RN4D
24.RN4D
24.
C111
0.1uF
C111
0.1uF
C13
0.1uF
C13
0.1uF
C113
0.1uF
C113
0.1uF
C19
0.1uF
C19
0.1uF
27
RN5B
24.RN5B
24.
36
RN13C
22RN13C
22
45
RN21D
22RN21D
22
36
RN4C
24.RN4C
24.
C21
0.1uF
C21
0.1uF
27
RN15B
22RN15B
22
R30
22R1
R30
22R1
MSC711xEVM Reference Manual, Rev. 0
Freescale Semiconductor A-3
A.1.3 StarLite HDI 55
44
33
22
11
DD
CC
BB
AA
HD15
HD11
HD10
HD14
HD12
HD13
HD8
HD9
HD7
HD3
HD4
HD2
HD5
HD6
HD0
HD1
HA0
HA2
HA1
nB_H
DICS1
HRW
nHACK
HA1
HD13
HD14
HD15
HD10
HD5
HD12
HD9
HD4
HD6
HD3
HD1
HD7
HD2
HD0
HD11
HD8
nB_H
DICS1
nB_H
DICS2
HA0
nHACK
HA2
nB_H
DICS2
nHREQ
HDS
HDDS
nHREQ
A1
A2
WP
A0
GND
3V3
3V3
GNDGND
3V3
GND
3V3
GND
3V3
3V3
GND
3V3
GND
3V3
GND
3V3
GND
3V3
GND
3V3
GND
GND
GNDGND
BADD[28:30]
4,5,6,10,11
HRW
5,13
HDDS
5,13
HDS
5,13
nHACK
5,13
nB_H
DICS2
5nB
_HDICS1
5
nHRESET
nPORST
nHREQ
I2CSCL
I2CSDA
Title
Size
Docum
ent Num
berRev
Date:
Sheet
of
PROTO
MSC711xE
VM: 711x H
DI
Freescale Sem
iconductor Israel Ltd.
Metrow
erks Israel
A3
411
Wednesday, A
pril 06, 2005
Title
Size
Docum
ent Num
berRev
Date:
Sheet
of
PROTO
MSC711xE
VM: 711x H
DI
Freescale Sem
iconductor Israel Ltd.
Metrow
erks Israel
A3
411
Wednesday, A
pril 06, 2005
Title
Size
Docum
ent Num
berRev
Date:
Sheet
of
PROTO
MSC711xE
VM: 711x H
DI
Freescale Sem
iconductor Israel Ltd.
Metrow
erks Israel
A3
411
Wednesday, A
pril 06, 2005
HDI HEADER CONNECTOR
NOTE:nPORST and nHRESET should be O.D. signals
SINGLE STROBE MODE
ACTIVE LOW POLARITY
(*) Default EEPROM
address is '000'
WP='0'
SCL
SDA
I2C EEPROM
R61
1KR61
1K
R14
10KOPTIO
NR14
10KOPTIO
NTP
15TP
15
TP14
TP14
R130
150
R130
150
A0
1
A1
2
A2
3
GND
4
WC
7
SDA
5
SCL
6
VCC 8
U6
M24256-B
VBN
U6
M24256-B
VBN
R11
10KOPTIO
NR11
10KOPTIO
N
LD9
LED_G
REEN
LD9
LED_G
REEN
R10
1KR10
1KR15
1KR15
1K
98
10
U7C
74LCX125
U7C
74LCX125
R98
1KR98
1K
12345 6 7 8
DIPSOCKET
Y2
Socket 8P
DIP
DIPSOCKET
Y2
Socket 8P
DIPR
1380
R138
0
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
P10
36P SMD HEADER
P10
36P SMD HEADER
R140
10KR140
10K
R10510
R10510
R38
10KOPTIO
NR38
10KOPTIO
N
R137
10KR137
10K
23
1
U7A
74LCX125
U7A
74LCX125
R59
10KR59
10K
1211
13
U7D
74LCX125
U7D
74LCX125
LD4LE
D_R
ED
LD4LE
D_R
ED
R139
0R139
0
R8
1KR8
1K
R7
10KOPTIO
NR7
10KOPTIO
NR12
10KOPTIO
NR12
10KOPTIO
N
56
4
U7B
74LCX125
U7B
74LCX125
R94
10KOPTIO
NR94
10KOPTIO
N
R58
10KR58
10K
R54
10KR54
10K
C144
0.1uF
C144
0.1uF
HD0
A14
HD1
A13
HD2
B13
HD3
C12
HD4
A12
HD5
B12
HD6
A11
HD7
A10
HD8
B11
HD9
C11
HD10
A9
HD11
B10
HD12
A8
HD13
C10
HD14
B9
HD15
A7
HA0
K18
HA1
H20
HA2
H19
HA3
J18
NC0
G20
NC1
G19
NC2
H18
NC3
F20
NC4
F19
NC5
G18
NC6
E19
NC7
E20
NC8
F18
NC9
E18
NC10
D19
NC11
D20
NC12
D18
NC13
C19
NC14
C20
NC15
B20
NC16
C18
NC17
B19
NC18
A20
NC19
C17
HCS1/H
CS1
L19
HCS2/H
CS2
L18
HRW/HRW / H
RD/HRD
L20
HDDS
K19
HDSP / H
TRQ/HTRQ / H
REQ/HREQ
J20
HRRQ/HRRQ / H
ACK/HACK
J19
HDS/HDS / H
WR/HWR
K20
NC20
B18
NC21
A19
NC22
C16
NC23
B17
NC25
A18
NC24
C15
NC26
B15
NC27
A16
NC28
B14
NC29
C13
MSC7116
Host Data
Interface
U15C
MSC7116
MSC7116
Host Data
Interface
U15C
MSC7116
R9
1KR9
1K
R144
150
R144
150
MSC711xEVM Reference Manual, Rev. 0
A-4 Freescale Semiconductor
MSC711xEVM Schematics
A.1.4 StarLite System and PIO 55
44
33
22
11
DD
CC
BB
AA
EVENT2
EVENT3
TDM1_TFS
TDM1_TD
ETH
_TXD0
ETX
D3_T2R
CLK
ETX
ER_T2R
D
UART_TX
DUART_R
XD
EVENT2
TDM0_R
FSTD
M0_TC
LKTD
M0_TFS
TDM1_R
D
TDM1_R
CLK
TDM1_R
FS
TMS
ETH
_TXCLK
ETH
_TXD1
ETH
_TXD0
EVENT1
ETH
_TXD2
ETH
_TXD3
ETH
_TXER
ETH
_RXD3
ETH
_RXD2
ETH
_TXEN
ETH
_RXD0
ETH
_RXCLK
ETH
_RXER
ETH
_RXD1
ETH
_RXDV
ETH
_CRS
ETH
_COL
TRSTb
MDC_H
8
TDI
DBREQ
TDM1_TC
LK
nPORST
nSC_N
MI
nHRESET
TDM0_R
CLK
TDM0_R
FSTD
M0_R
DTD
M0_TC
LKTD
M0_TFS
TDM0_TD
MDIO
TDM1_TFS
TDM1_R
CLK
TDM1_R
FSTD
M1_R
D
TDM1_TD
TDM1_TC
LK
EVENT2
EVENT4
EVENT3
TCK
EVENT1
ETH
_TXER
EVENT4
DBREQ
EVENT4
TEST0
EVENT3
TDM0_R
CLK
ETH
_TXEN
nSC_N
MI
ETH
_TXD1
I2CSCL
I2CSDA
EVENT0
DBREQ
TPSEL
UART_TX
D
UART_R
XD
RXD1
TXD1
nRS232_E
N
3V3
3V3
GND
3V3
3V3
GND
3V3
GND 3V3
GND
3V3
3V3
GND
3V3
3V3
3V3
3V3
3V3
3V3
GND
GND
GND
3V3
3V3
GND
Chassis
3V3
GND
GND
GND
GND
3V3
GND
TDM0_R
D
TDM0_TD
TDM1_R
CLK
TDM1_TC
LK
TDM1_R
FS
TDM1_TFS
TDM1_R
D
TDM1_TD
ETH
_RXER
ETH
_RXDV
ETH
_RXD0
ETH
_RXD1
ETH
_COL
ETH
_CRS
MDC_H
8MDIO
nPORST
nHRESET
nSC_N
MI
EVENT0
EVENT2
EVENT3
EVENT4
DBREQ
TCK
TDI
TMS
TRSTb
ETH
_TXD3
ETH
_TXD2
ETH
_TXER
ETH
_RXCLK
ETH
_RXD2
ETH
_RXD3
TDM0_R
CLK
TDM0_TC
LKTD
M0_TFS
EVENT1
TDM0_R
FS
SW_IN
0SW_IN
1SW_IN
2SW_IN
3
LD_O
UT3
LD_O
UT2
LD_O
UT1
LD_O
UT0
SW_IN
0SW_IN
1SW_IN
2SW_IN
3
TDO
ETH
_TXCLK
ETH
_TXEN
ETH
_TXD1
ETH
_TXD0 LD_O
UT0
LD_O
UT1
LD_O
UT2
LD_O
UT3
I2CSDA
I2CSCL
Title
Size
Docum
ent Num
berRev
Date:
Sheet
of
PROTO
MSC711xE
VM: S
YSTEM & PIO
Freescale Sem
iconductor Israel Ltd.
Metrow
erks Israel
A3
511
Wednesday, A
pril 06, 2005
Title
Size
Docum
ent Num
berRev
Date:
Sheet
of
PROTO
MSC711xE
VM: S
YSTEM & PIO
Freescale Sem
iconductor Israel Ltd.
Metrow
erks Israel
A3
511
Wednesday, A
pril 06, 2005
Title
Size
Docum
ent Num
berRev
Date:
Sheet
of
PROTO
MSC711xE
VM: S
YSTEM & PIO
Freescale Sem
iconductor Israel Ltd.
Metrow
erks Israel
A3
511
Wednesday, A
pril 06, 2005
CODEC Clock Source
Clock
Source
Debug Signals
CLKO
Power-On Configuration Signals
8.192MHz-3V3-50ppm
R112150
R112150
R68
1K5
R68
1K5
10
987654321
RN19
10K
RN19
10K
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
P5
36P SMD HEADER
P5
36P SMD HEADER
C129
0.1uF
C129
0.1uF
R49
10KR49
10K
R69
1K5
R69
1K5
R56
10KR56
10K
C9
0.1uF
C9
0.1uF
10
987654321
RN20
10K
RN20
10K
R119
0OPTIO
N
R119
0OPTIO
N
10
987654321
RN33
10K
RN33
10K
LD14
LED_G
REEN
LD14
LED_G
REEN
C133
0.1uF
C133
0.1uF
C78
0.1uF
C78
0.1uF
R115150
R115150
R65
22R1
R65
22R1
LD17LED_RED
LD17LED_RED
C128
0.1uF
C128
0.1uF
R43
0 R43
0
R71
1K5
R71
1K5
R42
4.7KR42
4.7K
R50
10KR50
10K
R34
22R1
R34
22R1
VCC 4OUT
3
GND
2
EN
1
U12
OSC_S
MT-8_192M
Hz U12
OSC_S
MT-8_192M
Hz
R63
1KR63
1K
VCC 4OUT
3
GND
2
EN
1
U24
OSC_T.H
_20.00 MHz
U24
OSC_T.H
_20.00 MHz
T0R
CK / IR
Q4
Y10
T0R
FS / IR
Q5
W11
T0R
DY11
T0TCK / IR
Q6
V12
T0TFS / IR
Q7
W12
T0TD
Y12
T1R
CK / IR
Q0
Y13
T1R
FS / IR
Q1
V13
T1R
D / IR
Q8
W13
T1TCK / IR
Q9
Y14
T1TFS / IR
Q10
W14
T1TD / IR
Q11
V14
TXD0 / IR
Q19
Y17
TXD1 / IR
Q20
W17
RXD0 / IR
Q22
V17
RXD1 / IR
Q21
Y18
TXCLK
/ IRQ23
W18
TX_E
N / IR
Q24
V18
RX_D
V / IR
Q25
Y20
RX_E
R / IR
Q26
W19
COL
U18
CRS
V19
MDC / H
8BIT
W20
MDIO
T18
TXD3 / T
2RCK / IR
Q16
Y15
TXD2 / T
2RFS
W15
TX_E
R / T
2RD / IR
Q17
V15
RXCLK
/ T2TCK
Y16
RXD3 / T
2TFS / IR
Q18
W16
RXD2 / T
2TD
V16
TCK
U19
TDI
V20
TDO
R18
TMS
T19
TRST
U20
J_DBREQ / E
E0
R19
SDA / IR
Q15
M18
SCL / IR
Q14
N19
URXD / IR
Q2
M20
UTXD / IR
Q3
M19
PORESET
P18
HRESET
T20
TEST0
R20
TPSEL(T
EST1)
P19
EVNT0
V10
EVNT1 / IR
Q13 / C
LK0
W9
EVNT2 / B
M0
W10
EVNT3 / B
M1
Y9
EVNT4 / IR
Q12 / S
WTE
V11
NMI
Y8
SMII_S
YNC
B16
SMII_S
YNC_IN
C14
SMII_T
XD
A17
CLK
INN18
MSC7116
SYSTEM & I/O INTERFACE
TDM0TDM1
MII/TDM2
UARTI2C
EONCE
U15B
MSC7116
MSC7116
SYSTEM & I/O INTERFACE
TDM0TDM1
MII/TDM2
UARTI2C
EONCE
U15B
MSC7116
R37
22R1
R37
22R1
R150
1K5
R150
1K5
R60
10KR60
10K
R66
22R1
R66
22R1
R143
1K5
R143
1K5
C1+
2
C1-
4
C2+
5
C2-
6
T1IN
11
R1O
UT
9
EN
1
FORCEON
12
V+
3
V-
7
T1O
UT
13
R1IN
8
IVALID
10
FORCEOFF
16VCC
15G ND
14
ICL_3221
U10
ICL3221
ICL_3221
U10
ICL3221
R72
10KR72
10K
1234
8765
SW1
SW DIP-4/S
MSW1
SW DIP-4/S
M
R73
22R1
R73
22R1
LD16
LED_G
REEN
LD16
LED_G
REEN
R21
10KR21
10K
R74
0R74
0
R35
22R1
R35
22R1
1234
8765
SW3
SW DIP-4/S
MSW3
SW DIP-4/S
M
R36
22R1
R36
22R1
R104150
R104150
R57
0R57
0
R148
1K5
R148
1K5
R70
1K5
R70
1K5
R67
22R1
R67
22R1
R149
1K5
R149
1K5
5 9 4 8 3 7 2 6 1
10 11
P4
P4
R81150
R81150
R5310kR5310k
R33
22R1
R33
22R1
R41
4.7KR41
4.7K
LD15LED_RED
LD15LED_RED
C132
0.1uF
C132
0.1uF
R118
0OPTIO
N
R118
0OPTIO
N
12345 6 7 8
DIPSOCKET
Y1
Socket 8P
DIP
DIPSOCKET
Y1
Socket 8P
DIP
R51
10kR51
10k
R11710k
OPTIO
N
R11710k
OPTIO
N
R521K
OPTIO
NR521K
OPTIO
N
13579
246810
P6
CON10A
P
P6
CON10A
P
C91
0.1uF
C91
0.1uF
10
987654321
RN18
10K
RN18
10K
R62
10kR62
10kR6410kR6410k
TP23
TP23
R1221K
R1221K
R781K
R781K
MSC711xEVM Reference Manual, Rev. 0
Freescale Semiconductor A-5
A.1.5 StarLite Power 55
44
33
22
11
DD
CC
BB
AA
2V5
3V3
GND
1V2S
L
GND
2V5
GND
3V3
1V2S
L
1V2S
L
GND
Title
Size
Docum
ent Num
berRev
Date:
Sheet
of
PROTO
MSC711xE
VM: 711x P
OWER
Freescale Sem
iconductor Israel Ltd.
Metrow
erks Israel
A3
611
Wednesday, A
pril 06, 2005
Title
Size
Docum
ent Num
berRev
Date:
Sheet
of
PROTO
MSC711xE
VM: 711x P
OWER
Freescale Sem
iconductor Israel Ltd.
Metrow
erks Israel
A3
611
Wednesday, A
pril 06, 2005
Title
Size
Docum
ent Num
berRev
Date:
Sheet
of
PROTO
MSC711xE
VM: 711x P
OWER
Freescale Sem
iconductor Israel Ltd.
Metrow
erks Israel
A3
611
Wednesday, A
pril 06, 2005
C88
0.01uF
C88
0.01uF
C81
0.1uF
C81
0.1uF
C66
0.01uF
C66
0.01uF
C92
0.1uF
C92
0.1uF
+ C34
47uF
+ C34
47uF
C82
0.01uF
C82
0.01uF
+ C46
47uF
+ C46
47uF
C65
0.1uF
C65
0.1uF
C37
0.1uF
C37
0.1uF
C68
0.01uF
C68
0.01uF
C47
0.1uF
C47
0.1uF
PW R12_0F4PW R12_1F5
PW R12_2F6
PW R12_3E6
PW R12_4E7
PW R12_5E8PW R12_6E9
PW R12_7K4
PW R12_8L4
PW R12_9U5
PW R12_10U6PW R12_11T6
PW R12_12U7
PW R12_13U8
PW R12_14U9
PWR25_0
B1
PWR25_1
D1
PWR25_2
F1
PWR25_3
T1
PWR25_4
V1
PWR25_5
Y1
PWR25_6
W2
PWR25_13
E4
PWR25_14
E5
PWR25_15
E10
PWR25_16
F10
PWR25_17
F11
PWR25_18
G4
PWR25_19
G5
PWR25_20
H4
PWR25_21
H5
PWR25_22
J2
GND0
A1
GND1
A2
GND2
A15
GND3
D4
GND4
E1
VDDPLLP20
VSSPLLN20
PW R12_15T9PW R12_16U10
PW R12_17U11
PW R12_26R17
PW R12_27P17
PW R12_28N16
PW R12_29N17
PW R12_30M 16PW R12_31M 17
PW R12_18U12
PW R12_19U13
PW R12_20U14PW R12_21U15
PW R12_22U16
PW R12_23U17
PW R12_24T16
PW R12_25T17
PW R12_32L17
PW R12_33K17
PW R12_34J17
PW R12_35H17PW R12_36G17
PW R12_37F16
PW R12_38F17
PW R12_39E16
PW R12_40E17PW R12_41D17
PWR25_7
D5
PWR25_8
D6
PWR25_9
D7
PWR25_10
D8
PWR25_11
D9
PWR25_12
D10
PWR25_23
J4
PWR25_24
J5
PWR25_25
J6
PWR25_26
K5
PWR25_27
L5
PWR25_28
M2
PWR25_29
M4
PWR25_30
M5
PWR25_31
N4
PWR25_32
N5
PWR25_33
N6
PWR25_34
P4
PWR25_35
P5
PWR25_36
P6
PWR25_37
R4
PWR25_38
R5
PWR25_39
R6
PWR25_40
R8
PWR25_41
R10
PWR25_42
T4
PWR25_43
T5
PWR25_44
T7
PWR25_45
T8
PWR25_46
T10
PWR25_47
T11
PWR25_48
U4
GND5
F7
GND6
F8
GND7
F9
GND8
F12
GND9
F13
GND10
F14
GND11
G1
GND12
G6
GND13
G7
GND14
G8
GND15
G9
GND16
G10
GND17
G11
GND18
G12
GND19
G13
GND20
G14
GND21
H6
GND22
H7
GND23
H8
GND24
H9
GND25
H10
GND26
H11
GND27
H12
GND28
H13
GND29
H14
GND30
J7
GND31
J8
GND32
J9
GND33
J10
GND34
J11
GND35
J12
GND36
J13
GND37
J14
GND38
J15
GND39
K2
GND40
K6
GND41
K7
GND42
K8
GND43
K9
GND44
K10
GND45
K11
GND46
K12
GND47
K13
GND48
K14
GND49
L2
GND50
L6
GND51
L7
GND52
L8
GND53
L9
GND54
L10
GND55
L11
GND56
L12
GND57
L13
GND58
M6
GND59
M7
GND60
M8
GND61
M9
GND62
M10
GND63
M11
GND64
M12
GND65
M13
GND66
M14
GND67
M15
GND68
N7
GND69
N8
GND70
N9
GND71
N10
GND72
N11
GND73
N12
GND74
N13
GND75
N14
GND76
P7
GND77
P8
GND78
P9
GND79
P10
GND80
P11
GND81
P12
GND82
P13
GND83
P14
GND84
R1
GND85
R7
GND86
R9
GND87
R11
GND88
R12
G ND89R14
GND90U1
GND91W 1 GND92Y2
GND93Y19
PWR33_0
D11
PWR33_1
D12
PWR33_2
D13
PWR33_3
D14
PWR33_4
D15
PWR33_5
D16
PWR33_6
E11
PWR33_7
E12
PWR33_8
E13
PWR33_9
E14
PWR33_10
E15
PWR33_11
F15
PWR33_12
G15
PWR33_13
G16
PWR33_14
H15
PWR33_15
H16
PWR33_16
J16
PWR33_17
K15
PWR33_18
K16
PWR33_19
L14
PWR33_20
L15
PWR33_21
L16
PWR33_22
N15
PWR33_23
P15
PWR33_24
P16
PWR33_25
R13
PWR33_26
R15
PWR33_27
R16
PWR33_28
T12
PWR33_29
T13
PWR33_30
T14
PWR33_31
T15
G ND94G3
MSC7116
POWER
U15D
MSC7116
MSC7116
POWER
U15D
MSC7116
C98
0.01uF
C98
0.01uF
C96
0.01uF
C96
0.01uF
C86
0.1uF
C86
0.1uF
C83
0.1uF
C83
0.1uF
C62
0.01uF
C62
0.01uF
C94
0.01uF
C94
0.01uF
C41
0.01uF
C41
0.01uF
+ C59
10uF
+ C59
10uF
C79
0.1uF
C79
0.1uF
C32
0.1uF
C32
0.1uF
+ C51
10uF
+ C51
10uF
C70
0.1uF
C70
0.1uF
C64
0.1uF
C64
0.1uF
C90
0.1uF
C90
0.1uF
C31
0.1uF
C31
0.1uF
C36
0.1uF
C36
0.1uF
C80
0.01uF
C80
0.01uF
C63
0.01uF
C63
0.01uF
C33
0.01uF
C33
0.01uF
C67
0.1uF
C67
0.1uF
C40
0.1uF
C40
0.1uF
C93
0.01uF
C93
0.01uF
C97
0.1uF
C97
0.1uF
+ C84
10uF
+ C84
10uF
C44
0.01uF
C44
0.01uF
C77
0.01uF
C77
0.01uF
C95
0.1uF
C95
0.1uF
C85
0.01uF
C85
0.01uF
+ C45
47uF
+ C45
47uF
C71
0.01uF
C71
0.01uF
C61
0.01uF
C61
0.01uF
C38
0.01uF
C38
0.01uF
C99
0.01uF
C99
0.01uF
+C48
10uF
+C48
10uF
C100
0.1uF
C100
0.1uF
R3920
R3920
C87
0.1uF
C87
0.1uF
MSC711xEVM Reference Manual, Rev. 0
A-6 Freescale Semiconductor
MSC711xEVM Schematics
A.1.6 Ethernet 55
44
33
22
11
DD
CC
BB
AA
LINK
DUPLE
XSPEED
LINK
SPEED
DUPLE
XNWAY
POWER_D
OWN
POWER_D
OWN
3V3
3V3
GND
3V3
GND
GND
3V3
GND
3V3
AGND
AGND
AGND
AGND
Chassis
Chassis
AVDD
AVDD
GND
GND
3V3
GND
3V3
3V3
GNDGND
GND
3V3
GND
Chassis
GND
Chassis
GND
AVDD
3V3
3V3
GND
AVDD
Chassis
GNDGND
AGND
AGND
AGND
3V3
ETH
_TXD1
ETH
_TXD2
ETH
_TXD3
ETH
_TXD0
ETH
_CRS
MDIO
MDC_H
8
ETH
_RXD3
ETH
_RXD0
ETH
_RXD1
ETH
_RXD2
ETH
_TXER
ETH
_TXEN
ETH
_RXER
ETH
_RXDV
ETH
_RXCLK
ETH
_TXCLK
nPORST
ETH
_COL
Title
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PROTO
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VM: E
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PROTO
MSC711xE
VM: E
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Title
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PROTO
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VM: E
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* Analog and Digital ground planes should be connected at one single point.
100Mbps
* MSC711x FAST ETHERNET: PHY ADDRESS 00001
FDXTx/Rx
Fast Ethernet on MSC711x PIO
PHY ISOLATE
LD2
LED_GREEN
LD2
LED_GREEN
C74
0.1uF
C74
0.1uF
C138
0.1uF
C138
0.1uF
C69
0.1uF
C69
0.1uF
R15575
R15575
R23
1K5
R23
1K5
R142
78.7R142
78.7
12 356 71011 12
1415 16
89
413
* **
***
**
**
* *
U4
PE_68515L
* **
***
**
**
* *
U4
PE_68515L
R1
150R1
150
C143
0.01UF-2K
VC143
0.01UF-2K
V
R141
49.9R141
49.9
C155
0.1uFC155
0.1uF
R129
10KR129
10K
R2
150R2
150
NC1 4
X2
3
NC0
2
X1
1
U5
CRYSTA
L_SMT-25M
Hz
U5
CRYSTA
L_SMT-25M
Hz
R24
10KR24
10K
C139
0.1uF
C139
0.1uF
C137
0.1uF
C137
0.1uF
R16075
R16075
C163
0.01UF-2K
VC163
0.01UF-2K
V
R123
22R1
R123
22R1
36
RN2C
22RN2C
22
MDIO
1
MDC
2
RXD3/P
HYAD1
3
RXD2/P
HYAD2
4
RXD1/P
HYAD3
5
RXD0/P
HYAD4
6
RXDV/BYPOSC
9RXC
10
RXER/IS
O11
TXER
14
TXC
15
TXEN
16
TXD0
17TXD1
18TXD2
19TXD3
20
COL/S
YMB
21
CRS/RPTR
22
G ND18
GND212
GND323
GNDRX35
GNDPLL36
GNDTXC39
GNDTX43
VDD17
VDD224
VCC13
VCCOSC47
VCCRX31
VCCTX42
INT#/P
HYAD0
25
LED0/LIN
K26
LED1/S
PD100
27LE
D2/D
UPLE
X28
LED3/N
WAYEN
29
PD#
30
RX+
33
RX-
32
SD/FXEN
34REXT
37
TX-
40
TX+
41
XO
45XI
46
RESET#
48
G NDOSC44
VDDPLL38
U8VIA_V
T6103
U8VIA_V
T6103
LD1
LED_GREEN
LD1
LED_GREEN
45
RN2D
22RN2D
22
45
RN1D
22RN1D
22
C145
0.1uF
C145
0.1uF
R133
6.49KR133
6.49K
C168
0.01UF-2K
VC168
0.01UF-2K
V
R127
10KR127
10K
L3FE
RRITE
120ohm/2000m
AL3
FERRITE
120ohm/2000m
A
R15675
R15675
C76
0.1uF
C76
0.1uF
R201K
OPTIO
N
R201K
OPTIO
N
R131
10KOPTIO
N
R131
10KOPTIO
N
R4
0R4
0
R3
150R3
150C147
0.1uF
C147
0.1uF
R1610kR1610k
BLU
E8
ORANGE
7
BLA
CK
6
RED
5
GREEN
4
YELLO
W3
BROWN
2
GRAY
1
Chassis19
Chassis210
Chassis311
Chassis412
P2
RJ45 - M
OLE
X / E
.C.COM
P2
RJ45 - M
OLE
X / E
.C.COM
C151
0.1uFC151
0.1uF
LD3
LED_RED
LD3
LED_RED
C146
0.1uF
C146
0.1uF
R16175
R16175
R128
10KR128
10K
C148
0.1uF
C148
0.1uF
C134
0.1uF
C134
0.1uF
C149
22pf
C149
22pf
R132
10KR132
10K
18
RN1A
22RN1A
22
C154
0.1uFC154
0.1uF
C158
0.1uFC158
0.1uF
12 +C142
10uF+
C142
10uF
C60
0.1uF
C60
0.1uF
27
RN1B
22RN1B
22
12
JP3
JP3
18
RN2A
22RN2A
22
R124
22R1
R124
22R1
C150
22pf
C150
22pf
L5 FERRITE
120ohm/2000m
A
L5 FERRITE
120ohm/2000m
A
L4 FERRITE
120ohm/2000m
A
L4 FERRITE
120ohm/2000m
A
R146
78.7R146
78.7 R145
49.9R145
49.9
36
RN1C
22RN1C
22
27
RN2B
22RN2B
22
R126
10KR126
10K
MSC711xEVM Reference Manual, Rev. 0
Freescale Semiconductor A-7
A.1.7 CODEC 55
44
33
22
11
DD
CC
BB
AA
AGND1
AGND1
AGND1
AGND1
AGND1
3V3
3V3A
3V3A
GND
AGND1
3V3
GND
3V3
GND
5V
5V
AGND1AGND1
AGND1
5VA
AGND1
GND
GND
GND
GND
AGND1
AGND1
EVENT1
TDM0_R
FS
TDM0_R
CLK
nPORST
TDM0_TD
TDM0_R
D
Title
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Date:
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PROTO
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VM: C
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????
????
C116
2200pf
C116
2200pf
12 34
LEFT
RIGHT
P8PHONOJACK STE
REO-15_0
LEFT
RIGHT
P8PHONOJACK STE
REO-15_0
R107
22R1
R107
22R1
+C109
4.7uF+
C109
4.7uF
C110
22pfOPTIO
NC110
22pfOPTIO
N
C72
0.1uFC72
0.1uF
R100
220
R100
220
R10810K
R10810K
+
C112
22uF +
C112
22uF
R45
0R45
0
12 34
LEFT
RIGHT
P7
PHONOJACK STE
REO-15_0
LEFT
RIGHT
P7
PHONOJACK STE
REO-15_0
R28
10KR28
10K
C103
0.1uFC103
0.1uF
+ C58
10uF
+ C58
10uF
R9910K
R9910K
C26
0.1uF
C26
0.1uF
+ C101
10uF
+ C101
10uFC43
1uFC43
1uF
C105
22pfOPTIO
NC105
22pfOPTIO
N
R26
10KOPTIO
N
R26
10KOPTIO
N
R113560
R113560
C73
0.1uFC73
0.1uF
R27
10KOPTIO
N
R27
10KOPTIO
N
MCLK
11
LRCK
10
SCLK
12
STDO
8
STDI
9
DEM0
6
DEM1
7
PWDA
14PWAD
13
AINL
3
AINR
2
VCOM
1
AOUTL
15
AOUTR
16
VDD5
VSS4
U19
AKM-AK4550
U19
AKM-AK4550
+
C108
22uF +
C108
22uF
12
L1
BEAD FE
RRITE
L1
BEAD FE
RRITE
C115
2200pf
C115
2200pf
+
C118
4.7uF +
C118
4.7uF
C104
1uFC104
1uFC49
0.1uFC49
0.1uF
+
C119
4.7uF +
C119
4.7uF
R25
10KR25
10K
12
L2
BEAD FE
RRITE
L2
BEAD FE
RRITE
R110
470
R110
470
R109220
R109220
R111
470
R111
470
R114560
R114560
MSC711xEVM Reference Manual, Rev. 0
A-8 Freescale Semiconductor
MSC711xEVM Schematics
A.1.8 JTAG_Master 55
44
33
22
11
DD
CC
BB
AA
nJTAG_R
DY
PP_A
D0
PP_A
D6
PP_A
D5
PP_A
D4
PP_A
D3
PP_A
D2
PP_A
D1
PP_A
D7
PP_A
D0
PP_A
D1
PP_A
D2
PP_A
D3
PP_A
D4
GND
GND
GND
GND
GND GND
GND
3V3
3V3
3V3
3V3
3V3
3V3
PP_B
USY
nHRESET
nJTAG_R
ST
JTAG_A
D1
JTAG_A
D0
nJTAG_D
STR
JTAG_C
LK
PP_A
D[7..0]
JTAG_A
D2
nJTAG_R
DY
nJTAG_TO
E
nJTAG_W
E
JTAG_TM
SJTA
G_TD
I
nJTAG_TR
ST
JTAG_TD
O
TRSTb
JTAG_TC
K
TCK
TDO
TDI
TMS
Title
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Title
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Date:
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PROTO
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Title
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PROTO
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VM: JT
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JTAG_EXTERNAL_I/F
DECOUPLING
SPP_TMSSPP_TCKSPP_TDI
* R203 - R208, U22, will be assembled in SPP Mode Only.
SPP_TRSTbSPP_TDO
JTAG/EOnCE Connector
STARLITE_JT
AG_I/F
SPP_TCKSPP_TMSSPP_TDISPP_TDOSPP_TRSTb
JTAG_MASTER
C5
0.1uF
C5
0.1uF
R147
1K R147
1K
R154
0R154
0
TOE
13
TMS
17
TCK
18
RST
14
D4
8
D0
3
VCC19
GND7
D1
4
TDI
15
D3
6D2
5
TRST
16
D5
9
D6
10
D7
11
A0
24
A1
23
A2
22
STRB
1
R/W
2
RDY
21
TDO
20
CLK
12
U21
SN74LVT8980ADW R
OPTIO
N
U21
SN74LVT8980ADW R
OPTIO
N
R152
0R152
0
R153
0R153
0
R101
0R101
0
R83
0R83
0
R116
0R116
0
C140
0.1uF
C140
0.1uF4
125
3
VCC
GND
OE
U22N
L17SZ126D
F
VCC
GND
OE
U22N
L17SZ126D
FR157
0R157
0
R84
0 R84
0
C157
0.1uF
OPTIO
N C157
0.1uF
OPTIO
N
C141
0.01uFC141
0.01uF
13579
246810
13 1114 12
GND
KEYTMSNCTRST
TDITDOTCKNCRSTVDDNC
GNDGND
P9C
ON14A
P
GND
KEYTMSNCTRST
TDITDOTCKNCRSTVDDNC
GNDGND
P9C
ON14A
P
R151
0R151
0
R85
10 R85
10
MSC711xEVM Reference Manual, Rev. 0
Freescale Semiconductor A-9
A.1.9 Parallel Port 55
44
33
22
11
DD
CC
BB
AA
DB2
PP_A
D[7..0]
F_DB5
DB0
DB1
DB6
DB7
F_DB6
DB3
DB4
DB5
DB6
nEXT_C
ON
F_DB7
PP_A
D6
PP_A
D7
F_ASTR
b
F_RSTb
F_WEb
F_DSTR
b
F_INb
PP_IS
PTD
IPP_IS
PTM
SPP_IS
PTD
OPP_IS
PTC
K
Write-
DB7
DB[0..7]
F_DB4
F_DB2
F_DB1
F_DB0
Wait-
Dstrobe-
DB1
nPP_IN
DB4
Reset-
DB5
Astrobe-
DB0
Select
IRQ-
DB2
DB3
IN-
PP_A
D5
PP_A
D1
PP_A
D6
PP_A
D2
PP_A
D7
PP_A
D3
PP_A
D4
PP_A
D0
F_SELE
CT
F_BUSY
F_INTb
nSPP_LE
DnE
PP_LE
D
F_DB3
JTAG_C
LK
F_DB7
F_DB6
F_DB5
F_DB4
F_DB3
F_DB2
F_DB1
F_DB0
F_DB[0..7]
PP_B
USY
PP_D
IR
PWR_1V
2_EN
nPP_I2C
_EN_S
W
PP_A
D0
nCPU_I2C
_LED
PP_A
D1
nPP_I2C
_LED
PP_A
D2
PWR_1V
2_EN
PP_A
D3
PP_A
D4
PP_A
D5
GND
GND
GND
GND
GND
GND GND
GND
GND
GND
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
3V3
5V
5V
5V
3V3
Chassis
Chassis
Chassis
Chassis
Chassis
3V3
GND
JTAG_C
LK
JTAG_A
D0
JTAG_A
D1
nPP_I2C
JTAG_A
D2
nJTAG_W
E
EEPROM_S
CL
nJTAG_D
STR
nJTAG_TO
E
nJTAG_TR
ST
JTAG_TD
IJTA
G_TM
SJTA
G_TC
K
nJTAG_R
DY
JTAG_TD
O
nHRESET
PP_A
D[7..0]
nCPU_I2C
nPORST
EEPROM_S
DA
PP_B
USY
nJTAG_R
ST
PWR_2V
5_EN
PWR_1V
2_EN
MON3V
3
Title
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1284 TRANSCEIVER
Sheeld1
TCK_IN
5V_OUT
TDO_OUT
EPPSheeld2
EPP
Compliant
1284A
TDI_IN
TRST_INb
SPP
RESET
TMS_IN
Parallel - OnCE
JTAG_MASTER_CLOCK
SPP_TRSTbSPP_TDOSPP_TDISPP_TMSSPP_TCK
PP_I2C
CPU_I2CI2C_EN
SERIAL
DE_IN
IDENT
PARALLEL PORT
FORCE PARALLEL PORT
DEFAULT
CHASIS GROUND
CHASIS GROUND
EXTERNAL
PARALLEL
40.00MHz-3V3-50ppm
C181470pF C181470pF
L6L6
12
JP2
OPTIO
NJP2
OPTIO
N
R125150
OPTIO
NR125150
OPTIO
N
C189470pF C189470pF
C187470pF C187470pF
10
987654321
RN34
10K
RN34
10K
LD5LED_GREEN
OPTIO
N
LD5LED_GREEN
OPTIO
N
TP1
TP1
C191
470pF
C191
470pF
R1581K
R1581K
C175470pF C175470pF
C177470pF C177470pF
C184470pF C184470pF
C166
0.1uF
C166
0.1uF
L18L18
C178470pF C178470pF
TP20
TP20
R135150
R135150
TP9
TP9
L15L15
TP10
TP10
C176470pF C176470pF
TP8
TP8
C152
0.1uF
C152
0.1uF
C153
0.1uF
C153
0.1uF
C182
470pF
C182
470pFC173470pF C173470pF
TP11
TP11
TP5
TP5
C170
470pF
C170
470pF
TP2
TP2
C179
470pF
C179
470pF
TP3
TP3
C186470pF C186470pF
L16L16
L7L7
C192470pF C192470pF
L8L8
TP17
TP17
C174470pF C174470pF
TP18
TP18
C165
0.1uF
C165
0.1uF
R121150
R121150
C159
0.1uF
C159
0.1uF
L10L10
C4
0.1uF
C4
0.1uFR6
10KOPTIO
N
R6
10KOPTIO
N
C2
0.1uF
C2
0.1uF
C190470pF C190470pF
C161
0.1uF
C161
0.1uF
C188470pF C188470pF
13579
246810
P3
CON10A
P
P3
CON10A
P
C167
0.1uF
C167
0.1uF
L19L19
C164
0.1uF
C164
0.1uF
C171470pF C171470pF
LD10LED_GREENOPTIONLD10LED_GREENOPTION
R136150
R136150
C1
0.1uF
C1
0.1uF
L21L21
13
2
JP1
JMP1x3
JP1
JMP1x3
L13L13
R5
1K R5
1K
L12L12
TP16
TP16
L17L17
L9L9
TP7
TP7
VCC 4OUT
3
GND
2
EN
1
U1
OSC_S
MT-40.00M
Hz
U1
OSC_S
MT-40.00M
Hz
TP6
TP6
L14L14
TP19
TP19
TP4
TP4
C156
0.1uF
C156
0.1uF
A14
20
A15
21
A16
22
A17
23
PLH
30
HLH
24
C14
29
C15
28
C16
27
C17
26
PLH
in19
HLH
in25
B1
41
B2
40
B3
38
B4
37
B5
36
B6
35
B7
33
B8
32
A1
8
A2
9
A3
11
A4
12
A5
13
A6
14
A7
16
A8
17
Y9
47
Y10
46
Y11
45
Y12
44
Y13
43
A9
2
A10
3
A11
4
A12
5
A13
6
VCC17
VCC218VDD131
VDD242
GND110
GND215 GND334
GND439
HD
1
DIR
48
U274LV
X161284
U274LV
X161284
13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 12627
P1
DNR-25P
CB-SG
P1
DNR-25P
CB-SG
C3
0.1uF
C3
0.1uF
C185470pF C185470pF
C169470pF C169470pF
R134150
R134150
C183
470pF
C183
470pF
TP12
TP12
C180470pF C180470pF
TCK
62
TDI
4
TDO
73
G NDINT138
GNDINT286
GNDIO111
VCCINT139
VCCINT291
VCCIO13
VCCIO218
VCCIO334
VCCIO451
VCCIO566
VCCIO682
GNDIO226
GNDIO333
GNDIO443
GNDIO553
GNDIO659
GNDIO765
GNDIO874
GNDIO978
GNDIO1095
TMS
15
IN/GCLK
187
IN/OE2/G
CLK
290
IN/GCLR
89
IN/OE1
88
(A)GIO1
14
(A)GIO2
13
(A)GIO3
12
(A)GIO4
10
(A)GIO5
9
(A)GIO6
8
(A)GIO7
6
(A)GIO8
100
(A)GIO9
99
(A)GIO10
98
(A)GIO11
97
(A)GIO12
96
(A)GIO13
94
(A)GIO14
93
(A)GIO15
92
(B)GIO16
37
(B)GIO17
36
(B)GIO18
35
(B)GIO19
32
(B)GIO20
31(B)GIO21
30
(B)GIO22
29
(B)GIO23
25
(B)GIO24
23
(B)GIO25
21
(B)GIO26
20
(B)GIO27
19(B)GIO28
17
(B)GIO29
16(C)GIO30
40
(C)GIO31
41(C)GIO32
42
(C)GIO33
44
(C)GIO34
45
(C)GIO35
46
(C)GIO36
47
(C)GIO37
48
(C)GIO38
52
(C)GIO39
54
(C)GIO40
56
(C)GIO41
57
(C)GIO42
58
(C)GIO43
60
(C)GIO44
61
(D)GIO45
63
(D)GIO46
64
(D)GIO47
67
(D)GIO48
68
(D)GIO49
69
(D)GIO50
71
(D)GIO51
75
(D)GIO52
76
(D)GIO53
79
(D)GIO54
80
(D)GIO55
81
(D)GIO56
83
(D)GIO57
84
(D)GIO58
85
GIO62
1
GIO59
2
GIO63
5
GIO64
7
GIO65
22
GIO66
24
GIO67
27
GIO68
28
GIO69
49
GIO70
50
GIO71
55
GIO60
70GIO61
72
GIO72
77
PLD
U3
EPM3064A
TC100-10
PLD
U3
EPM3064A
TC100-10
L20L20
L11L11
C172470pF C172470pF
LD6LED_GREEN
OPTIO
N
LD6LED_GREEN
OPTIO
N
LD12LED_GREEN
OPTION
LD12LED_GREEN
OPTION
TP13
TP13
LD7LED_GREEN LD7LED_GREEN
MSC711xEVM Reference Manual, Rev. 0
A-10 Freescale Semiconductor
MSC711xEVM Schematics
A.1.10 Power 55
44
33
22
11
DD
CC
BB
AA
PWR_3V
3_EN
nPORST
nPORST
GND
2V5
GND
5V
GNDGND
5V
GNDGND
GND
1V2S
L3V
3
GND
2V5
VREF
VTT
GND
3V3
GND
GNDGND
GND
3V3
GND
3V3
3V3
1V2S
L
3V3
GND
3V3
3V3
GND
3V3
3V3
GND
Chassis
GNDGND
GNDGND
GNDGND
3V3
GND
5V
3V3
GND
GND
5V
GND
2V5
PWR_2V
5_EN
PWR_1V
2_EN
nHRESET
nPORST
MON3V
3
Title
Size
Docum
ent Num
berRev
Date:
Sheet
of
PROTO
MSC711xE
VM: P
OWER
Freescale Sem
iconductor Israel Ltd.
Metrow
erks Israel
A3
1111
Wednesday, A
pril 06, 2005
Title
Size
Docum
ent Num
berRev
Date:
Sheet
of
PROTO
MSC711xE
VM: P
OWER
Freescale Sem
iconductor Israel Ltd.
Metrow
erks Israel
A3
1111
Wednesday, A
pril 06, 2005
Title
Size
Docum
ent Num
berRev
Date:
Sheet
of
PROTO
MSC711xE
VM: P
OWER
Freescale Sem
iconductor Israel Ltd.
Metrow
erks Israel
A3
1111
Wednesday, A
pril 06, 2005
MAIN GROUND-BRIDGES
MSC7116 DDR Voltage [email protected]
MSC7116 I/O Voltage [email protected]
MSC7116 CORE Voltage [email protected]
DDR VREF and VTT
CHASIS GROUND
Vt=1.05V
HRESET SWITCH
Vt=1.05V
POWER ON RESET
"5V IN
PUT"
TAB IS GROUNDED
3.3V_LED
5V_LED
2.5V_LED
TP21
Vtt
TP21
Vtt
12
F1SMD150/33-2
F1SMD150/33-2
RST
1
GND
2
MR
3
WDI
4
MON
5VCC 6
U14
MAX6831S
FUT
U14
MAX6831S
FUT
VIN
4
EN/ADJ
1GND
3
VOUT_1V
25
VBIAS
2
TAB
6
U16
MIC49150-12B
R
U16
MIC49150-12B
R
LD13
LED_G
REEN
LD13
LED_G
REEN
VDD1
1
VDD2
2
VDD3
7
PGND1
4
PGND2
5
PGND3
8SGND
13VREFin
11SHDN
12
VDDQ
15
NC1
9
NC2
16
VREFout
14
VTTforce1
3
VTTforce2
6
VTTsense
10
PAD17
Bus
Term
inationRegulator
U9
FAN1655M
TF
Bus
Term
inationRegulator
U9
FAN1655M
TF
R44
10KOPTIO
N
R44
10KOPTIO
N
+ C89
100uF16V
+ C89
100uF16V
R7610K
R7610K
TP24
3V3
TP24
3V3
C162
0.1uF-500V
C162
0.1uF-500V
R17
330
R17
330 R47
10KOPTIO
N
R47
10KOPTIO
N
C54
1uF C54
1uF
LD11
LED_R
ED
LD11
LED_R
ED
R22
150
R22
150
C102
0.1uF-500V
C102
0.1uF-500V
TP22
Vref
TP22
Vref
VIN
2
SD
1
GND
3
VOUT_3V
34
ERROR/SENSE
5
TAB
6
U18
NATIO
NAL_LP
3872_3V3
U18
NATIO
NAL_LP
3872_3V3
R13
150
R13
150
12
JS3
JS3
12
JS2
JS2
R106
0
OPTIO
N
R106
0
OPTIO
N
+C53
47uF+
C53
47uF+ C42
1uF
+ C42
1uF
C10
1nF
C10
1nF
R159
4.7k
R159
4.7k
R46
10KR46
10K
+ C39
100uF16V
+ C39
100uF16V
R79
10KR79
10K
+C55
10uF+
C55
10uF
RST
1
GND
2
MR
3
WDI
4
MON
5VCC 6
U13
MAX6831S
FUT
U13
MAX6831S
FUT
+ C6
1uF
+ C6
1uF R48
10KOPTIO
N
R48
10KOPTIO
N
VDD
2RESET
1
G ND3
NC1
4NC2
5
U23
S-80828A
NMP-EDR-T2
U23
S-80828A
NMP-EDR-T2
TP26
5VTP
26
5V
12
JS1
JS1
R7510K
R7510K
TP27
1V2SL
TP27
1V2SL
R55
10KR55
10K
+C135
100uF16V+C135
100uF16V
123
P11
RAPC722
P11
RAPC722
+ C35
100uF16V
+ C35
100uF16V
C52
1uF C52
1uF
C160
0.1uF-500V
C160
0.1uF-500V
LD8
LED_G
REEN
LD8
LED_G
REEN
213
SW4
SW4
1 4
2 3SW2
RED
SW2
RED
C56
0.1uF-500V
C56
0.1uF-500V
R120
0 R120
0
+ C57
100uF16V
+ C57
100uF16V
R91
10KR91
10K
+ C75
100uF16V
+ C75
100uF16V
+ C136
100uF16V
+ C136
100uF16V
+ C7
1uF
+ C7
1uF
VIN
2
SD
1
GND
3
VOUT_2V
54
ERROR/SENSE
5
TAB
6
U17
NATIO
NAL_LP
3872_2V5
U17
NATIO
NAL_LP
3872_2V5
TP25
2V5
TP25
2V5
C8
1nF
C8
1nF
R40
10KR40
10K
+ C50
100uF16V
+ C50
100uF16V
R8210K
R8210K
MSC711xEVM Reference Manual, Rev. 0
Freescale Semiconductor A-11
MSC711xEVM Reference Manual, Rev. 0
A-12 Freescale Semiconductor