MS7b STAMP RTP102.086 executive summary …eda.europa.eu/docs/documents/STAMP_executive_summary_1.pdf · Executive summary report Document Ident Type Rev_Iss Status 9505 ... A life

RTP102.086 STAMP Page 1/28 Executive summary report

Document Ident Type Rev_Iss Status 9505-002-819XX 001 EAR 1.0 Approved-Authorized

Surface-mount Technologies for Active Modules

Production

- STAMP -

D22 of Milestone 7b

RTP102.086 Executive Summary

Ivo Maatman TNL

Gijs van der Bent TNO Jan-Olof Axelsson SMW

Date of issue: 23/11/2009

This is an unpublished work the copyright in which vests in THALES Naval Netherlands, TNO and SAAB Microwaves Systems.

All rights reserved.

The information contained herein is the property of THALES Naval Netherlands, TNO and SAAB Microwaves Systems and is supplied without liability for errors or omissions. No part may be reproduced, disclosed or used except as authorized by contract or other written permission. The copyright and the foregoing restrictions on reproduction, disclosure and use extend to all media in which the information may be embodied.



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TABLE OF CONTENTS

1 INTRODUCTION ............................................................................................. 3 1.1 Global project objectives.........................................................................................3 1.2 Project organization.................................................................................................3 1.3 What is demonstrated..............................................................................................3 1.4 STAMP project structure. ........................................................................................4 1.5 List of STAMP publications (EuMW).......................................................................4

2 TECHNOLOGIES DEMONSTRATED IN THE STAMP PROGRAM............... 5 2.1 WP2.1: TX X-Band IC................................................................................................5

2.1.1 Global description of the work executed. .............................................................5 2.1.2 Goal of the work done..........................................................................................5 2.1.3 Detailed description of the work...........................................................................6 2.1.4 Analysis WP2.1....................................................................................................8

2.2 WP2.2: RX C-band IC. ..............................................................................................9 2.2.1 Global description of the work executed. .............................................................9 2.2.2 Goal of the work done..........................................................................................9 2.2.3 Detailed description of the work...........................................................................9 2.2.4 Analysis WP2.2..................................................................................................10

2.3 WP3: Packaging; antenna on package and package failure mechanisms........11 2.3.1 Antenna radiator development...........................................................................12 2.3.2 Final antenna package simulation .....................................................................12 2.3.3 Package Failure mechanisms and reliability ......................................................13

2.4 WP4: STAMP Passive array antenna demonstrator. ...........................................18 2.4.1 Simulation of passive antenna panel performance. ...........................................19 2.4.2 STAMP Passive array antenna panel measurements. ......................................20 2.4.3 Analysis Passive antenna demonstrator............................................................21

2.5 WP4: STAMP Active array antenna tile demonstrator ........................................21 2.5.1 STAMP Active module and tests setup..............................................................22 2.5.2 STAMP Active array antenna measurements. ...................................................24 2.5.3 Analysis Active array antenna demonstrators....................................................26

3 CONCLUSIONS STAMP............................................................................... 27



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1 INTRODUCTION

This executive summary gives a general overview of the activities, progress and achievements of the program STAMP. (Surface-mount Technologies for Active Modules Production). STAMP is a 36 months Eurofinder study program started under CEPA 2 (Microelectronics). The program started at September 1rst 2005 and ended at the (extended) final milestone at May 28th 2009. The final documents were distributed in November 2009. 1.1 Global project objectives

The objective of the STAMP project is to address the technical evolution towards the next generation of modular active transmit or receive phased array systems targeting cost reduction for Transmit and Receive components and systems taking advantage of the latest development of mass-production commercial microwave component and packaging technologies. It aims at single-chip active transmit antenna integrated component and single-chip receivers. Pick-and-Place assembly is used to build a transmit array panel and an integrated receiver front-end. The associated reliability was assessed by using specifically designed test vehicles. 1.2 Project organization

In the program STAMP following companies worked together:

• THALES NAVAL NEDERLAND, The Netherlands • SAAB MICROWAVE SYSTEMS, Sweden • TNO PHYSICS AND ELECTRONICS LABORATORY, The Netherlands

TNNL is acting as Single Lead Industrial Entity (SLIE) and is as such responsible for a possible conclusion of the main contract with the EDA and for the conclusion of the subcontracts or a consortium agreement with the IE’s. TNO-FEL and SAAB Microwave are participating in this project as an Industrial Entity (IE). Initially the contract was signed by the Western European Armaments organization (WEAO) Research Cell (referred to as WRC). Due to reorganization this contract was transferred to the European Defense Agency (referred to as EDA) at March 3rd 2006. 1.3 What is demonstrated

Within the STAMP work packages following work was executed: WP1: Requirement definition. Analyze and define performance of:

• TX X-Band IC. • RX C-Band IC. • Package for module.



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• TX X-Band Antenna on package. • TX X-Band radar Antenna Tile based on radiating packages. • Failure mechanisms and needed tests.

WP2: ICs development. WP2.1: TX X-Band IC: define; simulate design, manufacturing and test.

WP2.2: RX C-Band IC: define; simulate design, manufacturing and test. WP3: Pick & place packages development.

WP3.1: Technology assessment TX X-Band package and antenna structuring. WP3.2: Commercial package adaptation. WP3.3: Antenna development suited for X-Band capable phased array scanning. WP3.4: Investigate and analyze failure mechanisms.

WP4: Demonstration. WP4.1: X-Band Antenna panel demonstrators; passive and active. WP4.2: Test reliability of packages. Most of the work done in WP1 (requirement definitions) and WP3 (technology assessment and commercial packages) is used as input for the development for hardware and demonstrators. In this executive report this input part of WP1 and WP3 is concluded in the description of the subjects and hardware itself. 1.4 STAMP project structure.

The following table gives an overview of the participation of each partner on the various work packages (a cross implies active participation).

WP Sub WP Description TNNL TNO SMW WP Leader

WP0 Project management X X X TNNL WP1 Requirement definition X X X TNNL WP2 ICs development X X X TNO 2.1 GaAs Tx IC X X TNO 2.2 SiGe Rx IC X SMW WP3 Pick & place packages development X X X SMW 3.1 Technology Assessment X X X TNNL 3.2 Commercial Packages Adaptation X SMW 3.3 Antenna on Package Development X X TNNL 3.4 Failure Mechanisms X SMW WP4 Demonstration X X TNNL 4.1 Transmit Antenna Panel X TNNL 4.3 Reliability Analysis X X SMW

1.5 List of STAMP publications (EuMW)

• X-band Phase Shifting Dual Output Balanced Amplifier MMIC . • A High Linearity Mixed Signal Down Converter IC for C-band Radar Receivers. • XBand-phase-shifting-PWR-MMIC. • Protection-circuit-HPA-under-mismatch. • Low-cost TRM technologies for phased array radars_juni19th2009. (related to STAMP)



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2 TECHNOLOGIES DEMONSTRATED IN THE STAMP PROGRAM.

The next chapters will describe the technology items of the program; the main subjects are:

• TX IC. • RX IC. • Packaging; antenna on package, package failure mechanisms and reliability. • Passive array antenna demonstrator. • Active array antenna demonstrator.

2.1 WP2.1: TX X-Band IC.

2.1.1 Global description of the work executed. This chapter describes the development of a Tx X-band IC, a balanced HPA module and an integrated balanced amplifier. 2.1.2 Goal of the work done. WP2 has the following objective:

Design, manufacturing and test of the IC’s. WP2.1 has the following activities: (Tx X-band IC ). GaAs Tx chip final technology and topology selection GaAs Tx chip design, manufacturing and test (2 successive runs)

The target specifications for the Tx IC are listed in table 1. These specifications are obtained from the requirement definition. Specification Unit Value Remark Operating frequency GHz 8.5 – 10.5 Originally 20% at X-band was

specified Output power dBm > 36 Gain dB > 20 Output VSWR - up to 3:1 Any phase Number of bits - 6 3 to 5 bits according to original

specification Control voltage V 0 - 5 single ended

Table 1: Target specifications Tx X-band IC.



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2.1.3 Detailed description of the work In WP2.1 an X-Band Phase Shifting Power Amplifier MMIC was developed.

Figure 1 Photograph of integrated PHS and HPA CHIP TNO. The chip hold a 6 bits phase shifter and a 5 W X-Band amplifier. More details can be found in the EuMW publication. The measured output power and phase plane are shown in figure 2. The device delivers an output power of almost 37 dBm over the operating frequency band. In order to guarantee the reliability of the Tx IC under any load condition, a protection circuit is included which reduces the drive level of the output stage when the measured drain voltage peaks become too high.

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Figure 2 Tx X-Band IC test results. A life time test was performed at a VSWR of 3:1 with a phase that yields the highest drain voltage peaks. The result of this test shows that the output power was reduced with the same amount of degradation as observed from a lifetime test under nominal load conditions on a device from the same process. This demonstates that the HPA is effectively protected against extreme degradation due to voltage breakdown Within work package 2.1 also two types of balanced amplifiers where designed. The first amplifier is a module containing two separate amplifier MMICs.



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Figure 3 Balanced HPA module. A second balanced amplifier, the X-Band Phase shifting Dual-output Balance Amplifier MMIC was developed; this was presented in the EuMW 2009.

Figure 4 Photograph X-Band Phase shifting Dual-output Balance Amplifier. This MMIC contains two 6 bits phase shifters and two 1W X-Band amplifiers in a balanced configuration. It has two outputs and the output power ratio for the two outputs can be controlled with the phase shifter settings.



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Figure 5 Performance the X-Band Phase Shifting Dual-output Balanced Amplifier. For the balanced PSPA a package based on LTCC technology was designed. The photograph of the MMIC in the package shows the package from the bottom looking up to the MMIC which is bonded on the top metal base plate. Benefit of this packaging option is that the metal base plate on which the MMIC is bonded has a direct thermal contact to the ambient. This reduces the thermal resistance compared to the situation where the base plate is connected to a PCB.

Figure 6 Balanced PSPA package. 2.1.4 Analysis WP2.1. The performance of the TX X-band IC is compliant with the target specifications. The life test on the Tx X-band IC under mismatch conditions have shown a normal output power degradation. This is an indirect indication that the protection circuit is functional. The balanced PSPA MMIC has shown the reduction of load pulling. The configuration with two phase shifters opens the possibility for output power balance control.



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2.2 WP2.2: RX C-band IC.

2.2.1 Global description of the work executed. Low-cost silicon based semiconductors processes have steadily improved there performance over the years. At the same time it is today the only technology that successfully can be used to integrate analog/microwave and digital circuits on the same IC. This makes it interesting for applications where the number of components is crucial e.g. AESAs or multi-channel receivers. A reduced number of components reduces not only overall size but can also reduce the amount of data transferred between different components and thereby the complexity of the system. In order to investigate the possibilities of using silicon based mixed-signal ICs in radar applications a work package was initiated within STAMP where two receiver ICs were designed and manufactured. In order for such circuits to be successfully designed a lot of works have been spent to develop a consistent design flow. This was necessary since no complete design flow incorporating microwave and digital circuits was commercially available. 2.2.2 Goal of the work done. WP2 has the following objective:

Design, manufacturing and test of the IC’s. WP2.2 has the following activities: (RX C-band IC ).

SiGe Rx chip final technology and topology selection SiGe Rx chip design, manufacturing and test (2 successive runs)

The goal of the work done can be separated into three main goals listed below. 1. A receiver IC suited for a C-band receiver shall be designed where on-chip digital

control circuits shall be integrated to realize the following functions; automatic calibration for temperature and process parameters. Also an automatic STC-curve where all data is stored on-chip shall be realized.

2. Wideband microwave circuits designed by using standard analog/RFIC design solutions shall be demonstrated. Preferably these shall be integrated into a wideband receiver IC.

3. A consistent design flow shall be used to design the above ICs. This means that all circuits, both microwave and digital, shall be designed, simulated, layouted and checked using the same tools. This is important to minimize the risk of errors when all circuits are integrated into the same IC.

2.2.3 Detailed description of the work. Two receiver ICs have been designed. The first one has a vast amount of digital control circuits integrated in order to make the IC more or less autonomous. The design work of the second IC rather focused on the possibilities of using standard analog design methodologies to achieve wideband microwave circuits. A large amount of work was done in order to achieve a consistent design flow that can be used for both analog, microwave and digital circuits. This was necessary since these kind



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of circuits require different tools but shall still be integrated onto the same IC and work together. For example it is not possible to manually do the layout of the digital circuits due to the large number of devices. At the same time it is necessary to make the layout of the microwave circuits manually due to the required control of parasitics and so on. When a consistent design flow was established the two ICs could be designed with a large degree of confidence. The first IC is a C-band receiver IC with an output frequency of 2GHz. The IC should have a large number digital control circuits integrated; one of the realized functions was an STC-functionality. This means that the gain can be automatically controlled as a function over time. This is done completely automatic after a trig pulse has been transmitted. On example of the shape of the time dependent gain is shown in Figure 7 where a giraffe has been drawn at a sample rate of 2kHz even though sample rates up to 62.5MHz have been verified. The second IC is a wideband receiver IC that covers an input frequency range of 2-10GHz with an output frequency in band of 100-2500MHz. This means that the circuits can be used for the S-, C- and X-bands and even for a second conversion stage with an IF of 2 GHz. This was realized by using standard analog circuit methodologies instead of matched circuits. This also resulted in large reduction of circuit area since all inductors were omitted. This can be seen in Figure 7 where the second IC is laid out at the corner of the first one. Smaller ICs are not only a blessing when cost is concerned but also from reliability point of view. A smaller IC requires a smaller package and as been shown in work package 3.4 this is more robust to (for example) temperature cycling. Both ICs have been verified with good results showing good agreement with simulations. 2.2.4 Analysis WP2.2. It has been shown through this work package that it is possible to integrate high performance ICs in a standard silicon germanium process. The possibilities to also integrate a vast amount of digital content has also been demonstrated. That was done by designing a more or less autonomious receiver IC at C-band. The IC has integrated calibration data, temperature compensation and even a self timed STC-function. To be able to integrate microwave and digital circuits together with a high degree of confidence the design flow had to be revised so that all tools can use the same database. During the second run of the receiver IC the focus was spent on using traditional low frequency designs to realize the IC. The idea was to make it smaller and more wideband. This resulted in a very small size IC with a bandwidth of 2-10.5 GHz covering all the major radar bands. A standard high-volume low-cost silicon process has been used and the chips are packaged using a standard plastic package. The process has shown excellent environmental protection and is well suited for standard pick-and-place mounting on organic substrates. The process is used in commercial components in high volumes. This means that in terms of technology readiness level (TRL) the process and package would correspond to level 9.



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Figure 7 The two things that mainly stays in mind of the authors The two things that mainly stays in mind of the authors are the size reduction when using standard low frequency design topologies and the vast amount of intelligence that can be integrated when using a BiCMOS technology. 2.3 WP3: Packaging; antenna on package and package failure mechanisms.

Major part of the consumer electronics is surface mount. The Surface Mount Technology (SMT) is a very cost effective way of assembling electronics compared to the traditional ceramic hybrids for military electronics. Also the yield is much higher for surface mount assembly. The high frequency and high performance in components for defence products are rarely met in commercial available components. One of the most promising technologies to meet our STAMP objectives is a plastic package, combined with automatic pick & place assembly. Before the design of the package was started, a cavity QFN package type was selected in order to establish the global package geometry and interconnectivity. Extra attention is paid to the way of antenna-structure integration on package, which is realized by laser structuring the surface(s) of the package. At the start of the program separated antenna structures like non-planar transmission lines, interconnections and radiator designs were engineered. The final package design is created by a combination of the previous work combined with new iterative simulations to finally achieve the requirements for radar applications. Objectives WP3:

Review and selection of commercial pick and place packaging technologies, adaptation to military applications and antenna integration, review of critical failure mechanisms.



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Phi: 00deg, Theta: 00degPhi: 00deg, Theta: -60degPhi: 00deg, Theta: 60degPhi: 45deg, Theta: -60degPhi: 45deg, Theta: 60degPhi: 90deg, Theta: -60degPhi: 90deg, Theta: 60deg

2.3.1 Antenna radiator development The QFN type package is a good candidate for the antenna on package design mainly because of its proven microwave performance and cost. Although other types of antennas are considered a stacked patch type radiator on top of the QFN package can overcome the disadvantages of limited bandwidth and limited scan performance. Simulations proved this claim. Detailed design of this stacked patch radiator and detailed design of the complete module was executed in this program. Several demonstrators produced verify the feasibility of the stacked patch antenna.

Figure 8 Stacked patch antenna and input matching under scan angle performance 2.3.2 Final antenna package simulation The final antenna-on-package design was investigated to obtain the resulting antenna scanning performance over the required bandwidth. The simulated antenna performance is shown in three directions: broadside and the two extreme scan angles in E- and H-plane (elevation and azimuth).

Figure 9 Simulated antenna performance and package in intermediate version. All the suggested modifications from production and assembly point of view are designed and investigated for antenna performance. These final simulation results show the reflection in E- and H-plane (elevation and azimuth), the results are good and this setup was used for the final designing of the STAMP antenna demonstrators.



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2.3.3 Package Failure mechanisms and reliability The two main concerns of interest tested are corrosion resistance and solder fatigue. To investigate the humidity resistance, corrosion testing was performed both on chip and package level. Passivation on wafer level on Si-chip is mature but still under development on GaAs at many foundries. Corrosion testing was also performed on package level to find failure mechanisms and to compare epoxy moulded with cavity QFN packages. Solder fatigue is a common failure cause, and is of special interest since the studied QFN packages have a very low stand off. Several packages were studied in temperature cycling of two different test boards. 2.3.3.1 Corrosion test on chip level A specially designed test chip containing different test structures was designed and manufactured in different foundry processes for GaAs and SiGe. The samples were subjected to a cyclic humidity corrosion test based on MIL STD-202F, method 106 Tropical Test. This corrosion test is a severe test, designed to give failure within a rather short time period. Results from this corrosion test can to some extent be correlated to field data on telecommunications equipment. The test structures were biased during the test. The power dissipation was kept low to enable condensation on the chip surface. The development of the corrosion can be represented by the results obtained on one of the meander patterns, shown in Figure 10.

Corrosion development on GaAs without passivation Meander 10

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Corrosion development on SiGe with SiN+PI Meander 10

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Figure 10 Development of corrosion on the meander 10 pattern; GaAs without passivation (left), GaAs with BCB and SiN (middle), and SiGe with SiN and PI (right). Results show that:

• GaAs without any passivation showed the highest sensitivity towards humid environment.

• Passivation with BCB and SiN increased the humidity resistance • No defects were detected by optical inspection on the test patterns on the SiGe

chip. Not even after 1330 hours in test! 2.3.3.2 Corrosion testing of packages For the corrosion test on package level, a GaAs humidity test chip without passivation was mounted inside 7x7 epoxy moulded and in air-cavity QFN packages. A 4x4 epoxy package containing the same humidity test chip with a passivation of BCB was also tested. The boards were coated with acrylic conformal coating.



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The packages were subjected to a pressure cocker test at 110 °C. The packages were continuously biased with +5 V. The air-cavity packages were the first to fail in the corrosion test. The failure mechanism for the air-cavity packages was corrosion on chip level, shown in Figure 11.

Figure 11 Corrosion on chip level in one of the air-cavity packages. The corrosion resistance of the epoxy moulded packages was significantly better. Failure occurred due to corrosion and migration on board level. Figure 12 show some examples of current leakage and shorts. The failure is most likely related to flux residues.

Figure 12 Corrosion and migration leading to current leakage and shorts. The 4x4 packages containing passivation on the die had as expected the best corrosion resistance. 2.3.3.3 Fatigue of solder joints The QFN packages are small but have a very low stand-off (gap between package and board) and a CTE mismatch towards the board since the chip is large in relation to the package. Results from simulations and experiments reported on QFN packages show that solder joint fatigue is critical for applications that are subjected to large temperature variations. The solder fatigue is sensitive to factors that affect the stiffness of the materials adjacent to the solder joint such as board CTE, thickness and number of Cu layers of the board, die to die pad ratio, thickness of die, mould compound CTE/modulus etc.



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Temperature cycling was first performed on relatively thin boards with various packages. The boards consisted of four layers with 10 mil Rogers 4350B on each side of a FR4 core. The test boards contained different QFN packages, all with a daisy chain Si-chip. Temperature cycling was performed between -40 and +100 °C, with 15 minutes dwell time. The total cycle time was 70 minutes. The equipment used for continuous electrical monitoring during the temperature cycling was developed in-house by SMW. It fulfils the requirement according to IPC-9701A with the exception of a lower resistance change of 500 Ω. The results from the temperature cycling of the thin boards are presented in Table 2. Table 2 Results on thin boards after 7500 cycles. Package

Failure (%) Comment

Epoxy 7x7 (HANA) 22 Air-cavity 7x7 (SEMPAC) 31 Air-cavity 12x12 (SEMPAC) 67 Epoxy 4x4 3 Ceramic package (Kyocera) 80 Most likely 100 % PLCC48 12 0 % according to dye penetrant test

Generally, the failure rates were low. The two main reasons were:

• Thin test boards (0,86 mm) resulting in comparatively low stresses on the solder joints

• Good solder joint geometries of the QFN packages The result from the temperature cycling of the packages is shown in Figure 13.

Failure rate for packages on 0,86 mm thick board

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7x7 Epoxy QFN7x7 Air-cavity QFN12x12 Air-cavity QFN4x4 Epoxy QFN7x7 Ceramic air-cavity

Figure 13 Failure rates for packages on thin board. The second board that went through temperature cycling was a 18-layer board with a thickness of 2,2 mm. The carrier used in the STAMP antenna demonstrator was evaluated together with different QFN packages, reference packages and some RF-filters. The boards were conformally coated and mounted on a carrier.



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The boards were cycled for 2385 cycles, all package types showed high failure rates. Results are shown in Table 3.

Table 3 Results on thick boards after 2385 cycles. Figure 14 shows the failure rates for the 7x7 QFN package on the two test boards.

REF QFN

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Figure 14 Failure rate for the 7x7 QFN packages (blue-thick boards, pink-thin boards). The failure rate was expected to be much higher (i.e. the time to failure shorter) on the thicker boards since the stresses on the solder joints would be much higher. The difference was however larger than expected. Results from the other types of QFN packages are shown in Figure 15.

Package

Failure (%) Comment

7x7 epoxy QFN (TopLine) 100 9x9 epoxy QFN 100 No die inside Air-cavity 8x8 (Quantum) 93 TNL carrier 62 LGA (Linear) 100 PLCC48 94 BGA1156 (Xilinx) 100



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Figure 15 Failure rates for some packages on thick boards. The three surface mount filters were characterised by RF-measurements. Two of the filters were not affected, while the solder joints of the third filter was degraded during the temperature cycling.

2.3.3.4 Analysis Failure Mechanisms and Reliability The corrosion testing on chip level shows that a good passivation is essential for the humidity resistance. Addition of a passivation consisting of BCB and SiN on GaAs increase the humidity resistance significantly. The SiGe chip with SiN and PI showed superior humidity resistance compared to the GaAs chip. No corrosion defects were detected during the very long test time for the SiGe chip. Results from the package corrosion testing show clear differences between the air-cavity and the epoxy moulded packages. The air-cavity packages fail early due to corrosion on chip level inside the package. Air-cavity packages are sensitive to humid conditions and are not suitable in humid environment unless they are protected. The epoxy moulded packages show much better humidity resistance. The failure occurs outside the package on board level, most likely due to flux residues. Since the QFN package have a very low stand off, cleaning after soldering becomes more difficult. The package is more sensitive to humid environments than packages with a large gap between component and board providing for better cleaning. Temperature cycling was performed on two different test boards. The thin boards showed lower failure rates than expected for the QFN packages. The good results are explained by thin test boards and good solder joint geometries. The failure rates on the thicker test boards were however much higher. The results show that the properties of the board have a large influence on the life-time for a specific package. The temperature cycling results also show that QFN packages are sensitive to large temperature variations. A large delta T in an application results in much shorter time to failure.



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The size of the package is also essential, smaller packages have longer life-times. The influence of the size of the chip is also reflected by the results of the TNL carrier. Several small components inside the package will increase the life-time compared to one single big chip covering the major part of the middle cooling pad. The results from the environmental testing show that the possibility to use SiGe in future applications has clear environmental advantages:

• Superior humidity resistance on chip level • Increased life-time (solder fatigue) due to the possibility of using smaller

packages as result of decrease in chip size Chip and packages are today commercially available. The technology readiness level for military applications is regarded as level 5. Depending on environment and type of QFN package chosen for the application, proper environmental protection on subsystem level might be needed. 2.4 WP4: STAMP Passive array antenna demonstrator.

WP4 has the following objective: Demonstration of pick & place integrated component technology, for a transmit

array panel with the associated reliability assessment. The work done for the reliability assessment within WP4 was already shown in the former paragraph; in this chapter the focus of the executive report lies on the antenna demonstrators. This work package has two main goals:

• To verify the antenna performance and accuracy of the simulation models • To measure the active antenna performance after integration of the active STAMP

component developed in WP2.1 For the passive antenna measurements, an infinite array size would be ideal. This is technically and budgetary not possible. In this program a 16x16 array (256 passive modules) is used in the passive antenna demonstrator as shown in Figure 16. In this PCB panel, each element can be accessed by a network analyzer via its own RF connector located on the backside of the panel. For the passive array performance measurements, the individual element gain and patterns are measured using a network analyzer in a near field test range. From the near field measurements combined with the mutual coupling data, the far field pattern and scan performance of the array is calculated.

Figure 16 Passive demonstrator panel



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2.4.1 Simulation of passive antenna panel performance. For the measurements with the passive demonstrator, in particular the verification of the designed antenna performance, not only the simulated and expected performance of the antenna on package design is important. For straightforward design verification the package (together with the interconnection of the package to the PCB), the PCB itself and the connector are included in the simulations as well. This simulation is carried out with the configuration as shown in Figure 17.

The simulated performance of the total passive demonstrator set-up is shown in Figure 18, which shows the return loss in E-plane (elevation).

Figure 17 Simplified view one passive element

Figure 18 E-plane return loss demonstrator



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2.4.2 STAMP Passive array antenna panel measurements. After manufacturing the STAMP packages and after assembling the passive antenna board, measurements are executed.

Figure 19 Passive antenna demonstrator reflection measurements at Thales NL.

Figure 20 Passive antenna demonstrator in Near Field Test Range at Thales NL. Reflection measurements were executed over the most central orientated elements.

STAMP Packages

PCB Board



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After measurements the measured return loss can be compared to the simulated one:

8 .0 0 8 .5 0 9 .0 0 9 .5 0 1 0 .0 0 1 0 .5 0Fre q [G H z]

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A ns oft C orpora t ion E x tX_A r3 4543nP as s ive R e turn L o s s , C e nte r rad ia to r

Cu rv e Inf o

d B(S(Lu mp Po r t1 0 ,L u mp Por t10 ) )Se tup 1 : Sw ee p 1

Figure 21 Passive Return-loss single array element based on HFSS.

8 0 0 0 8 5 0 0 9 0 0 0 9 5 0 0 1 0 0 0 0 1 0 5 0 0-2 0

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Figure 22 Passive Return-loss single array element based on coupling data. 2.4.3 Analysis Passive antenna demonstrator. The passive demonstrator (array of passive 16x16 elements in a triangular grid) was used to prove the array performance of the elements. First the reflection and the coupling from element to element was measured, and from that the actual scan loss performance was determined. The measured values show a good match with the simulated data demonstrating the feasibility of this concept. 2.5 WP4: STAMP Active array antenna tile demonstrator



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The second demonstrator is the active demonstrator where the assembled QFN package are placed on the PCB board. For practical reasons, the active tiles are holding 16 modules each. The complete array consists of 16x4 = 64 modules. The practical design of these mini-tiles is constructed in such a way that the antennas are scalable in a horizontal way to realize a wider antenna with better beamforming. In practice and for symmetrical considerations only 16x3 elements are used in the final demonstrator. 2.5.1 STAMP Active module and tests setup. The active STAMP modules are build out of:

• Injection molded packages designed under WP3.3. • QFN carrier, also designed under WP3.3. • GaAs TX X-Band chip as designed and tested in WP2.1.

This is resulting in a SMD component, which is directly transmitting RF power out of the package itself.

Figure 23 Stamp package and STAMP inner QFN assembled carrier. The output power of the HPA will directly be fed to the antenna on top of the package; the other connections on the HPA are interconnected by means of three small ceramic substrates. When the QFN carrier is assembled with chip and these substrates, the package lid is also placed on the carrier to form the STAMP active module. The function of the transmitting active module is tested before placing them on the antenna PCB Tile panels. The tiles will hold the complete packages with their integrated antennas as well as the other required electrical components for antenna measurements, like FPGA beamsteering data control, power components, etc.

Antenna



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Figure 24 16x4 active demonstrator array

Figure 25 Cross section of active demonstrator panel With the active demonstrator panel the scan performance and ERP can be measured in a near field antenna test range.



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2.5.2 STAMP Active array antenna measurements. The STAMP active antenna demonstrator was put in an antenna test range. First the electronics was set to work and finally all elements were calibrated to be able to generate a good boresight beam. The antenna setup is placed on a rotating platform.

Figure 26 Active STAMP antenna Tile in Antenna range



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Several beams were measured; boresight and lots of angled beams up to 60 degrees offset. Note that only limited beamforming is possible with a width of only 16 elements.

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m e t in g 4 9 . 5 G H z fi0 2 0 0 7 0 9t h e o re t ic a l , c o s (fi ) x A F (w it h t h e o re t ic a l s p h e re )

Figure 27 Measurement result STAMP active antenna boresight Note that the measured value neatly matches the theoretical values!

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meting1 95GHz fi 30° 210709reference level boresighttheoretical, cos(fi) x AF

meting1 95GHz fi -30° 210709reference level boresighttheoretical, cos(fi) x AF

Figure 28 Results of a phase setting belonging to a beam of – and + 30 degrees.



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Figure 29 Results of a phase setting belonging to a beam of – and + 60 degrees. 2.5.3 Analysis Active array antenna demonstrators. The active demonstrator is an antenna array of 16x3 elements. This array was created by placing four tiles next to each other, each tile containing 4x3 Stamp modules. Each active STAMP modules holds the antenna-on-package based on a QFN carrier carrying the developed STAMP HPA/Phaseshifter chip. The SMD boards hold the active STAMP modules and contain all the drive electronics towards the active modules. Soldering and placing of the (QFN) active modules took extra attention and was not a normal SMD process. With the active STAMP array we were able to realize active TX beamforming on a 16 elements wide STAMP antenna array. All elements were calibrated and beam setting data for boresight and various offset beams were generated and measured. Good scan performance was measured over 120 degrees beam range. The measurements nicely fit with designed and simulated array performance.



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3 CONCLUSIONS STAMP

In this 3,5 year Eurofinder study program RTP102.086 the STAMP partners (Thales NL, TNO and SAAB Microwave) were able to study and test many aspects of the technical evolution towards the next generation of modular active transmit or receive phased array systems. The objectives of realizing packaged single-chip active transmit antenna integrated component and single-chip receivers targeting cost reduction for Transmit and Receive components are successfully fulfilled within this project. The latest development of mass-production commercial microwave components, the latest packaging technologies and Pick-and-Place assembly techniques were used to build a passive and an active STAMP demonstrator transmit array panel. In order to be able to integrate TX and RX functions into a few IC’s a X-Band TX chip and a C-Band RX chip were successfully designed. Not only an single chip integration of a phase-shifter and HPA is shown but also a chip proving that the use of balanced amplifiers could be very helpful to build a transmitting array antenna without magnetic Isolator units. On the RX part a novel digital/analog integrated receiver chip has successfully been developed showing good performance while integrating digital driver and memory circuits with reduced chip size. In this program also studies were executed to investigate, select and test these novel packaging in the military environment. Very promising results were achieved with SiGe MMIC’s and with small QFN packages; difficulties show up using the bigger sized QFN packages. The work done within STAMP is finally reflected in working TX antenna array demonstrators. These demonstrators show the antenna on package technology and are used for measurements in order to evaluate the simulations and expected performance. In total two antenna array demonstrators are produced, one passive and one active; the latter including operational STAMP transmitting modules. The passive demonstrator is used for detailed verification of the antenna-on-package simulations; the active demonstrator is used for measuring the antenna performance (inclusive HPA/phase shifter driver) by generating active TX beam steering and measuring the beam patterns. The active demonstrator is an antenna array of 16x3 elements. Each active STAMP modules holds the antenna-on-package based on a QFN carrier carrying the developed STAMP HPA/Phaseshifter chip. The SMD boards hold the active STAMP modules and contain all the drive electronics towards the active modules. With the active STAMP array we were able to realize active TX beamforming on a 16 elements wide STAMP antenna array. All elements were calibrated and beam setting data for boresight and various offset beams were generated and measured. Scan performance was measured over 120 degrees beam range. The measurements nicely fit with designed and simulated array performance.



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The STAMP program showed a working -next generation modular- scanning array performance but also showed challenges around module assembly. Next steps for future work is directed to industrialization; a controlled and optimised process is needed for the final package and assembly, also taking into account and solving other requirements like cooling and reliability of the setup. At the start of the STAMP program the setup of a transmitting package in a array configuration had a low TRL level (around TRL1). By proving and validating working demonstrators in a laboratory environment we can say that the STAMP program pulled the technology level up to TRL3. While the whole scene around Phased Array antenna technology is working on a setup with cheaper and integrated TR-modules, in the STAMP program we proved that alternative packaging with a much higher level of integration also can fulfill the required phased array performance. With the proof of working STAMP antenna transmitters new Antenna Array designs based on PCB technology with radiating packages will bring new and cheaper phased array technology for future use.

Documents

MS7b STAMP RTP102.086 executive summary …eda.europa.eu/docs/documents/STAMP_executive_summary_1.pdf · Executive summary report Document Ident Type Rev_Iss Status 9505 ... A life