MPC560xB Architecture and · PDF fileMPC5604B (Bolero 512K) CROSSBAR SWITCH PowerPC TM e200z0 Core VReg Interrupt Controller Crossbar Masters Nexus 2+ JTAG Debug

TM

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006.

Anoop Aggarwal

MPC560xB Architecture and Peripherals

PowerPC

TMFreescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006.

Freescale Semiconductor Confidential and Proprietary Information

2

Power ISA

�Power ISA 2.03 merges previous ISA definitions into one documentation set and serves as the foundation for future generations of the architecture.



3

Freescale’s 32-bit PowerPC Automotive MCU Portfolio

Powertrain

Chassis

Safety

Body Gateways

Central Body Modules

LIN Slaves MPC560xS

MPC563xM MPC5674F

MPC5561 MPC560xP

MPC551x MPC560B/C

MPC551x MPC560B/C

MPC5561 MPC560xP

MPC55xx1

MPC5668G

MPC5121e



LIN Slaves

CAN

FlexRay Controller Nodes

Infotainment

Vehicle Communications

All MPC55xx All MPC56xx

MPC5561 MPC5567MPC551x MPC560xP

MPC560xS

MPC5121e

1 Powertrain does not include MPC5561 or MPC551x.

I.MX35I.MX31

MPC5674F

MPC5121e

MPC5123MPC5200

MPC5604B (Bolero 512K)

CROSSBAR SWITCH

PowerPCTM

e200z0Core

VReg

Interrupt Controller

Crossbar Masters

Nexus 2+

JTAG

Debug

Oscillator

Memory Protection Unit (MPU)

System Integration

FMPLL

CORE• PowerPC e200z0 core running 48-64MHz• VLE ISA instruction set for superior code density• Vectored interrupt controller• Memory Protection Unit with 8 regions, 32byte granularity

MEMORY• 512Kbyte embedded program Flash, 64KByte data flash• 64Kbyte embedded data Flash (for EE Emulation)• Up to 64MHz non-sequential access with 2WS• ECC-enabled array with error detect/correct• 48Kbyte SRAM (single cycle access, ECC-enabled)

COMMUNICATIONS• 3x enhanced FlexCAN

• 64 Message Buffers each, full CAN 2.0 spec• 4x LINFlex• 3x DSPI, 8-16 bits wide & chip selects

PIT 4ch 32bPower Mgt



48K SRAM

Communications I/O System

Crossbar Slaves

512KFlash

BootAssist

Module (BAM)

I/OBridge

3 FlexCAN

4LINFlex

1I2C

3 DSPI

• 3x DSPI, 8-16 bits wide & chip selects• 1x I²C

ANALOG• 5V ADC 10-bit resolution

TIMED I/O• 16-bit eMIOS module

OTHER•CTU (Cross Triggering Unit) to sync ADC with PWM Channels• Debug: Nexus 2+• I/O: 5V I/O, high flexibility with selecting GPIO functionality• Packages: 100LQFP, 144LQFP, 208MAPBGA (Development only)• Boot Assist Module for production and bench programming

Standby RAM

64K DataFlash

36 chADC10bit

eMIOSLite6ch IC/OC50ch PWM

CTU

TM


Clocks

Platform overview – ClocksMPC560xB CGM Clock sources

►Main Clock• 4-16 MHz External Crystal/Oscillator -> FXOSC • 16 MHz Internal RC Oscillator -> FIRC

� Default system clock after Reset� Trimmable

• Frequency modulated phased locked loop -> FMPLL

►Low Power Clock



►Low Power Clock• 32 KHz External Crystal/Oscillator -> SXOSC

� Low power oscillator� Dedicated for RTC/API

• 128 KHz Internal RC Oscillator -> SIRC� Dedicated for RTC/API and watchdog� Trimmable

Platform overview – ClocksMPC560xB Clock structure

• Internal IRC 16MHz, default clock after reset

• Frequency modulated PLL to reduce EMC

• Clock Monitor Unit for

• PLL clock monitoring : detect if PLL leaves an upper or lower frequency boundary

• Crystal clock monitoring : monitors the external crystal oscillator clock which



• Crystal clock monitoring : monitors the external crystal oscillator clock which must be greater than the internal RC clock divided by a division factor given by RCDIV[1:0] of CMU_CSR register.

• Frequency meter : measure the frequency of a RCOSC versus a known reference clock XOSC

Platform overview – ClocksMPC560xB CGM Clocking Structure

System Clock

Selector(ME)

CorePlatform

Peripheral Set 1

Peripheral Set 2

Peripheral Set 3div 1 to 16

div 1 to 16

div 1 to 16

FXOSC 4-16MHz

div 1 to 32

FIRC16MHz div 1 to 32

FMPLL

CMU

SYSCLKFXOSC_DIV

FIRC_DIV

FIRC

FXOSCRESETSAFEINTSXOSC32KHz



Peripheral Set 3div 1 to 16

SXOSC 32KHz

div 1 to 32

SIRC 128KHz

div 1 to 32

API / RTC

SWT (Watchdog)

CMU INT

FIRC_DIV

SXOSC_DIV

SIRC_DIV

CLOCK OUTdiv 1/2/4/8

CLKOUT Selector

FXOSC

FIRC

FMPLL

SIRC

SXOSC32KHz128KHz

Platform overview – ClocksMPC560xB CGM System Clock

►Provides the clock (divided or not) to the Core/Peripherals

►Selected by ME_XXX_MC register

CorePlatform

SYSCLKFXOSC



System Clock

Selector(ME)

Peripheral Set 1

Peripheral Set 2

Peripheral Set 3Enable &

div 1 to 16

Enable & div 1 to 16

Enable & div 1 to 16

FIRC

FMPLL

FIRC_DIV

FXOSC_DIV

Platform overview – ClocksMPC560xB CGM System Clock Divider Configuration Register

CTULAll DSPI modulesI2C module

All FlexCAN modules

Peripheral Set 2

ADC

All eMIOS modulesAll LINFlex modules

Peripheral Set 3Peripheral Set 1



DEx: Peripheral Set x Divider EnableDIVx: Peripheral Set x Divider x Division Value (1..15)

Platform overview – ClocksMPC560xB CGM Output Clock Description

►Clock output on the GPIO[0] (PA[0]) pin

CLOCK OUT(GPIO[0])

div 1/2/4/8CLKOUT Selector

FIRC

FMPLL

FXOSC



SELDIV: division by 1, 2, 4, 8SELCTL: clock source (XOSC, FIRC, PLL) selection

CGM

►Frequency modulated PLL



►Frequency modulated PLL

CGM Frequency Modulated PLL (FMPLL)

►The purpose of the FMPLL is to generate a 64 MHz max system clock from the FXOSC.

►The FMPLL operating modes:• Power down

• Normal

• Normal with frequency modulation

• Progressive clock switching



• Progressive clock switching

• 1:1

►These modes are controlled by two registers:• Control Register (CR)

• Modulation Register (MR)

CGM FMPLLNormal mode

►The PLL output clock frequency derives from the relation:

►

► (FXOSC x NDIV)

► (IDF x ODF)Input

divider1..15

Output divider

2/4/8/16

FMPLL =



FMPLL

Example: FXOSC = 16MHzFMPLL = 64MHz � NDIV = 4 * IDF * ODF � NDIV = 32 , IDF = 4 , ODF = 2

16MHz 64MHz

4

32

2

128MHz4MHz

Loop divider32..96

CGM FMPLL Frequency modulation• Frequency modulated FMPLL

•Modulation enabled/disabled through software•Triangle wave modulation

• Programmable modulation depth•±0.25% to ±4% deviation from center spread frequency•−0.5% to -8% deviation from down spread frequency•Programmable modulation frequency dependent on reference frequency



CGM FMPLL

►FMPLL is enabled at Mode Entry ME_xxx_MC(PLLON)

►Progressive clock switching allows to switch FXOSC input clock to PLL output clock stepping through different division factors: This means that the current consumption gradually increases and so the voltage regulator has a better response.

This mode is enabled by setting bit PLL_CR(en_pll_sw), prior to



• This mode is enabled by setting bit PLL_CR(en_pll_sw), prior to enabling the PLL by setting the bit ME_xxx_MC(PLLON)

• Divide FMPLL output by 8->4->2->1 for 8 clock cycles each time

CGM FMPLL 1:1 mode

►The 1:1 mode is selected bit by asserting the CR(mode) bit.

►Then the input clock is divided by two and switched directly to the output clock.

►



FFMPLL = FFXOSC / 2

TM


Boot Process

Device Start-up: Reset Generation Module - RGM

�There are two classes of resethandled by the RGM

� Destructive resets completely restart the MCU after a critical event� Register and memory contents are not

guaranteed

� Functional resets restart digital modules but preserve analog, flash and debugging module settings

�The RGM contains various registers



�The RGM contains various registers that reflect the status of the MCU and allow users to configure certain reset behaviours

�Resets can drive the reset pin on an event

Device Start-up: Start-Up Sequence 1/3

� POR monitors internal voltage and de-asserts itself

� Default clock is the 16MHz IRC

� Boot configuration pins are sampled by the hardware -possiblity to go into e.g. serial boot mode

Hardware checks reset



� Hardware checks reset configuration half word (RCHW)

� If hardware finds a valid RCHW (0x5A) it reads the 32-bit word at offset 0x04 = address where Start-Up code is located (reset boot vector)


� If valid RCHW not found -> BAM code is executed. In this case BAM moves this device into static mode

� “crt0.s” file contains required Start-Up code

� example Stages required within the “crt0”• Configure RCHW

• Initialise Stack Pointer (GPR1)



• Initialise Stack Pointer (GPR1)

• Initialise Small Data Area Pointers (GPR2 & GPR13)

• Write to all of SRAM to initialise Error Correction Syndrome

• Copy initialised RAM variables from Flash -> RAM – done by compiler if required

• Branch to “main”

� Application specific configuration, Initialization tools available like e.g. RAppID

During the power-up phase, all pads are forced to tristate.

After power-up phase, all pads are still tristate on cut2 with the following exceptions:

• PA[9] (FAB = Force Alternate Boot Mode) is pull-down. The device starts fetching from flash unless there is a strong external pull-up.


YFABM = 1 ABS = ?

Flash BootID in any bootSector?

Serial Boot(SBL) LINFlex

Serial Boot(SBL) FlexCAN

Flash BootFrom lowest

sector

Static Mode

No boot ID

ABS = 0

ABS = 1NO

POR



unless there is a strong external pull-up.

• PA[8] (ABS = Alternate Boot Selector) input weak pull-up (selects UART or CAN boot)

Static Mode

Hardware configuration to select boot mode

TM


Core – Programming Model

e200z0 Overview: Core Diagram (e200z0)

Instruction Unit

Instruction Buffer

BrancPC

Ins

truc

tion

Bu

s In

terfa

ce

Un

it

32

32

Addre

ss

Data

Contro

l

GPR

LR, CR,

CTR, XER

SPRInteger

Execution Unit

Multiply Unit

External SPR

Interface

CPU Control Logic

Data

Control

► Single issue architecture, 32-bit CPU

► 32-bit PowerPC Book E VLE-only

►Harvard architecture

� Independent instruction and data buses

► Multiple execution units:– Integer Unit:

► arithmetic, logical, etc. instructions

� Instruction Unit:

– single cycle execution of successful look-ahead branches

�Load / Store Unit:



Branch Unit

Load / Store Unit

PC Unit

Data Bus Interface Unit

32 32 N

Address Data Control

Ins

truc

tion

Bu

s In

terfa

ce

Un

it

N

Contro

l

Nexus Debug

Unit

OnCE / Nexus Control Logic

– pipelined for single cycle execution

– 1 cycle load latency

– Big endian support only

– Misaligned access support

�Branch processing unit:

– Dedicated branch address calculation adder

– Branch target buffer (BTB) for branch accelaration

MSb LSb

e200z0 Overview: Data Organization in Memory

Byte 0 Byte 1 Byte 2 Byte 3

Bit 0……………………………………………………………31

Big Endian Byte Ordering




Memory Address0x0000_0000

0x0000_0004

0x0000_0008

0x0000_000C



MSb0

LSb31

GPR (Rn)

► All BookE instructions are 32 bits wide.

► Power architecture is naturally Big Endian, but has switch for Little Endian.

e200z0 Core Training

►E200z0 Registers



►E200z0 Registers

e200z0 Registers

CR

CTR

Condition Register

Count Register

LR

Link Register

XER

XER Register

GPR0

GPR1

GPR31

General purpose Registers

MSR

PVR

Machine State

Processor version

PIR

Processor ID

SVR

System Version

HID0

HID1

Hardware Implementation Dependent

IVPR

ESR

Interrupt vector prefix

Exception syndrome

MCSR

Machine check syndrom register

Data Exception

Save and Restore

SRR0

SRR1

CSRR0

CSRR1

DSRR0

DSRR1

General Registers Processor Control Registers Exception Handling/Control Registers

SPR General



DEAR

Data Exception Address

DBCR0

DBCR1

Debug Control

DBCR2

DBSR

Debug Status

IAC1

IAC2

IAC4

Instruction Address Compare

IAC3

DAC1

DAC2

Data Address Compare

PID0

Process ID

MMUCFG*

Configuration (Read only) L1CFG0*

Cache configuration (Read-only)

BUCSR

BTB Control

Debug Registers Memory management Registers

Cache RegistersBTB Registers

SPRG0

SPRG1

SPR General

* Read-only for backward compatibility

e200z0 RegistersGeneral Registers

Register Description

GPR0-GPR31 Thirty-two 32-Bit GPRs (GPR0–GPR31) serve as data source or destination registers for integer instructions and provide data for generating addresses.

CTR Count register holds a loop count that can be decremented during execution of appropriately coded branch instructions. It also provides the branch target address for the Branch Conditional to Count Register (bcctr, bcctrl) instructions.

LR Link Register provides the branch target address for the Branch Conditional to Link Register (bclr, bclrl) instructions, and is used to hold the address of the



Register (bclr, bclrl) instructions, and is used to hold the address of the

instruction that follows a branch and link instruction, typically used for linking to subroutines.

XER Integer Exception Register indicates overflow and carries for integer operations.

CR Condition register

e200z0 Registers Processor Control Registers


MSR The MSR register defines state of the processor.

PVR This register is a read-only register that identifies the version (model) and revision level of the processor.

PIR This read-only register is provided to distinguish the processor from other processors in the system.

SVR Read-only register that that specifies a particular implementation of a Zen-based system by a particular business unit at their discretion.



system by a particular business unit at their discretion.

HID0, HID1 Hardware implementation-dependent registers controlling various processor and system functions (setting power modes, debug unit enable etc.)

e200z0 RegistersInterrupt Registers


SRR0

SRR1

Save / Restore Registers 0 & 1 are used to save the machine state on a non-critical interrupt. SRR0 saves the address of the instruction at which execution resumes following the end of an interrupt. SRR1 contains the contents of the MSR when the interrupt is taken.

CSRR0

CSRR1

Save / Restore registers 0 & 1 are used to save the state machine state on a critical interrupt.

DSRR0

DSRR1

Save / Restore registers 0 & 1 are used to save the state machine state on a debug interrupt when enabled HID0[DAPUEN]=1 otherwise CSRR registers are used



DSRR1

IVPR The Interrupt Vector Prefix Register together with hardwire offsets provide the address of the interrupt handler for different classes of interrupts.

DEAR The Data Exception Address Register is set to the address of the faulting instruction after most Data Storage Interrupts or Alignment Interrupts.

MCSR This register provides a syndrome to differentiate between the different kinds of conditions which can generate a Machine Check.

ESR The Exception Syndrome Register provides a syndrome to differentiate between the different kinds of exceptions which can generate the same interrupts.

e200z0 Registers Debug Registers


DBCR0-2 These registers provide control for enabling and configuring debug events

DBSR Debug event status register

IAC1-4 These registers contain addresses and/or masks which are used to specify Instruction Address Compare debug event.

DAC1-2 These registers contain addresses and/or masks which are used to specify Data Address Compare debug event.



e200z0 RegistersKey registers overview - Machine State Register (MSR)

►Manipulated during exceptions• Saved when interrupt occurs to one of the save/restore registers (SRR1,

CSRR1, DSRR1)

• Restored when returning from exception

►Accessible by mtmsr and mfmsr instructions

►Modified by System call instruction se_scKey Machine State Register Options

Bit Name Description Reset value



Bit Name Description Reset value

13 WE Wait State (Power Management) Enable 0 (Disabled)

14 CE Critical interrupt Enable 0 (Disabled)

16 EE External interrupt Enable 0 (Disabled)

17 PR Problem state (0/1 – Supervisor/User mode) 0 (Supervisor)

19 ME Machine check Enable 0 (Disabled)

22 DE Debug interrupt Enable 0 (Disabled)

e200z0 RegistersKey registers overview – General purpose registers (GPRs)

►32-bit registers

►Source or destination registers for integer instructions

►Provide data for address generating

►All arithmetic instructions that execute in the core operate on data in the general purpose registers

►GPRs registers are accessed through instruction operands



e200z0 RegistersKey register overview - Condition register (CR)

►Condition Register (CR) has eight identical 4-bit comparison result fields

►Bit-Fields reflect results of certain arithmetic operations and provides a mechanism for testing and branching.

• LT less then flag

• GT greater then flag

• EQ equal flag

• SO summary overflow



• SO summary overflow

CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7

LT GT EQ SO

Condition register

Bit field

e200z0 RegistersSpecial purpose registers (SPRs)

►Most of core registers are special purpose registers (SPRs)

►Each SPR register has the number used in the instruction syntax to access it

►Two assembly instruction are used to read and write• mfspr gpr_dest,spr_src read from special function register

• mtspr spr_dest,gpr_src write to special function register

►Few SPRs have synchronization requirements for access (ie. HID0)

►Response to invalid SPR access depends on privileged level• Illegal instruction exception

Privileged Violation exception



• Privileged Violation exception

►Example

General Alternative Simplified Description

mtspr 9,r4 mtspr CTR,r4 mtctr r4 Copy contents of gpr4 to spr9 (CTR)

mtspr 22,r0 mtspr DEC,r0 mtdec r0 Copy contents of gpr0 to spr22 (DEC)

mfspr r11,1 mfspr r11,XER mfxer r11 Copy contents of spr1 (XER) to gpr 11

mfspr r0,26 mfspr r0,SRR0 mfsrr0 r0 Copy contents of spr26 (SRR0) to gpr 0

e200z0 Registers Programmer’s model 1 of 2

►e200z0 Register are either User Mode or Supervisor Mode Registers

►PR (Problem State) Bit in MSR determines current mode that core is using

►Supervisor Mode• All Core Registers have R/W Access



►User Mode• Only User Mode Registers have R/W Access (General registers)

• Access to any Supervisor Mode Register raises privileged exception

e200z0 RegistersProgrammer’s model 2 of 2

►Entering and exiting USER mode

►USER > SUPERVISER• Trigger Software Interrupt (in INTC) or System Call Interrupt (use se_sc

instruction)

• When Interrupt is taken, MSR is changed automatically to supervisor mode.

• In ISR, mask PR bit in SRR1 and set to 0 (Supervisor Mode)



• In ISR, mask PR bit in SRR1 and set to 0 (Supervisor Mode)• When Interrupt completes (via rfi instruction) the core will be restored

to user mode

►SUPERVISER > USER• Set the PR bit in the MSR to 1

Stack grows from high to low addresses

• Only created when necessary

• Size varies as needed

• 16-byte alignment requiredCR save area (+ pad)

32-bit GPR save area

last parameter save area

last LR save area

last back chain

•••

High Addresses

Programming Model: ABI Stack Frames



CR save area (+ pad)

local variable space (+ pad)

parameter save area

LR save area

back chainr1

Low Addresses

e200z0 Core Training

►Instruction model



►Instruction model

e200z0 Instruction Model VLE Encoding Overview 1 of 2

►e200z0 uses “Variable Length Encoding” Instruction Set – VLE

►Re-encoding of the Power Architecture BookE ISA fixed 32-bit instructions

►VLE contains a mixture of 16-bit and 32-bit instructions

►VLE Instructions have exact or similar semantics to BookE instructions

►Some 32-bit BookE instructions do not need full 32-bit instruction



size►16-bit PowerPC VLE instructions encoded with se_ prefix

►32-bit PowerPC VLE instructions encoded with e_ prefix

►ExampleInstruction Description

stw BookE 32-bit instruction (not used on e200z0)

e_stw 32-bit PowerPC VLE instruction

se_stw 16-bit PowerPC VLE instruction

e200z0 Instruction Model VLE 16-Bit Instructions

►~70 16 bit instructions►VLE 16-bit encodings have same constraints as other 16-bit ISAs

• Typical VLE 16 bit instruction is 2-operand, not 3 operand

• Many zero-operand instructions encoded in 16 bits

• Access to just 16 of the 32 GPR’s (4-bit range)

• Limited literal sizes►Example



OPCODE 0b0000111 r4 OPCODE rY rX

0 5 12 15 0 5 12 15

7-bit integer limit

4-bit range on GPRs

se_li

7

4-bit range on GPRs

se_sub

e200z0 Instruction Model VLE 32-Bit Instructions

►Equivalents for (nearly) all 32-bit BookE instructions• Typical VLE 32-bit instruction is 3 operand

• Access to all 32 GPR’s

• Larger literal sizes compared to 16-bit instructions

►32-bit VLE instruction



32-bit VLE instruction• e_add16i (32-bit add immediate) instruction

►Example

OPCODE rT rA

0 6 16 3111

SI

e_add16i rT, rA, SI

e200z0 Instruction Model VLE Example – Branching

►‘Branch’ VLE Encoding Example• Require an instruction which will jump (branch) to an instruction with an

offset of 0x8 from the current instruction• e_b 0x8 - PowerPC VLE 32-Bit Encoding

• se_b 0x8 - PowerPC VLE 16-bit Encoding

OPCODE 0b000000000000000000001000

e_b 0x8

16 Mega Byte Range



OPCODE 0b000000000000000000001000

0 5 30 317 24-bit offset

OPCODE 0b00001000

0 5 158

se_b 0x8

8-bit offset

256 Byte Range

16 Mega Byte Range

TM


System Integration Unit Lite (SIUL)

PeripheralsSIUL Introduction

►Pad Control and IOMux configuration;• Intended to configure the electrical parameters and

mux’ing of each pad;• May simplify PCB design by multiple alternate

input / output functions

►GPIO ports with data control;• Different access mechanisms to the GPIO data

registers in order to allow port accesses or bit manipulation without the need of R-M-W



manipulation without the need of R-M-W operations

►External interrupt management• Allows the enabling and configuration (such as

filtering window, edge and mask setting) of digital glitch filters on each ext. IRQ;

►MCU Identification• Recognition of the exact MCU

PeripheralsSIUL Pad Control and IOMux configuration overview

►Pad Control is managed through PCR registers

►IOMux configuration is managed through:• PCR Registers (output functionalities)

• PSMI Registers (input functionalities)



SIUL Pad Control and IOMux config

IP 1

IP 2

IP 3

IP 4

b)

PCRn.OBE

PAD nPCRn.SMC

PCRn.SRC

a)

PCRn.APC

ADC ch #…

PCRn.WPE

PCRn.WPSSoC Safe Mode

PCRn.ODE

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

RSMC APC PA OBE IBE ODE SRC WPE WPS

W

Reset 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

Pad ConfigurationReg. (PCR)



IP 4PCRn.PA

IP a

PSMI.PADSEL

PCRn.IBEADC ch #…

PAD mPad Select Multiplexed Inputs (PSMI) reg.

SMC – Safe Mode Control

PeripheralsSIUL Pad Control and IOMux configuration 2/4

Alternate functions are chosen by PCR.PA bitfields:

PCR.PA = 00 -> AF0;

PCR.PA = 01 -> AF1;

PCR.PA = 10 -> AF2;

PCR.PA = 11-> AF3.

This is intended to select the output functions;



For input functions,

PCR.IBE bit must be written to ‘1’, regardless of the values selected in PCR.PA bit fields.

For this reason, the value corresponding

to an input only function is reported as “--”.

PeripheralsPSMI SIUL Pad Control and IOMux configuration 3/4

IP “n+1”

PAD j

PAD k

PAD l



PAD m

0 1 2 3 4 … 7 8 9 10 11 12 … 15 16 17 18 19 20 … 23 24 25 26 27 28 … 31

R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WPADSELn PADSEL(n+1) PADSEL(n+2) PADSEL(n+3)

PSMIn_n+3 Register

PeripheralsSIUL Pad Control and IOMux configuration 4/4

►Different pads can be chosen as possible inputs for a certain peripheral function.

0 1 2 3 4 … 7 8 9 10 11 12 … 15 16 17 18 19 20 … 23 24 25 26 27 28 … 31

R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WPADSELn PADSEL(n+1) PADSEL(n+2) PADSEL(n+3)



TM


Timed I/O (Watchdog, PIT, STM & eMIOS)

Software Watchdog Timer (SWT)

� Watchdog is used to provide a system error recovery function, e.g. from software loop traps or failing bus transaction

� Software must periodically write a servicing sequence prior to the next expiration of the watchdog timer interval to avoid reset or interrupt by watchdog

� Writing the sequence resets the timer to the specified time-out period

� Programmable selection of window mode or regular servicing



� Programmable selection of window mode or regular servicing

� The MPC560xB watchdog resides in the Safety Module

� Watchdog is default enabled• Default : Watchdog is enabled• Can be disabled by default by programming WATCHDOG_EN Bit

in Non-Volatile User Option Register (NVUSRO) Bit 31 in Shadow Flash

SWT: Overview

�32-bit time-out register to set the time-out period

�The unique SWT counter clock is the undivided slow internal RC oscillator 128 KHz (SIRC), no other clock source can be selected

�Programmable selection of window mode or regular servicing

�Programmable selection of reset or interrupt on an initial time-out

�Master access protection



�Master access protection

�Hard and soft configuration lock bits

► Regular mode

• To prevent the watchdog from interrupting or resetting, the following sequence must be performed before a timeout period:1. Write 0xA602 to the SWT_SR

2. Write 0xB480 to the SWT_SR

Note: other instructions, such as an ISR, can occur between above writes

► Window mode

• The service sequence must be performed in the last part of the time-out

SWT: Refresh



• The service sequence must be performed in the last part of the time-out period defined by the window register

• The window is open when the down counter is less than the value in the SWT_WN register

• Outside of this window, service sequence writes are invalid accesses and generate a bus error or reset depending on the value of the SWT_CR.RIA bit.

RIA – Reset upon Invalid Access - 0 = Generate a bus error- 1 = Generate a reset

PIT Timer Module (PIT) : Features

� 32-bit counter resolution clocked by system clock

� Timer can generate interrupt (DMA trigger on MPC5601/2/5/6/7B)

� Independent timeout periods for each timer

� Channel outputs can trigger ADC conversion



� MPC5602/3/4 -> 6 PITs

System Timer module (STM) : Features

The System Timer Module (STM) is a 32-bit timer designed to support commonly required system and application software timing functions.

� One 32-bit modulus up counter with 8-bit prescaler (1-256)

� Four 32-bit compare channels, each with its own interrupt vector

Main features:



� Compliant with the AUTOSAR Task Monitor scheme

� Counter can be stopped in debug mode

eMIOS260Introduction►The eMIOS260 used on BOLERO

family is based on the existing eMIOS used on 5500 power architecture parts

• Provides various modes to generate or measure timed event signals.

• 24 to 56 Channels based on 3 channel types

• One new channel mode featuring lighting applications, OPWMT

• 16-bit time base

Crossbar Switch (XBAR)

INTC

Memory Protection Unit (MPU) 8 regions

IntegerExecution

Unit

MultiplyUnit

Instruction Unit VLE

General PurposeRegisters

(32 x 32-bit)

BranchUnit

Load/StoreUnit

e200z0h Core

(C)JTAG

Debug

VREG

OSC 32K

IRC 16M

PLL

IRC 128K

OSC 4-16M



• 16-bit time base

• All other channel modes are subset of the unified channel structure on previous eMIOS.

• Consistent user interface with previous eMIOS implementation.

RAMController

SRAM(ECC)

FLASH Controller

Code Flash(ECC)

Data FLASH(ECC)

Peripheral Bridge

LINFlex3 - 8

DSPI2 - 4

FlexCAN1 - 6

ADC1016 – 57 ch

eMIOS-lite24 – 56 ch

API/RTC

PIT6 ch

STM4 ch

I2C1

SIU

SWT

BCTU

PeripheralsEMIOS channel configuration MPC5604B



Bolero MPC5605/6/7B Block Structure

�2 EMIOS Blocks – EMIOS_A and EMIOS_B

�Each Block contains 32 Unified Channels

�Common System Clock Divider

�Separate Global Prescaler

System Clock (/1,2,4,8,16)

Default /1

EMIOS_A EMIOS_B



Global Prescaler (/1, 2, 3, … 256)

Channel 0

Prescaler (/1, 2, 3, 4)

Channel 31 Prescaler (/1, 2, 3, 4)


Channel 0

Prescaler (/1, 2, 3, 4)


EMIOS_A

eMIOS260 Unified Channel Features

• Selectable time base for each counter bus

• Programmable Clock Prescaler

• Double buffered data registers and comparators

• State Machine (with mode control)

• Programmable as input or output:- Input Edge Detect as rising, falling or

toggle.



toggle.

• Programmable digital input filter

►A and B data registers are double buffered to provide a mechanism for safe update of the A and B register values

• This also enables very small pulse / period generation or measurement since updates can happen in current period

►The channel A user registers are an address mapped link to either the A1 or A2 register (determined automatically by the mode of the unified channel).

• For output modes, data is typically written to the A2 register

• For input capture modes, data is latched into either A1 or A2 depending on mode.

• All of this is transparent to the user

eMIOS260 Double Buffered A and B Registers



• All of this is transparent to the user

Comparator A

Register A1

Register A2

UCAn Register(User Accessible)

Note – Same applies to B set registers as well!

PeripheralsEMIOS Channel Types MPC5604B



PeripheralsEMIOS clocking

►Channel clocks are derived from the peripheral set clock

►There are global and channel prescalers for flexibility

• Note that both prescalers must be enabled!!!

• Caution – Only eMIOS0 channels 0-8, 16, 23, 24 and eMIOS1 channels 0, 8, 16, 23, 24 have an internal counter

►The eMIOS is clocked from the “peripheral set 3 clock” signal which provides clock dividers from 1 to 16




Peripheral Set Clock (/1..16)



PeripheralsEMIOS counter buses

►The MPC560xB family has 5 shared counter busses allowing common counter bus timing across multiple channels

• Counter Bus A is shared with all channels and driven from channel 23

• Counter bus B is shared with channels 0 to 7 and driven from channel 0

• Counter bus C is shared with channels

UC[23]

UC[16]

UC[27]

UC[24] Counter Bus E

Counter Bus A

Counter Bus D



• Counter bus C is shared with channels 8 to 15 and driven from channel 8

• Counter bus D is shared with channels 16 to 23 and driven from channel 16

• Counter bus E is shared with channels 24 to 27 and driven from channel 24

UC[15]

UC[8]

UC[7]

UC[0] Counter Bus B

Counter Bus C

PeripheralsEMIOS mode selection

EMIOS_CCR[n] Mode Fields31…….... 7 6 5 4 3 2 1 0

MODE[0:6] Mode of operation

000_0000 General Purpose Input/Output (input)

000_0001 General Purpose Input/Output (output)

000_0010 Single Action Input Capture

000_0011 Single Action Output Compare

000_0100 Input Pulse width Measurement

000_0101 Input Period Measurement

000_011b Double Action Output compare000_1000

000_1111Reserved

001_0bbb Modulus Counter

001_1000

010_0101Reserved

010_0110 Output Pulse Width Modulation with Trigger



R

W

RST: ………. 0 0 0 0 0 0 0

Mode[6:0]010_0110 Output Pulse Width Modulation with Trigger

010_0111

100_1111Reserved

101_000b Modulus Counter Buffered (Up counter)

101_0010

101_0011Reserved

101_010b Modulus Counter Buffered (Up/Down counter)

101_0110

101_1001Reserved

101_10b0 Output Pulse Width and Frequency Modulation Buffered

101_11bb Center Aligned Output Pulse Width Modulation Buffered

110_00b0 Output Pulse Width Modulation Buffered

110_0100

111_1111Reserved

Note: This is only an example.

Implemented modes may be different.

Edge detect

Edge detect

PeripheralsEMIOS - Single Action Input Capture

Returns the value of the counter bus on an edge match of an input signal .- Can use Internal or Modulus counter

- Can match on Rising, Falling or Toggle determined by state of EDPOL, EDSEL

Edge detect

$001250$001000 $0016A0

input signal

selected counter bus

FLAG pin / register

$000500 $001000 $001100 $001250 $001525 $0016A0



Notes:

• When edge is detected, flag is set and counter bus value is captured in register A2. User reads this value from UCA[n] register.

• UCB[n] = Cleared and cannot be written

register

A2 (captured) value

$xxxxxx $001000 $001250 $0016A0

Peripherals EMIOS - Single Action Output Compare

Generates an output on a counter bus match- Can use Internal or Modulus counter- Can set output to go HIGH, LOW or TOGGLE, based on the state of EDPOL and

EDSEL

$001000$001000 $001000$001100selected

counter bus

FLAG pin /

$000500

output flip-flopEDSEL=0, EDPOL=1

output flip-flopEDSEL=1, EDPOL=x

$001000 $001100 $001000$001000 $001000



$001000$001000

Notes:

• Write the desired counter bus value to create a match into UCA[n] (A2n) which is buffered into A1.

• A comparator match of A1 results in an output event, defined by status of EDPOL and EDSEL

$001000

update of A1

register

A1 value $xxxxxx

A2 value

$001000

A1 match

$001000

A1 matchwrite into A2

$001000

A1 match

Peripherals EMIOS - Double Action Output Compare

Generates an output pulse - Can use Internal or Modulus counter

- Polarity of pulse is determined by value of EDPOL

$001000

$001000$001000 $001100 $001000$001100 $001000$001000

$001000

output flip-flopEDSEL=0, EDPOL=1


FLAG pin / register

A1 value $xxxxxx

$000500

MODE[0]=1

$001100 $001000

$001000

$001100 $001000

$001000



Notes:

• Write the desired pulse leading edge into UCA[n] (A2n) and the falling edge into UCB[n] (B2n) which are buffered into A1 and B1.

• On a comparator A match, the output is set to the value of EDPOL. FLAG is set if MODE0=1

• On a comparator B match, the output is set to the inverse of EDPOL. FLAG is set

$001000$001000

update of A1 & B1

write into A2 & B2

$001100$001100

$001100

A1 match

A2 value

B1 value $xxxxxx

B2 value

B1 match

$001100

A1 match B1 match

$001100

A1 match

A

Peripherals EMIOS - Input Pulse Width Measurement

Determines the width (in counter bus clock ticks) of an input pulse width- Can use Internal or Modulus counter

- Can be configured to measure HIGH or LOW pulses by state of EDPOL bit (EDPOL=1 for HIGH)

$001100

$001000$001000

B A

$001100$001100

$001525

$001250$001250

B

$001525$001525

A

$000125

$FFFEC0$FFFEC0

B


FLAG pin / register

A2(captured) value

$xxxxxx

input signalEDPOL = 1

$000125$000125



Notes:

• Leading edge is captured into B2[n]. (EDPOL Determines if leading edge is high or low).

• Trailing edge is captured into A2[n] and Flag is set

• Pulse width is calculated by subtracting UCBn (B1) from UCAn (A2)

• Caution – If pulse has spanned a counter bus period, then need to take care to modify calculation…. Width = (UCAn + Counter Bus Period) - UCBn

$001000

$001000

$001000

$001000

Width = A2 – B1

$001250

$001250

$001250

$001250

Width = A2 – B1

$FFFEC0

$xxxxxx

$xxxxxx

value

B1 value

B2(captured) value

$xxxxxx

A1 value

$FFFEC0

$FFFEC0

$FFFEC0

Width = A2 – B1 ???

PeripheralsEMIOS - Input Period Measurement

Determines the period (in counter bus clock ticks) of an input pulse width- Can use Internal or Modulus counter

- Can be configured to measure between 2 HIGH or 2 LOW edges, determined by the state of the EDPOL bit

$001000

$001000$001000

Edge detected

$001000

$001250

$001100 $001250$001250

Edge detected

$001250

$000005

$FFFEC0 $000005$000005

Edge detected

$000125$000005selected

counter bus

FLAG pin / register

A2(captured) value

$xxxxxx

input signalEDPOL = 1



Notes:

• When the edge of the selected polarity is detected, counter value is captured into A2[n] and B2[n],

the data previously held in B2[n] is captured into A1[n] and B1[n], and Flag is set.

• Period is calculated by subtracting UCBn (B1) from UCAn (A2)

• Caution – If period of input signal has spanned a counter bus period, then need to take care to modify calculation…. Width = (UCAn + Counter Bus Period) - UCBn

$001000

$001000

$001000

$001000

$001000

Width = A2 – B1

$001250

$001250

$001250

$001250

$001250

$000005

$000005

Width = A2 – B1 ???

$xxxxxx

$xxxxxx

value$xxxxxx

B1 value

B2(captured) value

$xxxxxx

A1 value

Peripherals EMIOS - Modulus Counter Mode – UP Counter

Generates a time base which can be shared with other channels through the internal counter buses

- Can use Internal or External (input channel pin) counter

FLAG pin / register

Internal Counter (UCCNTn)

0x000000

0x0010000x000800



$000800

$001000

Notes:

• On a comparator A match, FLAG is set and the internal counter is set to value $0.

• A change of the A2 register makes the A1 register be updated at the next clock.

• Caution – If when entering MC mode the internal counter value is upper than register UCA[n] value, then it will wrap at the maximum counter value ($FFFFFF) before matching A1.

$001000 $001000

A1 match

$000800

A1 match

A1 value

A2 value $000800$000800

$000800

update of A1

write into A2 A1 match

Peripherals EMIOS - Modulus Counter Buffer Mode – UP Counter



FLAG pin / register


0x000001

0x0010000x000800



$001000

$001000

Notes:


• Allowing smooth transitions, a change of the A2 register makes the A1 register be updated when the internal counter reaches the value $1.

• Caution – If when entering MCB mode the internal counter value is upper than register UCA[n] value, then it will wrap at the maximum counter value ($FFFFFF) before matching A1.

$001000 $001000

A1 match A1 match

$000800

A1 match

A1 value

A2 value $000800$000800

$000800

update of A1

write into A2

Peripherals EMIOS - Modulus Counter Buffer Mode – UP/DOWN Counter



FLAG pin / register


0x000001

0x0010000x000800



Notes:


• Allowing smooth transitions, a change of the A2 register makes the A1 register be updated when the internal counter reaches the value $1.

• Caution – If when entering MCB mode the internal counter value is upper than register UCA[n] value, then it will wrap at the maximum counter value ($FFFFFF) before matching A1.

$001000

$001000 $001000

A1 match A1 match

$000800

A1 match

A1 value

A2 value $000800$000800

$000800

update of A1

write into A2

Peripherals EMIOS - OPWMFMB

$001000 $001000 $001000

0x0010000x000800

0x000200

B1 value

Selected counter bus

output flip-flopEDPOL=1


$001000

Generates a simple output PWM signal- Requires INTERNAL Counter

- EDPOL allows selection between active HIGH or active LOW duty cycle.



Notes:

• Duty Cycle = UCA[n] (A1) + 1, Period = UCB[n] (B1) + 1

• On Comparator A1 match, Output pin is set to value of EDPOL

• On Comparator B1 match, Output pin is set to complement of EDPOL and Internal counter is reset

• The transfers from register B2[n] to B1[n] and from register A2[n] to A1[n] are performed at the first clock of the next cycle.

• FLAGS can be generated only on B1 matches or on both A1 and B1 matches depending on MODE[5] bit.

$001000

$000200

$001000

B1 match

$001000

B1 match

$000200

B1 value

A1 value

A2 value

A1 match

$000200 $000800

update of A1

write into A2

$000800$000800

A1 match

$000200

A1 match

$000800

B1 match

$001000

$000800

Peripherals EMIOS - OPWMB

Generates a simple output PWM signal- Can use Internal or Modulus counter

- EDPOL allows selection between active HIGH or active LOW duty cycle.

$000800

0x0010000x000800

0x000200

$000600

0x0006000x000400

$000600$000600

$000600


$000800B1 value


$000800B2 value



Notes:

• Write UCA[n] (A1) with Leading Edge. Write UCB[n] (B1) with trailing edge


• On Comparator B1 match, Output pin is set to complement of EDPOL

• The transfers from register B2[n] to B1[n] and from register A2[n] to A1[n] are performed at the first clock of the next cycle.

• FLAGS can be generated only on B1 matches or on both A1 and B1 matches depending on MODE[5] bit.

B1 match B1 matchA1 match

$000200 $000400

update of A1 & B1

$000400$000400

A1 match

$000200

$000600$000600

$000400

write into A2 & B2

$000200

$000200

A1 value

A2 value

$000800B2 value

$000800

PeripheralsEMIOS - OPWMT

Generates a PWM signal with a fixed offset and a trigger signal- Intended to be used with other channels in the same mode with shared common time base

- This mode is particularly useful in the generation of lighting PWM control signals.

$000800

0x000800

$000600

0x0006000x000400

$000600

0x001000

0x000200


$000800B1 value


FLAG pin / register



$000800

Notes:

• A1[n] defines the Leading Edge, B1[n] the trailing edge, A2[n] the generation of a FLAG event


• On comparator A2 match, FLAG is set (and can allow to synchronize with other events, ie. AD conversion)

• On Comparator B1 match, Output pin is set to complement of EDPOL

• The transfers from register B2[n] to B1[n] is performed at every match of register A1

$000800

$000200

$000400

$000200

$000600

$000600$000600

$000400

$000600$000800

$000200

$000400

B1 value

A1 value

A2 value

$000800B2 value

A2 match

A1 match

B1 match

A2 match

A1 match

B1 match

write into B2

A2 match

A1 match

B1 match

$000400

$000200

Update of B2

Peripherals EMIOS - Changing Modes

► If changing an operating mode• first change the channel’s mode to mode 0 (GPIO)

• then update A[n] and B[n] registers with the correct values for the next operating mode

• then write the new operating mode to the CCR[n] register

► If a Channel is changed from one mode to another without



► If a Channel is changed from one mode to another without performing this procedure, matches can occur in random time if the contents of A[n] or B[n] were not updated.

PeripheralsEMIOS - Programmable Input Filter

• Filter Consists of a 5 bit programmable up-counter, clocked by either the channel or peripheral set clock (defined by FCK)

• Input signal is synchronised to system clock.

• When the synchroniser output changes state, the counter starts counting up

• If the synchroniser state remains stable for the desired number of selected clocks, the counter overflows on next high clock edge, counter resets and filter output changes

5-Bit Up Counter

IF3 IF2 IF1 IF0FCK

Prescaled Channel CLK

Peripheral Set CLK

CLK

SynchroniserPIN

Filter Out

Filter can be set to trigger after 2,4,8 or 16 clocks (or bypassed)



Clock

5-bit counter

Input Sig

IF[0:3] = 0010Overflow

Filter Out

1

Start

1

Start

1

Start

2 3 4

Start

1 2

Start

1 1

Start

TM


Interrupt Controller (INTC)

INTC: Features

�The INTC provides priority-based preemptive scheduling of ISRs

�Supports 134 peripheral interrupt and 8 software-configurable interrupt request sources

�Provides a unique vector for each interrupt request source

�Each interrupt source programmable to one of 16 priorities

�Preemptive prioritized interrupt requests to processor

�Low latency—3 clock cycles from receipt of interrupt request from peripheral to interrupt request to processor

�Supports the priority ceiling protocol for coherent accesses



�Supports the priority ceiling protocol for coherent accesses

�Software configurable interrupt requests to separate the work involved in servicing an interrupt request into a high-priority portion and a low-priority portion

� Low-priority portion can be used to schedule tasks with RTOS at INTC_CPR priority 0

�Two handshaking modes with the processor� Software vector mode (HVEN bit in INTC_MCR is negated)

� Hardware vector mode

Interrupt controllerMPC5604B Interrupt Structure

► Interrupt Requests from► Interrupt Controller (INTC)

CPU

8 Software

3 MCM

2 Wdog & clock

4 STM

2 RTI/API

5 Mode Entry (MC)

6 PIT

5 SIU & WPU

Critical Input

Machine Check

Data Storage

Instruction StorageINTC in Software

Interrupt Requests fromCore Exceptions (e200z0)



CPU Interrupt6 PIT

3 ADC

54 CAN

External Input

Alignment

Program

System Call

Debug

SoftwareVectorMode

CPU Core

1 IIC

28 eMIOS

15 DSPI

12 LIN

Interrupt controllerMPC560xB INTC Interrupts

► The INTC provides a mechanism to service interrupts external to the core.►

► 8 Software Settable Flags► 3 MCM (Flash & RAM)► 1 Software watchdog timer SWT► 1 FXOSC► 4 System Timer STM► 2 RTC/API► 2 SIUL (external IRQ)► 3 Wakeup Unit► 5 Mode Entry (ME & RGM)



► 5 Mode Entry (ME & RGM)► 6 PIT► 3 ADC► 54 FlexCAN (6 per module)► 1 IIC► 28 eMIOS (14 per module)► 15 DSPI (5 per DSPI) ► 12 LINFlex (3 per LINFLex)► 148 Examples of Possible IRQ Sources to Interrupt Controller

► Software Vector Mode• The CPU branches to one of the 16 core interrupt vectors (IVOR’s) which contains a

branch to an exception handler (eg IVOR4 handler)

• The exception handler is common for the majority of exceptions

� Prologue

� Identification of specific interrupt by reading a register

� Location of ISR is read from a jump table

� Branch to ISR

� Common epilogue

Optimized for code size reductionNote – Hardware

and software vector

Interrupt controllerINTC Hardware and Software Vector Mode



Optimized for code size reduction

►Hardware Vector Mode• Each interrupt has a unique vector entry containing the jump address of the ISR. The ISR

contains:

� Unique Prologue

� ISR

� Unique Epilogue

Optimized for interrupt latency

mode are only relevant to IVOR4 (INTC) exceptions

Interrupt controllerINTC Hardware and Software Vector Mode

► The interrupt vectors are located on a 4KByte boundary. • Hardware vector mode has IVPR (Interrupt Vector Prefix Register) at a 2Kbyte

offset from the software mode IVPR

Note IVPR is SPR 63

IVOR0_ISR

IVOR1_ISR

IVOR15_ISR

---



SPR 63Only bits 0..19 are written in

IVPR hence 4k boundary

2K

Interrupt controllerTypical CPU Interrupt Behaviour

Interrupt is recognized

Hardware context switch:1. SRR0*: Loaded with address of

• Next Instruction, or• Instruction causing the interrupt

2. SRR1*: Loaded with• Bits 16:31 - MSR bits 16:31

Some interrupts use CSRR[0..1] (critical) or

DSRR[0..1] (Debug) instead of SRR[0..1]



• Bits 16:31 - MSR bits 16:313. MSR: All bits are cleared except ME4. Instruction Pointer: points to unique interrupt vector

Software Interrupt handler (at interrupt vector)• Last instruction, rfi, (return from interrupt):

- Restores MSR bits 16:31 from SRR1- Restores instruction pointer from SRR0

Use rfci, rfdi when CSRR[0..1]

or DSRR[0..1] are used

► When a core exception occurs, the core will branch to one of the IVOR vectors defined in the IVPR vector table

• Each entry in the vector table contains a branch instruction to the relevant IVOR exception handler.

• The IVPR base address (IVPR bits 0..19) and current IVOR causing the exception are added to calculate the vector table address to execute the branch from.

Interrupt controllerSoftware Vector Mode Core Interrupt Details



Base Address IVPRIVOR0IVOR1IVOR2

IVOR15

IVOR3IVOR4Jump to address in

Prefix Register (IVPR) + offset of

0x40 for IVOR4

Execute branch to IVOR4 handler

Interrupt controllerSoftware Vector Mode Interrupt Handler

►The IVOR4 Interrupt handler consists of 3 main parts:

► Prologue• Save SRR’s to stack• Read IACKR to determine which INTC interrupt occurred (See next slide)• Re-enable interrupts in MSR• Save GPR’s to stack

► Jump to ISR• Branch with link to IACKR (contains ISR address, see next slide)



► Epilogue• Execute MBAR to ensure all pending data operations are complete before

restoring any registers (synchronisation process)!• Write to EOIR (Sets CPR back to 0)• Restore GPR’s• Disable Interrupts in MSR• Restore SRR’s• Execute RFI (Return to address in SRR0 and restore MSR)

Interrupt controllerSoftware Vector Mode Interrupt Acknowledge

► The INTC has a an Interrupt Acknowledge Register (IACKR) for each core valid for IVOR4 (INTC) exceptions in software vector mode.

• INTC_IACKR

• Reading this register acknowledges the interrupt has taken place and prevents the same interrupt occurring again

• Reading IACKR also calculates and returns the address of the relevant Interrupt Service Routine based on reading the 32-bit address at “VTBA + ISR Offset”



Vector Table Base Address

(VTBA)

IACKR = Contents of (VTBA + Interrupt #)

ISR0

ISR1

ISR2

ISR293

ISR3

ISRn

Interrupt controllerSoftware INTC Interrupt Example

MAIN Program

{

…….

…….

}

IVOR4 Interrupt from INTC

SRR Updated with return address and

current MSR.MSR updated to

disable further EE Int’s

IVOR4 Handler

Prologue:

(1) Save SRR’s to stack

(2) Read IACKR to:- acknowledge interrupt

(to prevent servicing same interrupt again) - automatically return

IVOR VECTOR Table

Base Address IVPR

IVOR0IVOR1

ISR VECTOR Table

Base Address VTBA

ISR0ISR1ISR2

ISR293

ISR3

ISRn

Prologue

Jump to ISR

Current Priority Register (CPR) updated With current interrupt priority to prevent pre-emption of <= priority int



- automatically return physical address of ISR

(3) Store IACKR

(4) Re enable interrupts in MSR

(5) Save GPR’s to stack

(6) Branch with link to IACKR (ISRn Address)

ISRn

{

…….

}

Jump to address in Prefix Register (IVPR) + offset

of 0x40 for IVOR4

IVPR IVOR1IVOR2

IVOR15

IVOR3IVOR4 IACKR = Contents of

(VTBA + Interrupt #)

Jump to ISR

Epilogue

Interrupt controllerSoftware INTC Interrupt Example

MAIN Program

{

…….

…….

}

Write to EOIR resets the CPR

back to previous value so lower

priority interrupts are no longer

masked

IVOR4 Handler

Epilogue:

(1) Write mbar to finish any data transfers in progress

(2) Write to EOIR (End of interrupt register)

Prologue

Jump to ISR

CPR= current priority register



(3) Restore GPR’s from stack

(4) Disable Interrupts

(5) Restore SRR’s from stack

(6) Execute RFI

EpilogueISRn

{

Context Save

…….

Context Restore

}

RFI Causes:(1) Branch back to

origin (held in SRR0)(2) Restore of original

MSR from SRR1

Interrupt controllerHardware Vector Mode Details

► In hardware vector mode, IVOR4 is not used!• Each INTC interrupt has a unique 4 byte vector entry in the vector table at

IVPR+2KB

• The table entry is calculated by adding the 4 byte vector to the IVPR

• There is no common handler and each interrupt ISR has it’s own prologue and epilogue



Interrupt controllerHardware Interrupt Example

MAIN Program

{

…….

…….

}

Interrupt_n

SRR Updated with return

address and current MSR

MSR updated to disable further

EE Int’s

VECTOR Table

Base Address IVPR + 2KB

b_handler_0b_handler_1b_handler_2b_handler_3

Current Priority

handler_n

Prologue

handler_0

Prologue

ISR

Epilogue

---

Prologue saves SRR registers

and GPR as per software vector

mode



Jump to address vector calculated as IVPR + 0x800 + (Vector x 4)

b_handler_293

b_handler_n

Current Priority Register (CPR) updated with

current interupt priority to

prevent pre-emption of <=

priority int

ISR

Epilogue

handler_293

Prologue

ISR

Epilogue

---Epilogue follows same format as

per software vector mode

INTC Software & Hardware Vector Modes

handler_0 prolog

Address Instructions

IVPR + IVOR4 prolog

(including branch to

vector address using IACKR to get vector

then bl ISR_n)

epilog

IRQ ntaken

SoftwareVector Mode

ISR_0 ISR•••

ISR_n ISR•••

ISR_511 ISR

Address Instructions1,2

VTBA b ISR_0

b ISR_1

…

b ISR_n

…

b ISR_511



Address Instructions1

IVPR + 0x00 b handler_0

…


…


…

IVPR + n(0x10) b handler_n

…

IVPR + 0x1FF0 b handler_511

handler_0 prolog

ISR

epilog

handler_n prolog

ISR

epilog

handler_511 prolog

ISR

epilog

IRQ ntaken

.

.

.

HardwareVector Mode

Notes: 1. “b ISR_n” and “b handler_n” instructions

are technically part of the handlers.2. “b ISRn” instruction alignment in

software vector mode assume INTC_MCR[VTES]=0

.

.

.

SW vs HW Vector Mode Handler

Software Vector Mode (HVEN = 0) Hardware Vector Mode (HVEN = 1)

HW: - Backs up machine state to SRR0:1- Disables interrupts except CE, ME, DE- Takes External Input Interrupt based on IVPR and offset 0x40 (for “IVOR4”)

HW: - Backs up machine state to SRR0:1- Disables interrupts except CE, ME, DE- Takes unique IRQ vector based on IVPR and offset which matches INTVEC

SW Prolog: - Saves SRR0:1*- Reads INTC_IACKR[INTVEC]- Re-enables MSR[EE]*- Saves other registers

SW Prolog: - Saves SRR0:1*

- Re-enables MSR[EE]*- Saves other registers



- Saves other registers - Saves other registers

SW:- branches per INTC_IACKR[INTVEC]

SW ISR (clears interrupt flag) SW ISR (clears interrupt flag)

SW Epilog:- Executes mbar to ensure IRQ flag cleared- Restores most registers- Disables EE* and writes to INTC_EOIR - Restores remaining registers and returns (rfi)

SW Epilog:- Executes mbar to ensure IRQ flag cleared- Restores most registers- Disables EE* and writes to INTC_EOIR - Restores remaining registers and returns (rfi)

* When nesting

TM


UART (LINFlex)

Peripherals LINFlex►Features:

• Supports LIN protocol version 1.3, 2.0, 2.1 and J2602• UART mode

� 7/8-bit data, parity/no-parity, 1 or 2 stop bit� LSB first

►LIN Management• Initialisation, Normal and Sleep• Maskable interrupts• Wake-up event on dominant bit detection• 8-bit counter for time-out management• Software-efficient data buffer interface mapping at a unique address

space►LIN Master Mode

• Autonomous message handling• Once the software has triggered the header transmission, no further

intervention needed:� until the next header transmission request in transmission mode � until the checksum reception in reception mode

SCI / LINSCI / LIN



� until the checksum reception in reception mode►LIN Slave Mode (only LINFlex0 on Bolero is capable of slave mode)

• Software intervention needed only to:� Trigger transmission, reception or discard depending on the

identifier,� Fill the buffer (transmission) or get data from buffer (reception).

• In Filter mode Software intervention needed only to:� Fill the buffer in transmission,� Get data from buffer in reception.

►UART mode• Full duplex; Character length 7 & 8 bits; opt parity, 1 or 2 stop bits• 4 byte Tx and Rx buffers• 3 interrupt sources : error, Rx, Tx• LSB first

UART OverviewUART mode

►Mode• Full Duplex• 8-bit / 9-bit• Even / Odd parity

►Transmit Buffer• Depth configurable from 1 to 4

►Receive Buffer• Depth configurable from 1 to 4

►Error

TRANSMITBUFFER

4 BYTES

CONTROLSTATUS

REGISTERS

RECEIVEBUFFER

4 BYTES



►Error• Parity• Overrun

►Transmission starts when DATA0 (least significant data byte) is programmed.

►The number of bytes transmitted is equal to the value configured by the TDFL[0:1] bits in the UARTCR LIN TX LIN RX

UART/SCI CORE

UART Features

• Full duplex communication• 8- or 9-bit char with parity• One or two stop bits• Non-Return-to Zero data format encoding• 4-byte buffer for reception, 4-byte buffer for transmission• 8-bit counter for timeout management



• 8-bit counter for timeout management• Fractional baud rate generator• Loop-back and self test mode• 3 interrupt sources : Error, Rx, Tx

UART Mode Control Register (UARTCR)

TDFL[0:1] - Transmit data field length (Tx Buffer size range from 1 to 4)RDFL[0:1] – Receive data field length (Tx Buffer size range from 1 to 4)RXEN – Receive enable/disableTXEN – Transmitter enable/disableOP – Even/odd parity



OP – Even/odd parityPCE – Parity/transmit check enable/disableWL – 7 or 8 data bits with parityUART – LIN /UART mode

UART Mode Status Register (UARTSR)

This register contains UART mode status flags:• SZF - Stock at zero flag• OCF - Output compare flag• PEn – Parity error in received char n (1 flag for each of 4 received char n• RMB – Release message buffer (Buffer is either free or ready to be read)• FEF – Framing error flag



• FEF – Framing error flag• BOF – Buffer overrun flag• RPS – UART current receive pin state (LINRX)• WUF – Wakeup flag (An edge is detected a edge on the LINRX pin• DRF – Data reception complete flag• DTF – Data transmission complete flag • NF – Noise flag

Flags must be cleared by writing ‘1’s to them.

UART Mode

UART Transmit Process:1- Select the Baud Rate by writing the BAUD Register

2- Select UART Mode in UART control Register (UARTCR), select parity type (Odd/Even) & char length (8/9 bit)

3- Set the Transmit Enable bit in UART control Register (UARTCR)

4- Write the message to transmit into the transmit buffer (Max # = 4 bytes)



5- Write the Transmit Data Length field in the UARTCR

UART ModeUART Receive Sequence

• Select UART Mode in the UARTCR

• For the receiver to become active, exits Initialization mode and sets the RXEN bit in the UARTCR.

• Once the programmed number (RDFL bits) of bytes has been received, the DRF bit is set in UARTSR and an interrupt is generated, if enabled.

• If a parity error occurs during reception of any byte, then the corresponding PEx bit in the UARTSR is set but no interrupt is generated.



the UARTSR is set but no interrupt is generated.

• If a framing error occurs in any byte (FE bit in UARTSR is set) then an interrupt is generated if the FEIE bit in the LINIER is set.

• If the last received frame has not been read from the buffer (that is, RMB bit is not reset by the user) then upon reception of the next byte an overrun error occurs (BOF bit in UARTSR is set) and one message will be lost.

• Which message is lost depends on the configuration of the RBLM bit of LINCR1.

TM


FlexCAN

Control Area Network

Introduction

� Up to 6 FlexCAN modules with 64 message buffers

� Full Implementation of the CAN protocol specification Version 2.0B and ISO Standard 11898

• Standard and Extended ID frames and Remote Frames• Zero to eight bytes data• Programmable bit rate up to 1 Mb/sec

� Individual Rx Mask Registers per Message Buffer



� Full featured Rx FIFO• Storage capacity for 6 frames and internal pointer handling

� Powerful Rx FIFO ID filtering• Capable of matching incoming IDs against 8 extended, 16 standard or 32 partial

(8 bits) IDs, with individual masking capability

Introduction (Cont’d)

� Programmable acceptance filters for receive message buffers

�Arbitration scheme according to message ID or message buffer number

�Message buffers and errors can cause interrupts (maskable)

�Short latency time for high priority transmit messages

�Unused Message Buffer space can be used as general purpose RAM

CAN clock from Either Internal (PLL) or External Source (OSC)



�CAN clock from Either Internal (PLL) or External Source (OSC)

�Programmable loop-back for self test operation

�16-bit time Stamp

�Independent of the transmission medium

TM


Memories: Flash, SRAM

Memories: Flash and SRAM overview

RAM features:

up to 96KB (MPC5607B) general purpose SRAM

Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of memory

User transparent ECC encoding and decoding for byte, half word, and word

FLASH features:

� up to 1.5MB Code Flash (MPC5607B)

� up to 64k Data Flash on Bolero; same emulated EEPROM concept for most products of the Bolero family (sectorization; software compatibility; memory mapping)

� 64-bit programming granularity (can change value from 1�0 only)



decoding for byte, half word, and word accesses

32-bit ECC with single-bit correction (and visibility), double bit detection for data integrity

ECC is checked on reads, calculated on writes

change value from 1�0 only)

� Read-while-write with Code and DataFlash or by RWW feature

� Erase granularity is Sector size

� 64-bit ECC with single-bit correction (and visibility), double bit detection for data integrity

TM


ADC, CTU

ADC overview10-bit ADC resolution, on MPC5605/6/7B additional 12 Bit ADC

• Supports conversions time down to 650ns

• internal clock will be system clock/2

• Up to 36 single ended inputs channels, expandable to 64 channels with external multiplexers

• Internally multiplexed channels

— 10-bit ± 2 counts accuracy (TUE) available for 16ch

— 10-bit ± 3 counts accuracy (TUE) available for up to 20ch

• Externally multiplexed channels

— 10-bit ± 3 counts accuracy (TUE) available for up to 32ch

— Internal control to support generation of external analog



— Internal control to support generation of external analog multiplexer selection

• Dedicated result register available for every internally and externally muxed channel

• 3 independently configurable sample and conversion times for high occurrence channels, internally muxed channels and externally muxed channels

• Support for one-shot, scan, injection and triggered injected (CTU) conversion modes

• Independently configurable parameters for channels

ADC Block Diagram

End of conversion

End of injection

Threshold

ADC data registers

.

.

.

D1

D0

ANALOG

MUX

SUCCESSIVE APPROXIMATION A/D CONVERTER

ANALOG

MUX10 bit

Converter

SAMPLE&

HOLD

AIN0AIN1

AINx



Trigger event for injected conversion

The CTU will automatically signal the channel to be converted by hardware

Threshold Violation

Interrupts

ADC_PRE-EMPTS

D95

D94

ADC_CONTROL

Analogwatchdog

MUX

Cross triggering Unit

EMIOSTimer channels

ADC Block Diagram



PeripheralsExternal ADC multiplexing

►The ADC offers hardware support for external multiplexing

► Each of the 4 dedicated internal channels (ANX pins) can support up to 8 external multiplexed channels, yielding up to 32 channels with dedicated internal result registers

► 3 external multiplexer select channels (MA[0-2], PE[5-7]) are provided in the Bolero pinout

Mux

AIN64

AIN65

AIN70

32 (ANP + ANS)AIN0 – AIN 15

AIN32 – AIN47



MU X

Mux Control

ADC

AIN70

AIN71

Mux

AIN72

AIN73

AIN78

AIN79

Mux

AIN80

AIN81

AIN86

AIN87

Mux

AIN88

AIN89

AIN94

AIN95

36

4 ANX

MA[0-2]

ADC - Normal Channel Conversion

�Normal conversion mask registers (NCMR)� Each channel can be individually enabled by setting ‘1’ in the corresponding field of NCMR

registers

� Mask registers must be programmed before starting the conversion and cannot be changed until the conversion of all the selected channels ends

�Can be started in two ways:� By software—The conversion chain starts when the NSTART bit in the MCR is set.

� By trigger—An on-chip internal signal triggers an ADC conversion. The conversion is started if and only if the NSTART bit in the MCR is set and the programmed level on the



started if and only if the NSTART bit in the MCR is set and the programmed level on the trigger signal is detected.

114

ADC - Normal Channel Conversion contd.

�When the normal conversion starts� NSTART bit in the MCR is reset, allowing the software to program a new start of

conversion

� New requested conversion starts after the running conversion is completed.

�Two operating modes� One Shot (MODE = 0)

� Scan (MODE = 1)



115

ADC – Injected Channel Conversion

�A conversion chain can be injected into the ongoing Normal conversion by configuring the Injected Conversion Mask Registers (JCMR)

�This injected conversion can only occur in One Shot mode and interrupts the normal conversion

�The injected conversion can be started using two options:� By software setting the JSTART bit in the MCR

� By an internal on-chip trigger signal, setting the JTRGEN bit in the MCR



116

ADC – Description contd.

�Interrupts� EOC (end of conversion) interrupt request

� ECH (end of chain) interrupt request

� JEOC (end of injected conversion) interrupt request

� JECH (end of injected chain) interrupt request

� EOCTU (end of CTU conversion) interrupt request

� WDGxL and WDGxH (watchdog threshold) interrupt requests

�Aborting a conversionBy setting the ABORT bit in the MCR



� By setting the ABORT bit in the MCR

� Current conversion is aborted and the conversion of the next channel of the chain is immediately started

� If the last channel of a chain is aborted, the end of chain is reported generating an ECH interrupt.

� In Scan Mode, current chain conversion can be aborted by setting the ABORTCHAIN bit in the MCR; ECH interrupt is generated to signal the end of the chain.

117

Programmable Analog Watchdog

►Programmable UPPER and LOWER threshold

►Dedicated ADC (WD) Interrupt on UPPER and/or LOWER threshold violation

►Can be used in a lighting application to trim SMARTMOS devices to prolong LED life

• Use EMIOS (OPWMT mode) -> CTU -> ADC to continually monitor LED voltage• 0% CPU loading• Only use CPU in event of ADC watchdog interrupt





CTU LiteCTU Lite

PeripheralsCTU Lite Purpose

►The Cross Triggering Unit Lite on the Bolero family is a link between timers (eMIOS or PIT) and the ADC

►The CTU Lite automatically transforms timer events into ADC conversions without main CPU intervention



►The real-time behavior (synchronization) between timer events and ADC conversions is guaranteed

PeripheralsCTU Lite Block Diagram



eMIOS A0 Ch0 Trig

ADC Trigger

ADC Done

ADC Control

eMIOS A23 Ch23 Trig

eMIOS B0 Ch29 Trig

eMIOS

CTU

MPC5602/3/4B eMIOS260/OPWMT Trigger event



eMIOS B23 Ch52 Trig ADC

PIT

PIT3 Ch28 Trig

PIT2 Injection trigger

eMIOS - OPWMT Mode

Period

B1

C1

A1

Match A1

Match A2Match B1



Period: the period of the PWM is defined by a Modulus Counter channel.

A1 Value: define the leading edge (or shift) of the PWM channel. Buffering is not needed as the value of the shift must not changed on the fly.B1 Value: define the trailing edge (or duty cycle) of the PWM channelB2 Value: buffered value of trailing edgeB1 update: transfer from B2 to B1 takes place at A1 matchEDPOL: define the output polarityA2 Value: define the sampling point for the analog diagnostic. It can be configured anywhere within the PWM period.

Output Pin

PeripheralsCTU Lite Features

CTU features details:

• 64 timer events

• Each timer event can be assigned corresponding ADC channel

• Only one ADC conversion can be triggered at a time

• HW arbitration when simultaneous event occur

• Event priorities are HW defined

• Single cycle delayed trigger output. The trigger output is a combination of 64



• Single cycle delayed trigger output. The trigger output is a combination of 64

(generic value) input flags/events connected to different timers in the system.

• Maskable interrupt generation whenever a trigger output is generated

• One event configuration register dedicated to each timer event allows to define

the corresponding ADC channel

• Acknowledgment signal to eMIOS/PIT for clearing the flag

• Synchronization with ADC to avoid collision

TM


Deserial Serial Peripheral Interface

DSPI

PeripheralsSPI Overview

► High speed, full duplex, three wire synchronous interface

► Master and slave modes supported

► Six Peripheral Chip Selects

• Expandable to 64 with external demultiplexer

• Deglitching support of up to 32 chip selects when external mux used



used

► SPI Queue support

• Buffered transfers using 4 deep Tx FIFO and 4 deep Rx FIFO for regular SPI modules

• FIFO visibility for debugging

► 6 Interrupt conditions

DSPI: FIFO’s• Separate 4 message entry Rx and Tx FIFO

Tx Data Rx DataTx Command

Tx FIFO PUSHR

TXCNT# FIFO Entries

TXNXTPT

Rx FIFO POPR

RXCNT# FIFO Entries

POPNXTPT

Command Data

Status Reg Status Reg

RX Data



127

TX FIFO Fill

TX FIFO Underflow(Slave mode)

RX FIFO Overflow

Tx Shift Reg Rx Shift Reg

• Tx or Rx FIFO can be manually flushed (CLR_TXF or CLR_RXF in MCR)

• FIFOs can be individually disabled providing simple double buffered operation

DSPI: CTAR

► 8 Clock and transfer Attributes registers allow the transfer characteristics of each SPI message to be defined:

• Frame size of message (4-16 bits)

• Baud rate selection

• SCK Clock Polarity (inactive state of clock)



128

• SCK Clock Polarity (inactive state of clock)

• SCK Phase (defines active clock edge for data capture / change)

• Transmission order – LSB or MSB transferred 1st

• Delay between assertion of Peripheral Chip Select and 1st SCK edge

• Delay between assertion of last SCK edge and negation of chip select

• Delay between transfer frames

► The desired transfer characteristics (stored in the CTAR registers) are then called directly via the CTAS field in the TX buffer command field

DSPI: IRQ Request Sources

Transmit Receive

TFFF: Tx FIFO not full – “Fill Flag” (IRQ or DMA)

RFDF: Rx FIFO not empty - “Drain Flag”(IRQ or DMA)

TCF: Transfer of current frame complete(IRQ)

RFOF: Frame received while FIFO full(IRQ)

EOQF: End of queue reached (IRQ)

TFUF: Attempt to transmit with empty FIFO



INTC DSPI

Interrupt Requests:TFUF,RFOFEOQFTFFFTCFRFDF

TFUF: Attempt to transmit with empty FIFO(IRQ)

TM


Debugging, Tools

CROSSBAR SWITCH

PowerPCTM

e200z0Core

VReg

Interrupt Controller

Crossbar Masters

Nexus 2+

JTAG

Debug

Oscillator

Memory Protection Unit (MPU)

System Integration

FMPLL

PIT 4ch 32b

MCM

Power Mgt

Debug, Software & ToolsMPC560xB debug support – JTAG/Nexus2+

Includes Nexus Class 1 (i.e. JTAG)

• Standard interface

• High speed

• Run control

• Flexible breakpoint and watchpoint

set-up (4 IAC, 2 DAC)

• register/memory R/W

• minimum of 6 pins required

Class 2 adds the following (only on 208



CT

U

32K SRAM

Communications I/O System

Crossbar Slaves

512KFlash

BootAssist

Module (BAM)

I/OBridge

3 FlexCAN

4LINFlex

1I2C

3 DSPI

Standby RAM

64K DataFlash

36 chADC10bit

eMIOSLite6ch IC/OC50ch PWM

Class 2 adds the following (only on 208

packages):

• Full duplex communication

• Non-intrusive program trace

• Ownership trace

• Watchpoint messaging

And Class 2+ provides (only on 208

packages):

• Read/Write access to memory

locations while CPU is running

SW and Tools Market Coverage

Autosar MCAL 2.1Autosar environment

(SW & Tools)Autosar BSWAutosar MCAL 3.0

Autosar OS

FlexRay Drivers

LIN 2.1 Drivers

J2602 Drivers

General Motor Control

Flash Drivers

FEE Drivers

Developed in house

3rd Party ownership

Developed offshore

Vector CAN Driver

MC Complex Drv

Graphic Library

Stepper Motor Drivers

Sound Generation DrvSoftware Drivers

Software LibrariesDSP lib

eTPU+ Libs

Autosar OS Tresos Auto Core



Starterkit and evaluation boards

Tools

General Motor Control eTPU+ Libs

RAppID Init

RAppID Toolbox

Compiler & Debugger

GHS Compiler

GNU Compiler

Lauterbach Debugger

EVB Mini Modules

iSystem Debugger

PLS Debugger

P&E Debugger

GHS Time Machine

System Simulation

Simulink Support

Cosmic eTPU Compiler

Adapters

Wind River Compiler CodeWarrior Compiler

Evaluation boards



Debug, Software & ToolsXPC56xxEVB - Evaluation System

►XPC Evaluation board for XPC56xx devices. Allow to evaluate and develop the whole range of XPC devices.

• Full modular design: motherboard, mini-module for each device, standardized connectors

• Standard communication transceivers and connectors



transceivers and connectors• User’s buttons, jumpers and LED’s• Device mini-module connector

Nexus Class 0 – JTAG Interface for MPC55xx/56xx

►The USB Multi link is a Nexus Class 0 = JTAG Interface



►The USB Multi link is a Nexus Class 0 = JTAG Interface

►MULTILINK Interface is delivered with XPC560BKIT144/176/208 Starter Kits.

►It can also be purchased separately.

Standalone Flash Programmer



►The Cyclone Max is a standalone Flash Programmer that can save several images.

►Ethernet or USB interface

►It can also be purchased separately

►Other third party programmer, e.g. PROMIK are also available

Development Tools – An Existing Ecosystem

Compilers Debuggers Simulators Eval Boards

Initialization

Tools

Modeling and

Code

�(v2.2) works w/ any

debugger�

� � �

� �

�

� �

CodeWarrior

Green Hills

Wind River

GNU

Lauterbach



� �

� �

�

�

�

�

dSpace

MathWorks

Lauterbach

iSystem

P&E Micro

RAppID Init

TM



Documents

MPC560xB Architecture and · PDF fileMPC5604B (Bolero 512K) CROSSBAR SWITCH PowerPC TM e200z0 Core VReg Interrupt Controller Crossbar Masters Nexus 2+ JTAG Debug