Motivation for CDR: Deserializer (1)gram.eng.uci.edu/faculty/green/public/courses/270c/... · 2016-09-19 · t Tb = 2 + 1 2 VP Vswing = 2 t Tc 1 VP Vswing = +( 1)- + VP Vswing = 0.25

EECS 270C

Spring 2008

Prof. Michael Green

Univ. of California, Irvine

1

Motivation for CDR: Deserializer (1)

If input data were accompanied by a well-synchronized clock, deserialization

could be done directly.

Input clock

Input data

channel

÷2 ÷2

1:2

DMUX

1:2

DMUX

1:2

DMUX

EECS 270C

Spring 2008

Prof. Michael Green


2

• Providing two high-speed channels (for data & clock) is expensive.

• Alignment between data & clock signals can vary due to different channel

characteristics for the different frequency components. Hence retiming

would still be necessary.

Clock

Data

input data Clock

Recovery

circuit

retimed data

recovered clock

PLLs naturally provide synchronization between external and internal timing sources.

A CDR is often implemented as a PLL loop with a special type of PD...

Motivation for CDR (2)

EECS 270C

Spring 2008

Prof. Michael Green


3

RZ spectrum has energy at 1/Tc conventional phase detector can be used.

f

S

xf( )

1

Tb

Return-to-Zero vs. Non-Return-to-Zero Formats

NRZ

RZ

1 0 1 1 0 1 0

NRZ spectrum has null at 1/Tc ??

Tb

f

2

Tb

3

Tb

2

Tb

S

xf( )

EECS 270C

Spring 2008

Prof. Michael Green


4

Phase Detection of RZ Signals

VdataVRCK

Vd

Vdata

VRCK

Vd

• Phase detection operates same as for clock signals for logic 1.

• Vd exhibits 50% duty cycle for logic 0.

• Kpd will be data dependent.

EECS 270C

Spring 2008

Prof. Michael Green


5

Phase Detection of NRZ Signals

Vdata

VRCK

Vd

Vdata

VRCK

Vd

Since data rate is half the clock rate, multiplying phase detection is ineffective.

• RZ signals can use same phase detector as clock signals

• RZ data path circuitry requires bandwidth that is double that of NRZ.

• Different type of phase detection required for NRZ signals.

EECS 270C

Spring 2008

Prof. Michael Green


6

Idea: Mix NRZ data with delayed version of itself

instead of with the clock.

Example: 1010 data pattern (differential signaling)

1

2Tb

1

Tb

• • •

• • •

• • •

XX

= =

Tb

3

2Tb

5

2Tb

fundamental generated

2

Tb

1

2Tb

3

2Tb

5

2Tb

EECS 270C

Spring 2008

Prof. Michael Green


7

Operation of D Flip-Flips (DFFs)

CMOS transmission gate:

D

CK

CK

CK

CK

QI

latch:

D

CK

CK

CK

CK

QICK

CK CK

CK

Q

Master Slave

DFF:

Ideal waveforms:

D

CK

Q

D0 D1 D2

D0 D1 D2

Symbol:

D Q

No bubble Q changes following rising edge of CK

EECS 270C

Spring 2008

Prof. Michael Green


8

DFF Setup & Hold Time

tsetup thold

When a data transition occurs within the setup & hold region, metastability occurs.

D

CK

Q

At CK rising edge, the master latches and the slave drives.

EECS 270C

Spring 2008

Prof. Michael Green


9

DFF Clock-to-Q Delay

D

CK

CK

CK

CK

QICK

CK CK

CK

Q

Master Slave

D0 D1 D2

D0 D1 D2

D

CK

Q

tck-q

tck-q is determined by delays of tgate and

inverter.

EECS 270C

Spring 2008

Prof. Michael Green


10

Din

RCK

P

Q

Q

P

D0

D0

D1

D1

D2

D2

D3

D3

D4

D1 D2 D3

D0 D1 D2 D3

D0 D1 D2 D3

D0 D1 D2 D3

D0

D1

D1

D2

D2

D3

D3

D4

Din

RCK

Delay between Din to Q is related to phase between Din & RCK

Realization of Data/Data Mixing :

RCK early: RCK synchronized:

Same as Din,

synchronized with RCK

EECS 270C

Spring 2008

Prof. Michael Green


11

Define zero phase difference as a data transition coinciding with RCK falling edge;

i.e., RCK rising edge is in center of data eye.

2

=t

Tb

1

2

Q

P

Din

RCK

RCK early ( < 0): RCK synchronized ( = 0):

Tb

t

Tb

t

t =Tb

2+

1

2

EECS 270C

Spring 2008

Prof. Michael Green


12

Din

RCK

P

Q

0101… pattern: 0011… pattern:

Phase detector characteristic also

depends on transition density:

Q

P

Din

RCK

VP =Vswing 2t

Tb

1

VP =Vswing

t

Tb

1

In general,

VP =Vswing 2t

Tb

1

where average transition density

EECS 270C

Spring 2008

Prof. Michael Green


13

t

Tb

=2

+1

2

VP

Vswing

= 2t

Tc

1

VP

Vswing

= + ( 1)

- +

VP

Vswing

= 0.25 = 0.5

= 1

Kpd =

= 0VP

Vswing

= 1

Both slope and offset of phase-voltage characteristic

vary with transition density!

Constructing CDR PD Characteristic

slope:

intercept:

EECS 270C

Spring 2008

Prof. Michael Green


14

To cancel phase offset:

Din

RCK

P

Q

R

QR

D0 D1 D2 D3

D0 D1 D2 D3

Q

RCK

QR

R

Kpd still varies with ,

but offset variation cancelled.

C. R. Hogge, “A self-correcting clock recovery circuit,”

IEEE J. Lightwave Tech., vol. 3, pp. 1312-1314, Dec.

1985.

Always 50% duty cycle;

average value is ( 1) Vswing

-+

VP VR

Vswing

+1

-1

= 1

= 0.5

EECS 270C

Spring 2008

Prof. Michael Green


15

Transconductance Block

ISS ISS

P+ P- R- R+

Iout+ Iout-

EECS 270C

Spring 2008

Prof. Michael Green


16

Due to inherent mixing operation, Hogge PD is not a good frequency

detector. A frequency acquisition loop with a reference clock is

usually needed:

J. Cao et al., “OC-192 transmitter and receiver in 0.18μ

CMOS,” JSSC. vol. 37, pp. 1768-1780, Dec. 2002.

EECS 270C

Spring 2008

Prof. Michael Green


17

Non-Idealities in Hogge Phase Detector:

A. Clock-to-Q Delay (1)

Din

RCK

P

Q

R

QR

Din

RCK

Q

QR

P

R

tck-Q

tck-Q

EECS 270C

Spring 2008

Prof. Michael Green


18

Din

RCK

Q

QR

P

R

tck-Q

tck-Q

VP VR

Vswing

+

-os

os

= 2tck Q

Tc



Result is an input-referred phase offset:

EECS 270C

Spring 2008

Prof. Michael Green


19

Din

RCK

tck-Q

CDRDin

Dout

RCK

Phase offset moves RCK away from

center of data, making retiming less

robust.



EECS 270C

Spring 2008

Prof. Michael Green


20



Din

RCK

P

Q

R

QR

tck-Q

tck-Q

t

Set t t

CK Q

D t

Din

D t

RCK

Q

QR

P

R

Use a compensating delay:

EECS 270C

Spring 2008

Prof. Michael Green


21


B. Delay Between P & R (1)

Din

RCK

P

Q

R

QR

Din

RCK

Q

QR

P

R

P and R are offset by 1/2 clock period

EECS 270C

Spring 2008

Prof. Michael Green


22

P

R

Din

RCK

P

Q

R

QR

Vcontrol

to VCO



Average value of Vcontrol is

well-controlled, but resulting ripple

causes high-frequency jitter.

EECS 270C

Spring 2008

Prof. Michael Green


23

Idea: Based on R output,

create compensating pulses:

Din

RCK

P

R

P

R

DFF

latch

latch

latch

Din

RCK

Q

QR

P (up)

R (dn)

Vcontrol

Standard Hogge/charge pump

operation for single input pulse:



EECS 270C

Spring 2008

Prof. Michael Green


24

Din

RCK

P

R

P

R

DFF

latch

latch

latchQ4

Q3

Q2

Q1

Din

RCK

Q4

Q3

Q2

Q1

Vcontrol

P (up)

R (dn)

P’(dn)

R’(up)

Cancels out effect of next pulse



EECS 270C

Spring 2008

Prof. Michael Green


25

Other Nonidealities of Hogge PD (1)

PD

Dif

fere

nti

al

Ou

tpu

t (m

V)

0

-20

-40

-60

60

40

20

0 10p 20p 30p 40p 50p-30p-40p-50p

-20p -10p

Data Delay in regard to Clock (s)

response from

ideal linear PD

simulated result

of one linear PD

EECS 270C

Spring 2008

Prof. Michael Green


26

Effect of Transition Density:


EECS 270C

Spring 2008

Prof. Michael Green


27

Effect of DFF bandwidth limitation:


EECS 270C

Spring 2008

Prof. Michael Green


28

Effect of XOR bandwidth limitation:

Since the PD output signals are averaged, XOR bandwidth limitation has negligible effect.


EECS 270C

Spring 2008

Prof. Michael Green


29

Effect of XOR Asymmetry:


EECS 270C

Spring 2008

Prof. Michael Green


30

Binary Phase Detectors

Idea: Directly observe phase alignment between clock & data

Clock falling edge early:

Decrease Vcontrol

Clock falling edge late:

Increase Vcontrol

Clock falling edge centered:

No change to Vcontrol

Ideal binary

phase-voltage characteristic: +1

-1

VP

Vswing

Also known as

“bang-bang” phase detector

EECS 270C

Spring 2008

Prof. Michael Green


31

D Flip-Flop as Phase Detector

Early clock:

Data transitions align

with clock low

Late clock:

Data transitions align

with clock high

Din

RCK

Din

RCK

RCK

D

in

VP

VPRCK

D

in

D

in

D

in

=

Realization using double-clocked DFF; note

that RCK/Din connections are reversed:

Top (bottom) DFF detects on Din rising (falling)

edge; DFF selected by opposite Din edge to

avoid false transitions due to clock-q delay.

EECS 270C

Spring 2008

Prof. Michael Green


32

What happens if =0?

tsetup

thold

D

CK

Q

• If transition at D input occurs within

setup/hold time, metastable operation

results.

• Q output can “hang’’ for an arbitrarily

long time if zero crossings of D & CK

occur sufficiently close together.

• Metastable operation is normally

avoided in digital circuit operation(!)

EECS 270C

Spring 2008

Prof. Michael Green


33

Dog Dish Analogy

???

A dog placed equidistant between two dog dishes will starve (in theory).

EECS 270C

Spring 2008

Prof. Michael Green


34

Non-Idealities in Binary DFF Phase Detector

1. Metastable operation difficult to characterize & simulate, varies widely

over processing/temperature variations. Kpd (and therefore jitter transfer

function parameters) are difficult to analyze. Exact value of Kpd depends

on metastable behavior and varies with input jitter.

2. Large-amplitude pattern-dependent variation is present in phase detector

output while locked.

3. During long runs phase detector output remains latched, resulting in VCO

frequency changing continuously:

VP

RCK

D

in

fvco

EECS 270C

Spring 2008

Prof. Michael Green


35

Idea: Change VCO frequency for only one clock period

VP

RCK

D

in

RCK early RCK late

Circuit realization should sample data with clock (instead of clock with data)

while maintaining bang-bang operation.

EECS 270C

Spring 2008

Prof. Michael Green


36

Alexander Phase Detector

RCK

D

in

Q1Q2

Q3 Q4

UP

DN

Din

RCK

Q1

Q2

Q3

Q4

UP

DN

RCK early

Q1 leads Q3; Q2/Q4 in phase

RCK late

Q3 leads Q1; Q1/Q4 in phase

EECS 270C

Spring 2008

Prof. Michael Green


37

Simulation Results: Alexander PD

DFF outputs

VCO control

voltage

EECS 270C

Spring 2008

Prof. Michael Green


38

Binary PDLinear PD

Simulation Comparison:

Linear vs. Binary

• very small freq. acquisition range

• low steady-state jitter

• high freq. acquisition range

• high steady-state jitter

Vcontrol Vcontrol

EECS 270C

Spring 2008

Prof. Michael Green


39

Half-Rate CDRs

To relax speed requirements for a given fabrication technology, a half-

rate clock signal can be recovered:

Din

RCK

RCK2

input data

full-rate recovered clock

half-rate recovered clock

• Can be used in in applications (e.g., deserializer) where full-rate clock is

not required.

• Duty-cycle distortion will degrade bit-error ratio & jitter tolerance

compared to full-rate versions.

EECS 270C

Spring 2008

Prof. Michael Green


40

Idea 1: Input data can be immediately

demultiplexed with half-rate clock

Din

RCK2

DA

DB

Din

RCK2

DA

DB

D0 D1 D2 D3 D4

D0 D2 D4

D1 D3

synchronized with

clock transitions

EECS 270C

Spring 2008

Prof. Michael Green


41

Din

RCK2latch latch

latch latch

DAXA

XB DB

DB

RCK2

Din

XA

XB

DA

Splitting D flip-flops

into individual latches:

synchronized with

RCK2

synchronized with

both RCK2 & Din

These pulse widths

contain phase information.

EECS 270C

Spring 2008

Prof. Michael Green


42

DB

RCK2

Din

XA

XB

DA

P = X

AX

B

R = D

AD

B

RCK2

Din

P R

XA

XB

DA

DB

1

2

Complete Linear Half-Rate PD

J. Savoj & B. Razavi, “A 10Gb/s CMOS

clock and data recovery circuit with a

half-rate linear phase detector,”

JSSC, vol. 36, pp. 761-768, May 2001.

EECS 270C

Spring 2008

Prof. Michael Green


43

Idea 2: Observe timing between Din, RCK and quadrature RCKQ

Din

RCK

RCKQ

Din

RCK

RCKQ

S0 S1 S2 S0 S1 S2

Clock early Clock late

S0, S2 sampled with RCK transitions

S1 sampled with RCKQ transitions

Phase logic:

S

0S

1= 0( ) and S

1S

2= 1( )

S

0S

1= 1( ) and S

1S

2= 0( )

S

0S

1= 0( ) and S

1S

2= 0( )

clock early

clock late

no transition

EECS 270C

Spring 2008

Prof. Michael Green


44

Din

RCK

RCKQ

DI

DQ

VPD

Din

RCK

RCKQ

DI

DQ

VPD

Din

RCK

RCKQ

DI

DQ

VPD

Clock early Clock late

J. Savoj & B. Razavi, “A 10-Gb/s

CMOS clock and data recovery

circuit with a half-rate binary

phase detector,” JSSC, vol. 38,

pp. 13-21, Jan. 2003.

Documents

Motivation for CDR: Deserializer (1)gram.eng.uci.edu/faculty/green/public/courses/270c/... · 2016-09-19 · t Tb = 2 + 1 2 VP Vswing = 2 t Tc 1 VP Vswing = +( 1)- + VP Vswing = 0.25