Ž .Materials Science and Engineering C 15 2001 145–147www.elsevier.comrlocatermsec

MOS memory devices based on silicon nanocrystal arrays fabricatedby very low energy ion implantation

P. Normand a,), E. Kapetanakis a, D. Tsoukalas a, G. Kamoulakos a, K. Beltsios b,J. Van Den Berg c, S. Zhang c

a Institute of Microelectronics, NCSR Demokritos, 15310 Aghia ParaskeÕi, Greeceb Institute of Physical Chemistry, NCSR Demokritos, 15310 Aghia ParaskeÕi, Greece

c Department of Physics, UniÕersity of Salford, Salford M5 4WT, UK

Abstract

The electrical characteristics of Si nanocrystal-based MOS memory devices are studied. The nanocrystals are fabricated into 8-nm thinoxide by very low energy Siq implantation at different doses and subsequent annealing. TEM work suggests that Si nanocrystals developat a density, size and perfection that vary strongly with the implanted dose and these structural features are found compatible with thedevice transfer characteristics. q 2001 Elsevier Science B.V. All rights reserved.

Keywords: Si; Implantation; Nanocrystals; Memory

1. Introduction

In order to overcome limitations of conventional non-volatile and volatile memory devices, it has been proposedto use nanocrystals as charge storage elements embedded

Ž .in the gate oxide of a field-effect transistor FET andŽ .located in close proximity 2–3 nm to the transistor

channel. Si or Ge nanocrystal-based floating gates havebeen fabricated through the use of various deposition

w xtechniques or ion implantation and annealing 1 . The latterapproach is very promising because of its well-establishedmanufacturing advantages but faces the major issue ofmaking nanocrystals close to the channel without compro-mising the integrity of the gate oxide and the quality of theSiO rSi interface. For that reason, the ion implantation at2

a very low energy is particularly attractive. It has beenw xrecently demonstrated 2 that this technique can lead upon

proper annealing to the formation of 2-D arrays of semi-conductor nanocrystals located at a tunneling distancefrom the SiO rSi interface. In this work, we present the2

memory characteristics of Si-nanocrystal floating-gateMOSFETs and discuss the effects, on the device operation,of the implanted dose as well as of the various traps anddefects that originate from the nanocrystal fabrication pro-

) Corresponding author. Tel.: q30-1650-3115; fax: q30-1651-1723.Ž .E-mail address: p.normand@imel.demokritos.gr P. Normand .

cess. The devices are fabricated in a manner similar to thatused for conventional nMOS transistors, with the excep-tion of the generation of a 2-D array of Si nanodomains inthe gate oxide. For this purpose, silicon is implanted atdoses of 5=1015, 1=1016 or 2=1016 Siq cmy2

Žhereafter referred to as low, medium and high dose,.respectively at 1 keV into 8-nm thick oxide. Subse-

quently, a 30-nm control oxide is deposited, followed by a30-min, 9508C annealing in nitrogen, aiming at the precipi-tation of Si nanocrystals.

2. Results and discussion

2.1. TEM obserÕations

Fig. 1 shows the cross-sectional and plane-view TEMmicrographs of 8-nm thick oxide layers implanted with5=1015, 1=1016 and 2=1016 Siq cmy2 and subse-quently annealed at 9508C for 30 min. XTEM analysis of

Ž . Ž .medium- see Fig. 1 and high-dose not shown hereimplanted samples reveal the presence of a Si-rich band ofabout 3 nm in thickness located at 2–3 nm from theSiO rSi interface. Electron diffraction patterns and plane2

view TEM observations indicate that these bands are com-posed of silicon nanocrystals of 3–8 and 4–15 nm in sizefor the medium- and high-dose samples, respectively. Re-garding the low-dose implanted sample, the plane view

0928-4931r01r$ - see front matter q 2001 Elsevier Science B.V. All rights reserved.Ž .PII: S0928-4931 01 00251-X

( )P. Normand et al.rMaterials Science and Engineering C 15 2001 145–147146

Fig. 1. TEM micrographs from samples with 8-nm thick SiO layer215 Ž . 16 Ž . 16implanted with 5=10 left inset , 1=10 central inset and 2=10

Ž . q y2right inset Si cm at 1 keV and annealed at 9508C for 30 min.Nanocrystals appear as white entities in the central and right insets. Thecross-section image pertains to the 1=1016 Siq cmy2 implanted sample.

image in Fig. 1 shows no distinct structure. Nevertheless,cross-sectional dark field images and related e-diffractionpatternrplane-view work indicate the presence of some Siclusters of a 2–4 nm size.

2.2. DeÕice characteristics

Fig. 2 shows the effect of Siq implantation dose on thetransfer characteristics of the devices. The curves weretaken by sweeping the gate bias forth and back with a0.2-Vr0.13-s step. Devices implanted with a low- ormedium-dose exhibit a clear memory effect caused by thetrapping of electrons or holes in the gate oxide during thepositive or the negative gate voltage sweep. The high-doseimplanted devices show a higher leakage current and a

Fig. 2. Source-drain current versus gate voltage characteristics for Si-im-Ž .planted low, medium and high doses and non-implanted devices with a

4-mm gate length. The gate voltage is swept continuously from y19 V toŽ .q19 V and back to y19 V. The source-drain voltage V is fixed atDS

0.1 V. The linear transfer characteristics for the low- and medium-dosecases are shown in the inset. No hysteresis is observed for the non-im-

Ž .planted reference device.

strong reduction of the source-drain current as the gatebias is swept from negative to positive values. Linear

Ž .I –V characteristics inset of Fig. 2 reveal that thisDS G

drain current reduction is also present for the low- andmedium- dose implanted devices. The gate bias for theobservation of this effect depends on the implantation doseŽa bias of 0.8, 4.2 and 10.4 V for the high-, medium- and

.low-dose cases, respectively and is related to the dynamicchanges of the device threshold voltage caused by chargeexchange. The latter exchange can take place between theinversion layer and electronic states that may be due to the

Ž .presence of excess Si low-dose case or can be located tow xthe bulk of Si nanocrystals 3 or at the Si-nanocrystalrSiO2

w x Ž .interfaces 4 medium- and high-dose cases . For constantelectric field, charge movement is expected to be stronglyaffected by several factors such as the location of the Siislands from the Si inversion layer, the size and degree ofcrystallinity of the Si islands and the density of interfacestates at the SirSiO and nc-SirSiO interfaces.2 2

Ž .The dependence of the threshold voltage shift DV onT

the gate voltage sweep rate was investigated at room andŽ .liquid nitrogen 77 K temperatures for low- and medium-

Ž .dose implanted devices Fig. 3 . The measurements werew xperformed in a way similar to that of Ref. 5 . A load

Ž .resistor R s100 V is connected between the sourceL

electrode and ground to monitor the drain current IDŽ .through source voltage V s I R measurements. A tri-S D L

Ž .angular signal of q15ry15 V amplitude V was ap-G

plied to the gate electrode for a wide range of frequencies.The V and V signals were stored in an oscilloscope andG S

the DV values were extracted from the V versus VT S GŽ .both linear scale plots.

For the low-dose case, DV is larger at room tempera-T

ture and monotonically increases as the frequency de-creases with a tendency for saturation. For the medium-dosecase, DV at 77 K increases monotonically as the fre-T

Ž .Fig. 3. Threshold voltage shift DV versus frequency of q15ry15 VT

V triangular signal for low- and medium-dose implanted devices at 300G

and 77 K.

( )P. Normand et al.rMaterials Science and Engineering C 15 2001 145–147 147

Fig. 4. Source-drain current decay characteristics for low- and medium-dose implanted devices after application of y15 V pulse gate bias. Thedrain voltage was fixed at 0.1 V.

quency decreases. For the same dose at 300 K, DVT

increases continuously up to 10 Hz and then decreasessignificantly in contrast to the 77 K trends. These observa-tions indicate that both the degree of crystallinity of the Siclusters and the traps generated during Siq implantationplay a significant role in the charge storage mechanism ofthe resulting memory devices. The decrease of DV atT

Ž .room temperature for low frequencies medium-dose caseimplies that thermal activation is significant in the chargeexchange process for these implantation conditions and our

Ž .structural observations Fig. 1 suggest the involvement ofSi nanocrystals.

Fig. 4 shows the retention time characteristics in termsof the decay of drain current for the low- and medium-dose

implanted devices. For the measurement of the decaycurrent from 10y5 to 1 s, a voltage pulse of y15 V isapplied to the gate and the drain current decay is measuredat 0 V gate voltage corresponding to the erase operation.The hold time of the injected holes is improved for thelow-dose devices, an observation that is consistent withour preceding discussion.

3. Conclusions

Si-nanocrystal floating-gate MOSFETs are fabricatedand electrically characterized at room and liquid nitrogentemperatures. The nanocrystals are obtained by very lowenergy ion implantation of silicon at different doses into8-nm thick thermal oxide and subsequent annealing. Ac-cording to TEM studies, the degree of crystallinity, den-sity, and size of the nanocrystals depend strongly on theimplanted dose. TEM observations are consistent with theelectrical characteristics of the memory devices.

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