Module #7 Page 1 EELE 414 – Introduction to VLSI Design Module #7 – Storage Devices Agenda 1.Sequential Logic 2.Memory Announcements 1.Read Chapters 8

Module #7Page 1EELE 414 – Introduction to VLSI Design

EELE 414 – Introduction to VLSI Design

Module #7 – Storage Devices

• Agenda

1. Sequential Logic

2. Memory

• Announcements

1. Read Chapters 8 & 10


Sequential Logic

• Sequential Logic

- Now we move to logic circuits whose outputs depend on:

- the current values of the inputs - the past values of the inputs

- this is the definition of "Sequential Logic"

- in order to make logic circuits based on the previous values of inputs, we need a storage device


Feedback & Metastability

• Feedback

- consider this circuit

- the outputs are "fed back" to the inputs

- this gives the following relationships: Q = Vin1' Qn = Vin2' Vin1 = Qn Vin2 = Q

Vin1 = Vin2' = Q' = Vin1 Vin2 = Vin1' = Qn' = Vin2

- this circuit will HOLD or STORE a logic value

- feedback gives us the ability to build "Sequential Storage Devices"



• Metastability

- what if the input is VDD/2

- in an ideal world, the outputs would be driven to VDD/2

- we know that noise exists in the world (thermal, shot, etc…)

- noise will add a small Δv to the nodes in the system



• Metastability

- let's consider a + Δv being superimposed on input Vin1 who starts out at VDD/2

- this causes a - Δv to be superimposed on output Q due to the inverting nature of the inverter

- this - Δv is fed back to input Vin2, which in turn causes a + Δv on output Qn

VDD/2 + Δv VDD/2 - Δv

VDD/2 - Δv VDD/2 + Δv



• Metastability

- this new + Δv is fed back to the original Vin1 voltage in an additive nature

- this drives Vin1 even further positive, which in turn starts the loop all over again

- this feedback loop continues until the inputs and outputs are driven to either a 0 or a 1

VDD/2 + Δv + Δv VDD/2 - Δv - Δv

VDD/2 - Δv - Δv VDD/2 + Δv + Δv



• Metastability

- Metastability is the situation where the inputs cause an indeterminate output in a feedback circuit

- i.e., VILmax < Vin < VIHmin

- using feedback, we know that the circuit will always be driven to a final state

- this is also called a "Bi-Stable" element meaning that the inputs and outputs will be driven to one of two final states (i.e., a 1 or a 0)

- the final state that the circuit is driven to is unknown, but we know it will go there eventually



• Recovery time

- manufactures can specify the maximum amount of time that a bi-stable element will take to reach its final value

- the time that the output is unknown is called the "Metastability Region"

- the time it takes to exit the Metastable region is called the "Recovery Time" (t recovery)


SR Latch

• SR Latch

- consider the following circuit which is called an "SR Latch"

- To understand the SR Latch, we must remember the truth table for a NOR Gate:

AB F 00 1 01 0 10 0 11 0


SR Latch

• SR Latch

- when S=0 & R=0, it puts this circuit into a Bi-stable feedback mode where the output is either:

Q=0, Qn=1 Q=1, Qn=0

AB F AB F 00 1 (U2) 00 1 (U1)01 0 01 0 (U2)10 0 (U1) 10 0 11 0 11 0

0

0

0

0 1

1 1

1

0

0 0

0


SR Latch

• SR Latch

- we can force a known state using S & R:

Set (S=1, R=0) Reset (S=0, R=1)

AB F AB F 00 1 (U1) 00 1 (U2)01 0 01 0 (U1)10 0 (U2) 10 0 11 0 (U2) 11 0 (U1)

1

1

0

1 0

0 0

0

1

0 1

1


SR Latch

• SR Latch

- we can write a Truth Table for an SR Latch as follows

S R Q Qn . 0 0 Last Q Last Qn - Hold 0 1 0 1 - Reset 1 0 1 0 - Set 1 1 0 0 - Don’t Use

- S=1 & R=1 forces a 0 on both outputs. However, when the latch comes out of this state it is metastable. This means the final state is unknown.


SR Latch

• SR Latch

- Remember the Truth Table for an SR Latch:

S R Q Qn . 0 0 Last Q Last Qn - Hold 0 1 0 1 - Reset 1 0 1 0 - Set 1 1 0 0 - Don’t Use

- there is delay associated with changes on the input causing a change on the outputs:

tPLH(SQ) = Δt for a LOW-to-HIGH transition on S to cause an output change on Q tPHL(RQ) = Δt for a HIGH-to_LOW transition on R to cause an output change on Q

- there is also a specification on how small of a pulse width we can have and be recognized

tPW(min) = minimum input pulse width that can be recognized


SR Latch

• SR Latch

- Just as in the NOR gate transistor circuit, the delay comes from charging and discharging capacitance.

- However, in addition to the intrinsic capacitance of the driving NOR gate and the receiver’s gate capacitance, the driver must also drive the gate capacitance of its own bi-stable element


S'R' Latch

• S’R’ Latch

- we can also use NAND gates to form an inverted SR Latch

S’ R’ Q Qn . 0 0 1 1 - Don’t Use 0 1 1 0 - Set 1 0 0 1 - Reset 1 1 Last Q Last Qn - Hold


SR Latch w/ Enable

• SR Latch w/ Enable

- this allows us to add an enable line also using NAND gates

- remember the Truth Table for a NAND gate

AB F 00 1 - a 0 on any input forces a 1 on the output 01 1 - when C=0, the two EN NAND Gate outputs are 1, which forces “Last Q/Qn” 10 1 - when C=1, S & R are passed through INVERTED 11 0


SR Latch w/ Enable

• SR Latch w/ Enable

- the truth table then becomes

C S R Q Qn . 1 0 0 Last Q Last Qn - Hold 1 0 1 0 1 - Reset 1 1 0 1 0 - Set 1 1 1 1 1 - Don’t Use 0 x x Last Q Last Qn - Hold


D Latch

• D Latch

- a modification to the SR Latch where R = S’ creates a D-latch

- when C=1, Q <= D- when C=0, Q <= Last Value

C D Q Qn . 1 0 0 1 - track 1 1 1 0 - track 0 x Last Q Last Qn - Hold


D Latch

• D Latch

- we can use CMOS transmission gates to implement the functionality of a D-latch


D Latch

• D Latch

- The T-gates operate as complementary switches which either:

- drive the output - hold the input

- the T-gate gives the necessary functionality and a reduced transistor count in the final implementation

- timing specifications dictate how long before and after the clock that the data must be valid in order for the circuit to operate correctly


D Latch

• D Latch

- An edge triggered D-latch can be created using the following configuration:


Flip Flops

• Flip-Flops

- a "Latch" is a device that "tracks or holds" the input depending on a control signal (i.e., C or CLK)

- a "Flip-Flop" is a device that will "acquire and hold" the input when a transition is present on C or CLK

- Flip-Flops are commonly used in sequential logic due to their speed

- The general configuration of a Flip-Flop has two latches in series called Master and Slave stages


D-Flip-Flops

• D-Flip-Flops

- we can combine D-latches to get an edge triggered storage device (or flop)

- the first D-latch is called the “Master”, the second D-latch the “Slave”

Master Slave CLK=0, Q<=D “Open” CLK=0, Q<=Q “Close”

CLK=1, Q<=Q “Closed” CLK=1, Q<=D “Open”

- on a rising edge of clock, D is “latched” and held on Q until the next rising edge


D-Flip-Flops

• D-Flip-Flops

- In CMOS, we can use two of the T-gate stages to implement a falling edge D-flip-flop with a minimal transistor count


D-Flip-Flops

• D-Flip-Flops

- The DFF passes and holds the information on D to Q on the falling edge of CK


D-Flip-Flops

• D-Flip-Flops

- The DFF requires tsetup and thold to be met in order for proper operation

- The following shows a setup/hold violation


D-Flip-Flops

• D-Flip-Flops

- the CMOS DFF can be implemented in a regular layout pattern just as combinational logic


D-Flip-Flops

• D-Flip-Flops

- the bi-stable behavior of Sequential Logic can be used to create hysterisis.

- this can be used to overcome intermittent switching of digital circuits in a noisy environment.

- Hysterisis creates a gate which has a different switching threshold for rising edges and a different switching threshold for falling edges.

- the following is an example of such a circuit called a Schmitt Trigger.


Memory

• Memory

- Memory is the storage of digital information

- Memory is typically classified differently than flip-flops and latches due to the ability to create large arrays of storage

- Memory is actually the driving force behind Moore's law and consumes the majority of area and power in a modern uP

- The factors that drive the different architectures we see in memory are:

1) Cost - cost per bit, more bits per area reduces cost

2) Speed - how fast can we get or put data, does this match the performance needs of other logic 3) Power Consumption - does the power consumption make deep memory infeasible


Memory

• Memory Types

Notes on definitions:

1) The word "RAM" is now used interchangeably with R/W memory. Formally, most types ROM are also Random Access

2) ROM memory typically refers to storage that can't be written during program execution. It can hold program and data information, but under normal operation a CPU doesn't use it for variable storage.

As Flash EEprom gets faster and more reliable, Flash may become used as RAM


Memory - SRAM

• Static Random Access Memory (SRAM)

- SRAM is volatile memory (i.e., if the power is removed, the information is lost)

- SRAM uses an inverter loop to store the digital information

- two NMOS transistors acting as switches are used to Read and Write the stored data

- we call the circuitry to store 1-bit a "cell"


Memory - SRAM

• SRAM Addressing

- we configure the cells into an array

- we address each cell using:

Row Address

- a row decoder produces a "Word Line"

- this gives a "Row Select" (RS) signal

Column Address

- a column decoder produces a "Bit Line"

- this gives a "Column Select" (CS)


Memory - SRAM

• SRAM Addressing

- The Word Lines are used to address a row of cells

- The Bit Lines are used to address a column in addition to reading and writing

- There are two bit lines per cell, BL and BL'

- This allows a difference amplifier to be used to distinguish between a 1 and a 0


Memory - SRAM

• SRAM Reading

- The capacitance of the Bit Lines can be very large due to multiple cells being attached

- This creates a problem during a READ because the small cell will need to drive this large capacitance

- To reduce the amount of charge that the cell has to drive during a READ, pull-up transistors are used to "pre-charge" the lines to VDD


Memory - SRAM

• SRAM Reading

- In order to design a usable SRAM cell, we must meet the condition that:

"Reading the value does NOT destroy the contents of the cell"

- Let's look at what happens during a read to see how to meet this condition

Reading a '0'

- Initially V1=0v, V2=VDD

- M3 and M4 are turned ON

- this allows the Cell to drive BL and BL'

- The voltage V2 will be the same as the pre-charged BL' line, so no current will flow through M4


Memory - SRAM

• SRAM Reading

Reading a '0' cont…

- M1 will attempt to pull down the BL line through the M3 and pull-up transistors.

- This action creates a slight difference between BL and BL' which gives us the information about the cell (i.e., it holds a 0).

WL

BL

BL'

VDD

0

VDD

0

VDD

0


Memory - SRAM

• SRAM Reading


- The BL line will actually pull up V1 through the M3 transistor

- we need to ensure that V1 does not get large enough to turn ON M2

- if V1>VT,n-M2, then M2 will begin conducting current and will put the cell into an unknown state

- our first design condition is:

nTVV ,1


Memory - SRAM

• SRAM Reading


- We can write KCL at the V1 node to derive an expression between the size ratio of M3 and M1 in order to meet our condition.

- We can then substitute in V1=VT,n

2,12

,3

13

1122

11

2

1VVVVkVVVk

II

nTDDnnTDDn

MDMD

nTnTDDnnTDDn

nTnTDDnnTDDn

nTnTnTDDnnTDDn

nTnTnTDDnnTnTDDn

VVVkVVk

VVVkVVk

VVVVkVVk

VVVVkVVVk

,,12

,3

2,,1

2,3

2,

2,,1

2,3

2,,,1

2,,3

2

32

2

12

2

1

322

12

2

1

222

12

2

1

22

1

2

1


Memory - SRAM

• SRAM Reading


- We can then rearrange to put in terms of Transconductance

- since the NMOS mobility's and Oxide Capacitances are the same, we get

1

32

,

,,

1

3

2

23

2

LW

C

LW

C

VV

VVV

k

k

oxn

oxn

nTDD

nTnTDD

n

n

2,

,,

1

3

2

23

2

nTDD

nTnTDD

VV

VVV

LWLW


Memory - SRAM

• SRAM Reading


- Due to symmetry, we size M3=M4 and M1=M2.

- In addition, the Lengths of all transistors are typically the same

- this allows us to relate the sizes for 4 of the 6 transistors in the SRAM cell

2,

,,

2/1

4/3

2

23

2

nTDD

nTnTDD

VV

VVV

LWLW


Memory - SRAM

• SRAM Writing

- when writing to the SRAM cell, we inject full swing digital signals onto BL and BL'.

- when we assert the Word Lines, M3 and M4 will open and attempt to change the state of the cell.

- the worst case situation is when writing a '0' when a '1' is already stored in the cell

- another design condition is that when we put full swing voltage levels on BL and BL', we need to be able to change the state of the cell.

Writing a '0'

- Initially V1=VDD, V2=0v (i.e., the cell stores a '1')

- we write a 0 by driving BL=0, BL'=VDD

- when the Word Line is asserted, M3 and M4 are turned ON


Memory - SRAM

• SRAM Writing

Writing a '0' cont…

- In this case, BL'=VDD and V2=~0v. If we met our first design condition, then BL' should NOT be able to change the state of the cell

- In order to successfully change the state of the cell, V1 must be driven low enough by BL to turn OFF M2.

- this gives us our 2nd design condition for the SRAM cell during a write:

nTVV ,1


Memory - SRAM

• SRAM Writing


- We can write KCL at the V1 node to derive an expression between the size ratio of M3 and M5 in order to meet our condition.

- Substituting in V1=VT,n and rearranging, we get:

2,3

2,5

2,,,,3

2,,5

35

1122

10

2

1

22

1

2

1

VVVVkVVk

VVVVkVVk

II

nTDDnpTDDp

nDSnDSnTnGSnpTpGSp

MDMD

3

52

,

,,

3

5 23

2

LW

C

LW

C

VV

VVV

k

k

oxn

oxp

pTDD

nTnTDD

n

p


Memory - SRAM

• SRAM Writing


- the Oxide Capacitances are the same so we get:

- Due to symmetry, we size M5=M6

- now we have a relationship for all 6 transistors in the SRAM cell

- Note: these ratios enable DC operation. In order to determine the final sizes of the transistors, we use timing or area specifications.

2,

,,

3

5 23

2

pTDD

nTnTDD

p

n

VV

VVV

LWLW


Memory - SRAM

• SRAM Operation

- The voltages on BL and BL' will look as follows during successive Read/Write cycles

WL

BL

BL'

VDD

0

VDD

0

VDD

0

Write 1 Read 1 Write 0 Read 0


Memory - SRAM

• SRAM Read Circuitry (Sense Amps)

- Sense Amplifiers are used to distinguish between a 0 and a 1 on BL / BL'

- The first stage amplifier is a current amp that is enabled using a PSAE' signal

- The output of this amp is fed into a voltage amplifier which amplifies the signals to full swing CMOS levels (DIO, DIO')


Memory - SRAM

• SRAM Write Circuitry

- To write a value, a high strength digital buffer is used to drive BL and BL'

- The buffer has to be strong enough (i.e., Low Zout) to drive all of the capacitance on the Bit Lines within a specified time.


Memory - SRAM

• SRAM Operation

- Waveforms of a Read and Write cycle

READ

WRITE


Memory - SRAM

• SRAM Layout

- SRAM cells can be laid out in a very compact manner. This allows them to be easily copied to form large arrays.

1 Cell 4x4 Array


Memory - DRAM

• Dynamic Random Access Memory (DRAM)

- A volatile memory storage device even smaller than SRAM

- DRAM uses a capacitor to store the value of the digital information (instead of an inverter loop)

- one NMOS transistor is used to address the storage element

- the one-transistor configuration is known as a “1T” DRAM


Memory - DRAM

• DRAM Operation

- When the cell is addressed, the charge on the storage capacitor (CS) is dumped onto the bit line (BL)

- To reduce the amount of charge the cell has to provide, the bit line capacitance (CBL) is pre-charged to VDD/2

- When the NMOS switch closes, the two capacitances will share their charge


Memory - DRAM

• DRAM Operation

- this is a typical charge sharing problem

- remember that prior to the switch closing, each node has a total amount of charge given by:

- after the switch closes, the voltage across both capacitors will be equal due to KVL

- the total charge will distribute across the capacitors according to their values

V

QC


Memory - DRAM

• DRAM Operation

- we define: VS - the voltage across the storage capacitor CS

VBL - the voltage of the Bit Line capacitance CBL

- if originally:

VS > VBL - the final value of VBL will be slightly greater than the original value of VBL

VS < VBL - the final value of VBL will be slightly less than the original value of VBL

- to reduce the power and time associated with moving charge, the bit lines are charged to VDD/2

- this gives the Bit Lines the ability to be charged or discharged equally around VDD/2

- typically, CBL is ~10x larger than CS due to the multiple cells that are connected to the Bit Line


Memory - DRAM

• DRAM Operation

Charge Sharing when Reading a '1'

VS = VDD (i.e., storing a 1) VBL = VDD/2 (pre-charged)

at t=0-

at t=0+

now if CBL≈10·CS

2DD

BLBLBLBL

DDSSSS

VCVCQ

VCVCQ

BLS

DDBLDDS

BLS

BLS

TOT

TOTNEW CC

VCVC

CC

QQ

C

QV

2

211

6

101

51

102

10DD

DDDDSS

DDSDDS

NEW

VVV

CC

VCVC

V


Memory - DRAM

• DRAM Operation

Charge Sharing when Reading a '0'

VS = 0v (i.e., storing a 0) VBL = VDD/2 (pre-charged)

at t=0-

at t=0+

now if CBL≈10·CS

2

0

DDBLBLBLBL

S

VCVCQ

Q

BLS

DDBL

BLS

BLS

TOT

TOTNEW CC

VC

CC

QQ

C

QV

20

211

5

101

5

102

10DD

DDDDSS

DDS

NEW

VVV

CC

VC

V


Memory - DRAM

• DRAM Operation

- The new value of VBL given by the charge sharing expressions is:

where

- for VDD=5v, ΔV is between 50mv to 200mV

- to distinguish this small of a ΔV, we need sense amplifiers

VV

V DDBLnew

2

2DD

BLS

S V

CC

CV


Memory - DRAM

• DRAM Operation

Bit Line Sense Amplifiers

- a differential version of BL exists called BLB that is used to sense BL and increase the sensitivity

- this line is also pre-charged to VDD/2 and provides an initial reference for BL

- a latch amplifier is used to detect the differences between BL and BLB


Memory - DRAM

• DRAM Operation

Bit Line Sense Amplifiers

- control signals SA and SAB are used to selectively amplify the bit lines

- PSA and PSAB control the load transistors for the Sense Amps

- these are typically turned on sequentially to reduce the amount of simultaneous charge movement


Memory - DRAM

• DRAM Operation

Bit Line Sense Amplifiers & Read Amps

- the values of BL and BLB will eventually reach 0v and VDD

- the values are then connected to a Read Amp through switch transistors (MNC1 & MNC2)

- the switch transistors are turned on by the Column Select line

- the Read Amp then converts the BL and BLB signals into full swing, high drive strength signals (Dout)


Memory - DRAM

• DRAM Operation

Bit Line Equalizers

- prior to addressing the cell, the Bit-Lines are pre-charged to VDD/2 using a “Bit Line Equalizer”

- a control line (PEQ) is used to turn this circuit on


Memory - DRAM

• DRAM Operation

Sense Line Equalizer

- prior to connecting the Bit Lines (BL/BLB) to the Sense Amps, the sense lines are pre-charged to VDD/2 using a “Sense Line Equalizer”

- a control line (PSAEQ) is used to turn this circuit on


Memory - DRAM

• DRAM Operation

Charge Pumps (PISOi)

- The Bit Lines are connected to the Sense Amplifiers through NMOS switches

- The NMOS's are turned on using the control signal PISOi

- Notice that since the PISOi NMOS's act as switches, to turn them on the Gate voltage needs to be greater than the storage voltage (potentially VDD) + the threshold of the storage transistor (VT,n)


Memory - DRAM

• DRAM Operation

Charge Pumps (Word Lines)

- Notice that since the storage NMOS's act as switches, to turn them on the Gate voltage needs to be greater than the storage voltage (potentially VDD) + the threshold of the storage transistor (VT,n)

- this means we have two locations (PISOi & WL) that require a voltage higher than VDD

- instead of using an additional power supply, an internal charge pump is used to create the on-chip, "higher than VDD" voltage (Vpp)


Memory - DRAM

• DRAM Operation

Charge Pumps

- charge pumps trap charge on capacitors by only allowing current to flow uni-directionally into a capacitor

- this can be accomplished with a Diode

- one terminal of the capacitor is connected to Vin through a Diode

- the other terminal of the capacitor is connected to a Clock signal

- when the Clock is LOW, the capacitor charges to (V in - Vt-diode) through the Diode

- when the Clock goes HIGH, the capacitor voltage goes to (VDD + Vin - Vt-diode) since the original charge on the capacitor can't flow back into V in due to the Diode polarity

- this gives a voltage higher than VDD - multi-state charge pumps can create >20v on-chip


Memory - DRAM

• DRAM Operation

Write Amps

- to write information to the cell, a full-swing amp simply drives BL and BLB using the same path as during the Read Operation

- the data to be written comes from the Din bus


Memory - DRAM

• DRAM Operation (Reading)

Step 1 – the Bit Line and Sense Amp Equalizers Pre-Charge the Bit Lines and Sense Amps

Step 2 – the PISOi and Word Lines are “boosted” to Vpp (>VDD)

Step 3 – the Word Line is asserted which starts the charge sharing between the storage cell and the bit line


Memory - DRAM

• DRAM Operation (Reading)

Step 4 – The BL sense amp is activated

Step 5 – The BLM sense amp is activated

Step 6 – the Column Select (CS) line is asserted connecting BL/BLB to the full swing Read Amp

Step 7 – the full swing signal is seen on Dout


Memory - DRAM

• DRAM Operation (Writing)

- everything is the same as in a Read, accept that instead of connecting the Read Amp, the Write Amp is connected which drives the BL/BLB lines to their new values


Memory - DRAM

• System Level Operation

- RAS and CAS are system level signals which are used to latch in the Row and Column Addresses

- The Row and Column addresses are latched in on the falling edges of RAS/CAS

- there is a delay between RAS and CAS to give time for the lines to be pre-charged

- the time from the falling edge of RAS to when data is valid is called Latency

- the time from the falling edge of CAS to when data is valid is specifically called CAS Latency

Refresh

- since the capacitor is continually leaking its charge, it needs to be periodically “refreshed”

- this can be accomplished by performing a simple READ since the sense amps will drive BL and BLB to full swing signals


Memory - DRAM


Page Mode

- we can access multiple bits on a single Word Line without re-asserting RAS

- this reduces latency when performing multiple Read/Write cycles

- for one RAS assertion, multiple CAS assertions can be performed

Extended Data Out (EDO)

- additional latching circuitry can be added to leave the data on the bus even after RAS and CAS go high

- this gives additional timing margin to circuits interfacing with DRAM memory


Memory - DRAM


Synchronous DRAM (SDRAM)

- state machines can also be added on-chip that handle the scheduling of all timing events within the DRAM

- this enables tighter timing control within the DRAM and increases performance

Burst Mode

- we can configure the state machines in SDRAM to Read/Write to a group of cells automatically

- this further reduces latency

- we setup the state machine with the start address and how much information to give


Memory - DRAM


Double Data Rate (DDR)

- SDRAM can be further sped up by allowing data to be transferred on both edges of the clock

- this effectively doubles the data rate that can be achieved using the same state machine speed

Protocol Based DDR

- to reduce the pins on the DRAM package, the information that is communicated to the state machines can be provided in a serialized packet instead of in the traditional parallel method.


Memory – ROM

• Nonvolatile Memory

- SRAM and DRAM and attractive due to their speed

- however, they are volatile which means when the power is removed, the data is lost

- for a microcomputer, we need a nonvolatile storage device so that upon power-up, the computer knows what to do.

- currently, the most popular semiconductor ROM is Flash (or EEprom)

- before looking at the details of a Flash transistor, let’s first look at the different types of ROM arrays and addressing modes


Memory – ROM

• ROM Arrays

- There are two basic types of ROM arrays

1) NOR-based ROM 2) NAND-based ROM

• NOR-based ROM

- All Column Lines are pulled-up using a PMOS transistor (or resistor) - The Row Lines are connected to the gates of NMOS transistors at the intersection of Row and Column Lines

- The presence or absence of the NMOS transistors dictates whether a 1 or a 0 is stored

- If the NMOS transistor is present, it will pull down the Column Line when its gate is driven high by the Row Line

- if the NMOS transistor is absent, the Column Line will not be pulled down, so it will remain pulled up by the PMOS’s


Memory – ROM

• NOR-based ROM

- In order to Read from the array, the Row line is asserted and the desired Column line is observed

- a NOR-based ROM is similar to a Hex Keypad


Memory – ROM

• NOR-based ROM

- This type of array can be physically laid out using a very symmetric, regular pattern

- The presences or absence of NMOS pull-down transistors can be accomplished in a variety of ways

1) MROM (Mask ROM) - all NMOS transistors are diffused

- however, metal is not connected in areas where a ‘1’ is to be stored

2) PROM (Programmable ROM) - all NMOS transistors are diffused

- however, fuses are blow on the drains of the NMOS transistors where a ‘1’ is to be stored


Memory – ROM

• NOR-based ROM

3) Implant-Mask ROM

- another way to “disconnect” the NMOS transistors from the Column lines is to perform additional and selective doping in order to raise the threshold of the device

- this has the effect of raising VT,n so high (i.e., >VDD) that even a full swing signal on its gate will not turn it ON

- this means that when the Row line asserts, it cannot turn on the NMOS and the corresponding Column Line will remain high


Memory – ROM

• NAND-based ROM

- NAND-based ROM is a different array architecture

- it uses a depletion-load NMOS as the pull-up transistor

- the Column NMOS’s are connected in series with the column lines (i.e. a NAND configuration)

- If an NMOS exists in the Column line and the Row line is asserted, the NMOS will pull the Column Line down and represent a stored ’0’

- If an NMOS is absent on the Column line and the Row line is asserted, the Column Line will remain pulled high by the depletion NMOS and represent a stored ‘1’

- since all of the NMOS’s are in series, in order to Read from a Row, all other Rows much be turned ON

- this means in order to distinguish the Row we are asserting, we write a ‘0’ to it


Memory – ROM

• NAND-based ROM

- In this configuration, if an NMOS is present, it will represent a “stored 1” since in order to address its location, the Row line is driven to a ‘0’ and the NMOS not turned on. This leaves the Column line pulled HIGH

- if an NMOS is absent, it will represent a “stored 0” since all of the other Row NMOS’s are turned on and will pull the Column Line LOW

- this gives the opposite behavior as in a NOR-based ROM

NOR NAND NMOS present 0 1 NMOS absent 1 0

- it also gives a complementary addressing scheme

NOR NAND Address Row Line by driving: 1 0 All other Row Lines driven to: 0 1


Memory – ROM

• Row Decoders

NOR-based ROM

- to address a NOR-based ROM, we want to drive the Row Line of interest HIGH and leave all other Row Lines LOW

- this addressing mode is in effect a 1-of-2n Decoder

- this behavior can be accomplished by simply creating a duplicate NOR-Array configured as:


Memory – ROM

• Row Decoders

NAND-based ROM

- to address a NAND-based ROM, we want to drive the Row Line of interest LOW and leave all other Row Lines HIGH

- this behavior can be accomplished by simply creating a duplicate NAND-Array


Memory – ROM

• Column Decoders

- Column decoders take one of the selected Column lines and route it to a Data Output Line

- this requires a 1-of-2M Decoder in addition to a multiplexing scheme

- a straight forward implementation would be a wired-OR configuration where every Column Line is connected to a pass transistor

- a 1-of-2M NOR-based Address Decoder selects only one of the Columns at a time to drive the Data Output line

- the entire Column Decoder takes (2M + M∙2M) transistors


Memory – ROM

• Column Decoders

- A more efficient Column Decoder uses a binary selection tree

- The pass transistors are used to select one out of every two bit lines at each stage

- the column address bits drive the pass transistors

- this eliminates the NOR address decoder but adds M additional inverters (2∙M transistors)

- this requires fewer transistors but has a drawback of adding more pass transistors in series with the Column line, thus reducing access speed


Memory – Flash

• Flash Memory Cells

- a novel breakthrough in ROM memory was the invention of the floating gate transistor in 1984 by Toshiba

- this transistor is constructed such that the threshold of the device can be changed in-system

- if the threshold can be raised and lowered, this allows the transistor within the ROM array to either be:

“present” i.e., Normal Row addressing will turn the device ON (VRow-HIGH>VT,n)

or

“absent” i.e., Normal Row addressing is not high enough to turn the device on (VRow-

HIGH<VT,n)

- the threshold change is accomplished by applying an E-field to specifically induce “hot electron injection” to change the characteristics of the Gate structure

- if this threshold change can be accomplished after fabrication, this allows a reconfigurable ROM device that is nonvolatile, reusable, and programmable with electricity (i.e., EEprom)


Memory – Flash


- a floating gate transistor has a Control Gate and a Floating Gate

- the Floating Gate is separated from the semiconductor substrate using a “Thin Tunneling Oxide”

- On top of the Floating Gate, a thick Dielectric is grown and another Control Gate is patterned


Memory – Flash


Raising VT,n

- if charge accumulates at the Floating Gate, this in effect makes the thin dielectric a better conductor

- If the thin dielectric becomes a conductor, this is the same as moving the functional Gate further away from the substrate

- this makes it more difficult to create a channel in the substrate (i.e., VT,n gets higher)


Memory – Flash


Raising VT,n

- we use hot electron injection to accomplish this

- if we apply a high voltage across the Source and Drain (VD=6v), electrons near the Drain region will receive enough energy to form electron/hole pairs

- if we apply a high voltage at the Gate (VG=12v), the hot electrons in the substrate will be attracted to the gate

- since the electron/holes have enough energy to move freely, electrons will tunnel into the thin oxide and holes will tunnel into the substrate

- when the high voltages are removed, the electron/holes will remain in their new locations and effectively increase VT,n

- Raising VT,n is called Programming


Memory – Flash


Lowering VT,n

- we use the Fowler-Nordheim Tunneling Mechanism (FN tunneling) to return the Thin Floating Gate oxide to a conductor

- if the Gate is grounded and a high voltage (12v) is applied to the Source, the electrons in the Floating Gate will be ejected out of the dielectric and into the Source

- this has the effect of restoring the insulating ability of the Thin Dielectric and effectively moves the functional gate of the transistor closer to the substrate

- this makes it easier to create a channel in the substrate (i.e., VT,n gets lower)

- Lowering VT,n is called Erasing


Memory – Flash


- If we position the threshold voltage at a normal CMOS level (~1v), then the transistor can be turned on using a standard signal level at the gate (i.e., Vgate=5v)

- If we position the threshold voltage at a raised level (>VDD), then a standard signal level at the gate will NOT be able to turn on the transistor


Memory – Flash

• NOR Flash

- we can use Flash Cells in a NOR Array to implement a EEprom

- the Flash Cell requires one additional line on the Source of each transistor in order to accomplish the programming and erasing.

- In normal operation, the Source Line is set to Ground

- during Programming, the Source Line is set to Ground while the Word and Bit Lines are set to High Voltages

- during Erasing, the Word Lines are set to Ground and the Source Line is set to a High Voltage


Memory – Flash

• NAND vs. NOR Flash

- “Flash” implies that blocks of memory are erased at a time

- this is a specific type of EEprom and is cheaper to fabrication due to less programming circuitry

NOR Flash

- slower erase and write times- allows access to any address which makes it truly Random Access- this is suitable for uP ROM applications such as BIOS or Firmware in which the uP needs to access memory locations individually

NAND Flash

- faster erase and write times- smaller chip area which creates higher density and lower cost- more erase cycles than NOR-Flash- not Random Access, data must be read/written in large blocks, not suitable for uP ROM- it is well suited for thumb drives, iPods, and secondary storage in microcomputers (i.e., hard drives, CDROMS)

Documents

Module #7 Page 1 EELE 414 – Introduction to VLSI Design Module #7 – Storage Devices Agenda 1.Sequential Logic 2.Memory Announcements 1.Read Chapters 8