Modelling uppression of MOSFET distortion

F.S. S h o uca i r

Abstract: The author presents an analysis of the dominant distortion components of the drain current of a long-channel MOSFET in non- saturation, which accounts explicitly for the modulation of the inversion layer mobility by transverse electric fields and for all bias and relevant process (SPICE) parameters. This model predicts that if the gate is driven by a linear and by a parabolic signal ( q V D + a2VD2), both derived from the drain signal V,, odd and even distortion components are decoupled and simultaneously suppressed by separately setting the constants al and a2 under normal bias conditions. In prior methods, these components are strongly coupled and their suppression requires a delicate body bias or signal (PV,) adjustment to offset the signal-dependent mobility modulation, which is impractical in monolithic applications. These predictions are confirmed by Fourier analysis and by SPICE simulations provided the mobility modulation parameter matches experimental observations.

1 Introduction

The MOSFET is widely used as a ‘resistor’ in modern analogue integrated signal processing circuits such as RF, high-frequency, antialiasing filters, etc. The overall linearity of such circuits is limited by the nonlinearities of the transistor current-voltage (I-V) characteristics which generally dominate those of monolithic capaci- tors. While various practical schemes have achieved noteworthy reductions of MOSFET circuit nonlineari- ties, these reductions have been limited by virtue of the paradigm under which they were conceived, namely that the MOSFET inversion layer mobility was assumed to be field-independent. Moreover, in most schemes, the body terminal was tied to the source (or drain) of the device, or biased by a fixed potential [ 1-31. In circuits using balanced topologies, which improve common-mode signal rejection and dynamic range, the nonlinearities are attenuated because of first- order cancellation of the square terms in the sum or difference of currents in matched transistors. However, since this cancellation is predicated on the matching between nominally identical devices, it is fundamentally

0 IEE, 1999 IEE Proceedings online no. 19990277 DOL 10.1049/ipcds: 19990277 Paper first received 7th November 1997 and in revised form 6th July 1998 The author is with the Department of Electrical Engineering and Compu- ter Sciences, University of California, Berkeley, CA 94720, USA

limited by this practical constraint. In current proc- esses, the typical matching between the I-V characteris- tics of carefully laid out MOSFETs is of the order of 1%. Hence, even if otherwise perfect cancellation of nonlinear (square) terms is achieved by balanced con- figurations, a residual second harmonic distortion com- ponent of the order of 60dB below fundamental is inevitably observed, which results in total harmonic distortion (THD) no lower than approximately 0.1% even if higher-order harmonics are negligible.

Recently, the influence of the body potential on the nonlinearities of the inversion layer has been modelled to the extent that it has been demonstrated, analytically and experimentally, that the dominant even and odd nonlinearities of the I-V characteristics can be sup- pressed by applying signals of appropriate amplitude to the gate andior to the body of the standard four- terminal MOSFET [4-61, which are proportional to the drain-source signal. An ostensible practical disadvan- tage of this method, however, is the difficulty of pre- dicting and automatically producing the required gate and body signals on chip. Alternatively, these nonline- arities have been suppressed in a BiCMOS process with a high-resistivity polysilicon layer where the electric field normal to the inversion layer is signal-independ- ent. While this method requires a six-terminal MOS- FET with resistive gate and substrate, the additional power dissipation in these resistors appears to preclude operation in weak inversion and therefore low power monolithic applications. Moreover, this method requires careful layout in aligning gate and substrate contacts, and generally larger area [7].

This paper aims to present a detailed analysis of the dominant distortion components of the standard four- terminal MOSFET and to examine the conditions under which these components can be nulled by the application of linear and parabolic gate and/or linear body signals. We derive accurate analytical expressions which account explicitly for all bias, signal and relevant process parameters. We examine the sensitivities of dis- tortion components to the various parameters of inter- est, and propose several practical conditions under which these components can be suppressed.

2 Analytical results

2. I Transverse conductivity modulation model for long-channel devices Consider a standard, long (e.g. L 1 25pm), four- terminal n-channel MOSFET, although the forthcom- ing discussion is equally applicable to p-channel devices. This restriction properly allows us to neglect the longitudinal field modulation of the inversion layer conductivity under typical operating conditions [4-6]. The effects of combined transverse and longitudinal conductivity modulation in shorter channel devices

31 IEE Proc -Circuits Devices Syst., VX. 146, No I , February 1999

have been discussed in [6]. Using the source terminal potential as a reference, we superimpose signals vg( Vi,) and vh( V(,) on the gate (V,) and body ( V,) bias poten- tials, where V,, is the input signal applied to the drain terminal of the device (Fig. 1). Moreover, assuming constant substrate doping N,, and accounting for a first-order Taylor series correction for the transverse electric field modulation of the inversion layer conduc- tivity of the form

M4l = go($ (x ) ) . [1 + Q T ( $ ( X ) ) * $(.)I (1) where

ao(Nx>) = P o w c o z [Vc - VTO + .,(7b(x)>

+ 7dVB - $(x)

-7d$ (x ) - VB - %($(x))]

with e ~ y ( x ) ) a function of fix), the potential at posi- tion x along the inversion layer (x = 0 at the source; x = L at the drain), V, = V,, + 2@,, VT = V , + y[dV, - 4(2$~~)] , y = (l/Co.J 4(2&,,qN,), W the width of the channel, the oxide capacitance per unit area and o, the channel conductivity with V, = 0 and eT = (ep + ebb). The term edw(x))*fix) is equivalent to a first- term Taylor series correction for the transverse electric field modulation of the conductivity (e,), and for the variation in the distribution of the electrostatic poten- tials between the oxide and the band bending needed to account for the inversion charge (ebb). Because these effects depend on the bias conditions, eT too has a bias dependence even in strong inversion. The validity of this method was established in Section 11-C of [6], wherein the accuracy of the parameter 0, was critically reconciled with the Schwarz-Russek high-transverse- field theory [8].

VG + “&’in)

vB + vb(vin)

Fi .I Standard, long-channel four-terminal n-MOSFET, with gate v ?Vi,,) and body v b ( c n ) signals superimposed on bins voltages V , and fiSB. respectiveb V,,, is the signal applied to the drain and V, is the reference source potential

where v i s understood to stand for Hx). Since eqn. 1 only assumes operation in strong inversion, eqn. 2 is valid in both the triode and saturation regions. We have measured a bias dependence of eT which tits the relationship 0-X Vcs) = (-0.009 V,, + 0.086) V-’ for 2 V 5 VG 5 5 V and 0 S V,, 5 5 V. Eqn. 2 expresses a suffi- cient, spatially local, condition (for every x along the inversion layer) which yields a linear I-V relationship when dfx)] is integrated along the entire length of the channel. The resistive gate and substrate six-terminal MOSFET proposed in [7] uniformly meets this require- ment insofar as any residual nonlinearities become unobservable with standard instruments, because vg(fix)) = v h ( f i x ) ) = fx) at every x along the channel and because and d0dv)ldv are sufficiently small.

In the standard four-terminal MOSFET where the sufficient, local, condition (eqn. 2) does not hold, the I- V characteristics may be linearised by meeting the equivalent, necessary, condition that the integral of @fix)] along the length of the inversion layer be strictly proportional to the drain-source voltage. Start- ing from eqn. 1 we derive the exact I-V relationship for the four-terminal MOSFET under the assumption ded(w)/dy = 0, with a signal vg( v) = (al V, + c$VD’) superimposed on the gate bias V, and a signal v h ( v ) = PV, superimposed on the body-source reverse-bias potential VsB, where V, is the signal applied between drain and source, and al, a, and are constants such that loll V, + a2VD21 5 1 V, - Vd and IpVDl 5 1 VsBl. The resulting expression for ID is a ‘5/2 power law’ owing to the term &(w(x))*fix) in eqn. 1

V D

I D = a[‘$‘(x)1d$(2)

I) 2 2 5

- - ( V B + (1 - p)vD)5/2 + 5(VB - pVD)5/2

( 3 ) where K = poco, WIL. In the absence of the field- dependent mobility parameter (e, = 0), and of gate and body drive (a, = a, = p = 0), eqn. 3 reduces to the standard ‘312’ power law. We subsequently expand the resulting I-V characteristics (eqn. 3) in a Taylor series about V, = 0

I D = K . [ a l V ~ + u ~ V ; + uyVz

+ . . . higher-order terms] (4) where

(5)

38 IEE Pror.-Circuir.s Devices S.yst., Vol. 146, No. I . February I999

) (7) +6T (5 - - 1 7 + -(3p - 2)V,-1/2

2 3 12 The amplitudes of the second (0,) and third (&) har- monic distortion components, as fractions of the fun- damental amplitude, for a sinusoidal input signal VD = Vp sin(ot) are then given by

(9)

We have verified the accuracy of these analytical results experimentally (for D2 and D3 down to at least 80dB below fundamental) with the following data extracted for our n-channel devices: y = 1.04 VIJ2, 2@B = 0.7V, V , = 0.95V, 0.025 V-I < I 0.055 V-I. We have also verified the accuracy of eqns. 5-9 by performing a numerical Fourier analysis on the '5/2 power law' for ID for a wide range of bias and parameter a,, a, and p conditions. The individual influences of at, a, and p on the roots (nulls) of D2 and D3 are readily observed in eqns. 6-9. The numerator of D2 is a first-order polyno- mial in a, and in p and is independent of a,, while the numerator of D3 is parabolic in p and a first-order pol- ynomial in both al and a,. The parabolic gate drive component a,, which appears only in the numerator of D3, provides a direct means of dynamically nulling D3 and is the counterpart of al in the numerator of D2. In the absence of this component (a2 = 0), D3 can only be nulled by means of fl and has real roots for 0.25 5

< 3.5 for a wide range of bias conditions if 0, 2 (y/24) VB-3'2 as is typically the case. While this nulling has been demonstrated experimentally [6], it is delicate and only possible because mobility effects (0, # 0) can be offset by suitable values of p. Since D3 is owed entirely to the body effect ( y # 0) and to mobility mod- ulation by transverse fields (6, # o), predicting D3 nulls is contingent upon accurately modelling both effects. While body effects are adequately modelled, the modu- lation of mobility is signal-dependent, and difficult to predict to the same degree of accuracy. The parabolic gate drive allows nulling D3 by offsetting known body effect contributions [(y/24)(1 - 3p + 3p2)VB -3'2] by a known gate signal (a,) rather than by an unknown mobility modulation component (e,), and is analogous to the method of reducing D2 in [l-31. In the absence of gate and body drive (a, = a, = p = 0), neither D2 nor D3 can be nulled. Since D2 can be nulled (with neg- ligible effect on D3) by varying al, while D3 can be nulled by varying a, with no effect on D2, the nulling of D2 and D3 is effectively decoupled. These results are confirmed by the relative magnitudes of the sensitivities of D, and D, to a,, a2 and p which are quantified in Section 2.3.

2.2 Conditions for simultaneous distortion component nulls (D2 = D3 = 0) If one sets U, = 0 in eqn. 6, and u3 = 0 in eqn. 7, a single root P((D2=o) and two roots Pll(D3=0, and & I ( D ~ = o ) IEE Proc.-Circuits Devices Syst., Vol. 146, No. I, February I999

are obtained which can be equated separately. Two conditions result between a, and which thus hold when D2 = D3 = 0:

where

Eqn. 10 has real roots if the determinant A, which is given by eqn. 11, is positive, i.e. if

5 Q 2

(12) For our CMOS process (MOSIS), the double inequal- ity (eqn. 12) requires approximately -0.003 V-' I g 5 +0.005 V-' for a wide range of typical bias conditions, which corresponds approximately to +0.25 5 al 5 +l and -0.7 I p I +1.2. Simultaneous nulls D2 = D3 = 0 can thus be achieved only with gate drive and without body drive (p = 0). Fig. 2 shows the linear relationship between a, and p with VsB a parameter when D2 = 0, as in eqn. 6. Fig. 3 shows the parabolic relationship between a, and p with VsB a parameter when 0, = 0,

r

\ -2 1 1 " 1 1 1 1 1 1 ' 1 ' '

-4 -3 -2 -1 0 1 2 3 4 P

Fig.2 condition Dj = 0 with Vss a parameter vG = 4 v, vm = 0.95 v, e = 0.04 v-I, y = 1.04 v"2, 2# = 0.7v

Linear relationships between a, and Ppredicted by eqn. 6 for the

0.005 0.004 0.003 0.002

a -0.001 O.Oob 1 -0.004 -0.005

-1 -0.5 0 0.5 U

1.5 B

Fig.3 Parabolic relationships between a2 and Ppredicted by eqn. 7 for the condition D, = 0 with V,, a parameter al = +OS, 0 = 0.04 V-', y = 1.04 2# = 0.7V

39

as in eqn. 7. Fig. 4 shows the two relationships between aI and a, with VsB a parameter when D2 = 03 = 0, as in eqn. 10. While two values for a1 are possible at fixed a,, since eqn. 10 is not single-valued, we show only those values of al and a, allowed by eqn. 12, which are practical conditions.

-20

Vse=+5 v 0.3

a'

a, = a2 =p = 0 '

-0.003 -0.002 -0.001 0 0.001 0.002 1

a2, V Fig.4 Linear relationships between a, and a2 predicted by eqn. 10 for the simultaneous condition D, = D3 = 0 with V, = 4 V, V,, a parameter and 4 . 7 < p <+l.2 There is no root for Vsa = 0 and only one root for Vsa = + I V

These results yield general conditions which a , , a2 and p must meet so that D2 = 0 and D, = 0 individu- ally or simultaneously. These conditions take the form of ranges in which a l , a, and p must lie so that eqns. 8 and 9 are nulled under the constraints of eqn. 12, and as V, and VsB vary over their useful ranges (1 - 5V approximately). While the exact limits of the various ranges are also process parameter dependent, we have evaluated these for our process (Table 1). In the lowest three entry rows of Table 1, we indicate various combi- nations for al, a, and p which result in D2 = D3 = 0, because of their practical interest.

Fig. 5 shows the variations of D2 with +0.4 I al 5 +0.55 (i.e. the range wherein D2 = 0 and D3 = 0 have real roots) for several fixed values of fl between 0 and + 1. While D2 displays a null for each p, as expected, we note the uniform attenuation of D2 throughout the range, relative to its condition with no gate or body drive (al = a, = p = 0). Fig. 6 shows the variations of 0, with 0 I p 5 +1 at fixed a, = +1/2, and with body bias VsB a parameter. As expected from Fig. 5, D, = 0 for = +1/4 and is relatively insensitive to VsB. More- over, as long as p remains within approximately ,lo% of its nominal value of +1/4, 0, remains at least 70dB below the fundamental. Since the body signal @VD) can be derived from V, by voltage division using

standard, on-chip, passive resistors/capacitors whose values can typically be ratioed to within fl '% without trimming, this method is suitable for monolithic inte- gration.

8 N 0

-80

1 nn , "" 0.4 0.425 0.45 0.475 0.5 0.525 0.55

a1 Fig.5 Variations q f D 2 wJith 0.4 < a, <OS5 atfixed VS, = 2 V rind 0 i P < I a parameter, us in eqn. 8 Note the systematic attenuation of D2 for all values of a, relative to the con- dition a, = 0, including a null for each value of 0. V, = 3 V, V,, = 0.5V

0 0.25 0.5 0.75 1

0 Fi .6 Variutions of D, with 0 < P < I at j k e d a, = 0.5 and I V < V,, < ?v a parameter, us per eqn. 8 Note the systematic attenuation of D2 for all values of p relative to the condi- tion p = 0, including a null near 0 = 0.25 which is relatively insensitive to var- iations of VTB VG = 3V, I:, = O.SV, a, = + O S

Fig. 7 shows the variations of D, with -0.003 I a, 5 +0.005 (i.e. the range wherein D, = 0 and D, = 0 have real roots) for the condition at = +1/2, /? = +1/4 shown in Fig. 6 where D2 = 0. For each of several fixed values of V,, between 1 - 4V, Fig. 7 shows that a, can be tuned to attenuate D,. At fixed VsB, D, remains at least 80dB below fundamental in the worst case condition (VsB = 4V), even if a, varies by f25% about its nomi- nal value. Since the parabolic gate signal component (a2VD2) can be derived from VD by well known CMOS [9] or BiCMOS [lo] squaring circuits whose precision

Table 1: Gate and body drive amplitude ranges for bias voltages V, and V,, ranging from 1 - 5V

a1 a2 P 4 (a,, p) = 0 D3(al, a2, p, pz) = 0 dimensionless V-' dimensionless possible? possible?

0 0 0 no (-20dB typically) no (-65dB typically)

0.4 I a1 i 0.6 0 0 yes [I-31 no

0 0 1.5 I fl I 3 Yes no

0 -0.05 5 a2 5 +0.013 0 no Yes

0 0 0.25 I IpI 5 3.5 no yes i l l 4 I al 5 +I -0.003 I az 5 +0.005 -0.7 5 f i I +1.2 General conditions for Dz = 0 and D3 = 0 to

have real roots as in eqn. 12 0.525 f 1% -0.003 I az 2 +0.005 0 +I12 f 1%

0.425 f 1% 0 + I f 1%

Particular conditions which achieve Dz = D3 5 -70dB -0.003 5 az 2 +0.005 +1/4 f 1%

40 IEE Pro<.-Circuits Devices Syst.. VX. 146. No. I , Fchruary 1999

exceed the present requirements, this method is likewise suitable for monolithic integration.

a l = a 2 = P = 0 -60 -

-1201 I l l l l 1 l “ ’ l l l ‘ l l l l I ‘ l l l l ‘ ‘ l ‘ l l l ’ -0.003 -0.001 0.001 0.003 0.005

%, v-’ Fig.7 at D2 = 0 (i.e. with a, = 0.5 and P = 0.25 as in Fig. 6 ) A-&. 9 Note the systematic attenuation of D, relative to the cuadition a, = 0, includ- ing a null for each value of 1 V 5 VsB 5 4V where D2 - D3 0. V, = 3 V, V, = 0.5V

Variations of D, with 4.003 V’ I a < +0.005

2.3 Sensitivity analysis We derive the sensitivities of D2 and D3 to al, a, and p from eqns. 8 and 9 by using the conventional definition for the sensitivity of a system parameter M to a varia- ble y in that system SyM = (’y/M)(aM/ay)

s i 3 = (A) (6)

The above sensitivities to a,, a, and /3 are rea&ly eval- uated for any device and bias conditions. In Table 2, we list the functional dependences of these sensitivities to a,, a,, p, VG and VB for the following typical condi- tions: 0, = 10-I (-20dB), D3 = 5 x lo4 (-66dB), 0, =

Vp = 1V. These dependences are merely intended to quantify the relative influences of al, a2, p, VG and VB on D, and D3, and must be regarded as lower bounds since sensitivities increase in the vicinities of nulls. Table 2 indicates that 0 2 is roughly as sensitive to al as to p, and insensitive to a,, while D3 is roughly 7 - 50 times more sensitive to a, than to al or p. The signifi-

0.04 V-’, y 1 V I , p 1, V G - V T = lV, VsB 2V,

IEE Proc -Circuits Devices Syst.. Vol. 146. Ab. f , February I999

cance of these results is that the tuning, or nulling, of D, and D3 is effectively decoupled and is a systematic two-step process: a, can first be tuned to null D, (thereby causing a change in D, since S$ # 0), then a, can be tuned to null D3 with negligible effect on D,. No ‘iterations’ are required. The effectiveness of this simple procedure is confirmed even by computer simulations as shown in Table 3. In the absence of a2, by contrast, the simultaneous nulling of 0, and D3 is much more delicate, though possible [6], since both S p and Sf3 are nonzero; tuning either p or al affects both D2 and D3 which are then strongly coupled.

Table 2: Functional dependences of distortion sensitivi- ties with respect to a,, o+, p, VG, VE

Sesitiviw Approximate function functional Equation Parameter range

dependence used

sa92 5 a1 13 +I14 5 a1 5 + I

s 2 0 14 any a2 value

sa93 10 al 16 +I14 5 a1 5 +I S 2 500a2 17 -O.O03V-’ 5 a2 5 +O.O05V-’

S p 1.5p 15 -0.75p5+1.2

18 -0.7 P S +1.2 s p 75P

S@ -Vr1/2 9 1 v 5 v g s 5 v

vp= 1 v

8 2 v < VGs5v

8 2 v 5 VG55v -vG

-vG

S a -3OV~312 9 1 v s vES5v

D2 = IO-’ (-20dB), 4 = 5 x IO4 (-66dB), BT= 0.04 V-’, y= 1 V-’,

Table 3: Decoupling between 4 and 4 nulls as demon- strated by SPICE harmonic distortion predictions

a1 a 2 p D2dB 4 d B Comments

0 0 0 -17.3 -65.5 no gate or body drive

0.5 0 114 -35.2 -76.1 initial setting

0.56 0 1/4 4 6 . 0 -72.2 increment a1 only

0.585 0 114 -77.0 -71.1 D 2 = nulled

0.585 -0.0455 114 -76.9 -68.3 fix al = 0.585, increment a2

0.58 0 114 -61.0 -71.3

0.585 4.0405 114 -77.1 -78.0

0.585 -0.0385 114 -77.5 -90.5 D2 and D3 nulled

VG = 3V, VsE = 2V, Vp = 0.5V. While the model for e+vG,) is quantitatively inaccurate in SPICE, qualitative results are unaf- fected (Section 3.2)

3 Experimental results and computer simulations

3 , l Accuracy of the mobility modulation model The mobility modulation parameter f3=, which is critical to the accurate prediction of distortion parameters, is inadequately modelled in standard simulation pro- grams such as SPICE wherein the user cannot, gener- ally, specify OT as an ‘input parameter’. We have extracted experimental values of at nulls of D2 and D3, using eqns. 6 and 7, for 2V 5 VG I 5V and 0 I V, , 5 5V, and found these data to fit the following empiri- cal relationship:

&(VGB) “N ( - 0 . 0 0 9 V ~ ~ + 0.086) V-l

41

This finding is consistent with the assumption dOdy)/ d y = 0 made prior to deriving eqn. 3 for In, to the extent that the predictions of our model for 0, and D3 agree closely with measurements (+I dB) down to the limit of our instrument (Hewlett Packard 3585A spec- trum analyser), or approximately 90dB below funda- mental. For V,, 2 3V approximately, our empirical expression for OdV,,) is in very good quantitative agreement with the Schwarz-Russek theory [SI which predicts the high-transverse-field mobility modulation component. At relatively low transverse fields, where band-bending effects dominate those of mobility modu- lation, our data for OdV,,) increasingly deviate from the Schwarz-Russek model as expected. We have also 'extracted' Od VGB) numerically from PSPICE simula- tions at nulls of D2 and D3 for the same experimental conditions, and found that this program typically underestimates \O,l by a factor ranging between 10 and 50. For example, at VGs = 3V and V,, = 2V, the experimental value for = 0.04 V-I, whereas SPICE yields 0.0014 V-I. Consequently, the nulls of D2 and D, shown in Figs. 5-7 are predicted by PSPICE for values of al, a, and p, which are offset from their respective experimental values. Otherwise, SPICE does duplicate Figs. 5-7.

While the above simulation conditions correspond to the experimental conditions indicated in Figs. 5-7, we have verified, as may the reader, that SPICE duplicates Figs. 5-7 if one uses the value OT = 0.0014 V-I in eqns. 5-9.

'G + "g(Vin)

1 I

1 1 -

O r

-20

-40 m U

-60

'6 - VbO/in)

Fig. 8, nents for n-channel MOSFETs WIL = 1OOpn/10Opmun, Vti = 5V, VrB = 4V, V,,, = 2 Vpp, 1 kHz sinusoid

E.xperinzentu1 circuit used to tnensure harmonic distortion compo-

: I

3.2 Unbalanced and balanced circuit topologies We have found quantitative agreement between our model and measurements under various conditions listed in Table 1 for a single-MOSFET integrator. In a balanced topology, Fig. 8, even-order harmonics are reduced by virtue of signal balancing so that mis- matches among nominally identical devices set the lower limit for D,. Odd-order harmonics, however, are not suppressed. Among the two possible methods for suppressing D3 in a single device (Table l), the simplest is the body-drive only (a, = a, = 0). In Fig. 8, the differential output voltage is proportional to the differ- ence of the two MOSFET drain currents [ZD(V,) - ID(- Vjn)] , whose distortion polynomials are different from eqns. 6 and 7. While an analytical solution similar to that of a single device is possible in principle, the analysis is complicated because the opamp input termi- nals carry a common-mode signal comprising even har- monics of the input signal. Unlike the single MOSFET

42

integrator, the balanced MOSFET source terminals are not at a virtual ground, which gives rise to intermodu- lation distortion components. Hence the single-device equations for 0, and 0, (Section 2) cannot directly be used for the balanced topology and thus, even for this apparently simple extension, an accurate simulation program is a practical necessity.

O r 1

-20

-40 m U

-60

-80

-100

frequency, kHz Fig. 9 gale or body signals (a , = a2 = p = 0)

Single-ended (unbalanced) circuit .spectrum nirusurcd with no

-inn -80~,L-lwL- . _ _

0 1 2 3 4 5 frequency, kHz

Balanced circuit spectrum measured with no gate or body sig- Fi n a F i a , = a2 = p = o j

10

The 1OOpn long and wide n-channel MOSFETs in Fig. 8 were integrated in a standard, double-polysili- con, 2 p p-well CMOS process (MOSIS, Tinychip runs #M94W and #N 13H) whose parameters were carefully extracted (Section 2.1). Other experimental conditions were V , = 5V, VsB = 4V, (+Vi,) a lkHz, 2Vpp sinusoidal signal. In Fig. 9, where half of the balanced circuit is disabled, we observe the single- ended (unbalanced) distortion components 0, = -19.4dB and D3 = -64.8dB under conditions of no gate or body drive (al = a, = /? = 0) in quantitative agree- ment with eqns. 5-9. The spectrum in Fig. 10 is the measurement for the balanced topology under the same bias and drive conditions, and yields D, = -69dB and D3 =: -64.8dB. While the reduction in D2 corresponds to device matching of the order of l'%, D, is unchanged. In Fig. 11, finally, we observe the condition

= 0.45 under identical bias and gate drive conditions. While a further reduction in D, is achieved because the individual a2 terms in eqn. 6 are reduced, D3 is below the resolution limit of our spectrum analyser (5 -90dB). This experimental condition not only dem- onstrates the condition D2 = D, = 0 for the balanced topology, but allows a crucial additional verification of our analytical model as well. By evaluating the differ- ence [ID( Vin) - ZD(-Vi,,)] numerically, using eqn. 3 twice, and performing a Fourier decomposition on this difference, our model correctly predicts D2 = 0 and

IEE Proc.-Circuita Devices Sq'sl.. Vol. 146. No. I . F?hrurrry I999

D3 = -95.7dB with OAV,,) = w9U) = 0.005 V-’, whereas SPICE predicts D2 = 0 and, erronmusly, D3 = 47.3dB.

O L I -40 - * O I II ” -60 II -80 -

-100 0 1 2 3 4 5

frequency, Ib(z

Fig. 11 Harmonic suppression in balanced circuit (p = 0.45)

4 Conclusions

We have presented a general analysis of the dominant distortion components of the drain current of an inte- grated long-channel MOSFET in nonsaturation with signals simultaneously applied to the drain, gate and body terminals. We have derived accurate analytical expressions, in closed form, for the odd (D3) and even (D2) distortion components which explicitly account for all bias and relevant process parameters, and for the modulation of the inversion layer mobility by trans- verse electric fields (€$(VGB)) which was shown to be a critical effect. We have derived the conditions for the existence of real roots for the polynomials D2 = 0 and D3 = 0, and we have quantified the relationships among these roots and their variations with, and sensi- tivities to, the applied gate and body bias and signal amplitudes. We have shown that D2 and D3 can be

IEE Proc -Circuits D w e s Syst., Vol 146, No I , February 1999

nulled individually and/or simultaneously by a wide range of practical combinations of gate and body sig- nal amplitudes under normal bias conditions. We have

==- shown, in particular, that if the gate is driven by a lin- ear and by a parabolic signal (al V, + a2 VD2), D2 and D3 are decoupled and can simultaneously be nulled by separately setting the constants a, and a2. The method is believed to be suitable for monolithic integration where highly linear, tunable, MOSFET resistors are required.

5 References

4

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