Modeling for Statistical Timing Applications · Affine Delay Models • Why model delays as linear functions of parameters? – Digital circuits are strongly nonlinear with respect

1 CADENCE DESIGN SYSTEMS, INC. BMAS 2006

Modeling for Statistical Timing Applications

Joel Phillips, Cadence Berkeley Laboratories

Collaborators: L. Miguel Silveira (INESC-ID/CBL) Luis Guerra e Silva (INESC-ID/CBL), Zhenhai Zhu (CBL)

2 BMAS 2006 – Modeling for SSTA

Outline

• Background: Statistical Static Timing Context

• Incorporating Variability via Affine Delay Models

• Cell Modeling Under Parameter Variation

• Interconnect Modeling Under Parameter Variation


Worrying About Variability

• What it is– Undesired fluctuation of circuit figure

of merit – e.g. gate delay, leakage, ….

• Why do we care ? – (It’s widely believed that) relative

magnitude of variability is increasing – approaching physical limits of MOS technology

– Increased susceptibility: Devices in small geometries at low voltages are more sensitive to perturbation

Variation

Nom

inal

Min

Max

A 22 nm MOSFETIn production 2008

[Asenov et al, “Simulation of Intrinsic Parameter Fluctuations inDecananometer and Nanometer-Scale MOSFETs”, ELECTRON DEVICES, SEPT 2003]


The Usual Suspects

• Processing condition shift (“dial spinning”)

– Wafer to wafer, fab to fab, same fab over time

• Environmental – thermal gradient, IR drop

• Wafer level parameter nonuniformity

– Oxide thickness, etch rate vary on wafer scale

• Across-die systematics

– Optical lens aberration

• Local systematic – tied to (and predictable from) layout

– Sub-wavelength lithography effects, CMP

• Stochastic – random device-to-device variation

– Channel dopant fluctuation effects, line edge roughness


Analyzing Variability Effects

• Setup

• Hold

clock

in clock

out clock

data

setupoutjji

ini tlTdl −+≤+ ,

inil

outjl

setupt holdtjid ,

jiinihold

outj dltl ,+≤+

inl1

innl

combinationalblock

outl1

outml

i j

• Analog folks….old news! – SPICE, Monte Carlo,

cocktail napkins ….

• Digital folks – Meet timing constraints?

– Meet power budget?

– Scalability, automation, ….


Static Timing Analysis (STA)

• Abstract timing analysis to propagation (T,s) through graph

• Logic operation reduced to max computation : simple but conservative analysis

• Delays from wires, cells represented notated on arcs of graph

• From arrival times, compute slacks, critical paths, …

• Note: delays depend on selected operating and process conditions

cell

max

sum

4.05.0

9.0

sum1.0 at=1.0

sum

1.02.0

3.0

Waveform slope + arrival time


The Case For “Statistical Timing” (SSTA) So

urce

: Nar

diet

al,

Tran

s. Se

mM

anuf

‘99

- may be overly pessimistic

- may not catch all problems

Reg i Reg j

• “Traditional” worse-case analysis

– Pick a set of operating conditions (corners)

– Run STA for each “corner”

• Which corners to pick? Exhaustive analysis may not be possible!


Timing Analysis in Presence of Process Variation

• “Statistical Timing”methodologies intensely researched in past few years

• Intellectual paradigm: propagate some parametric quantity (e.g., distributions) through timing graph

• Key issues

– Max function computation

– Tracking parameter correlations

– Delay models


Affine Delay Models

• Why model delays as linear functions of parameters ?

– Digital circuits are strongly nonlinear with respect to circuit inputs, but celldelays are often close to linear with respect to process parameters over relevant parameter ranges.

– Introduces explicit dependence of all quantities on specific variation sources

– Simplifies certain computations in analysis

• Affine parametric delay formulation:

λλλλλ

λλλλ

∆+=∆⇔⎥⎥⎦

⎤

⎢⎢⎣

⎡−

∂∂+=− ∑

=

Tx

p

ii

isxxxxx 0

1000 )()()()(

0incremental

variationnominal

point

sensitivity


cell

Timing Analysis with Parametric Delays

• Typical model: Gate and interconnect delays are affine functions of ∆λ.

• Circuit delays and arrival times are piecewise-affine functions of ∆λ.

– Result from sum and max.

4321 11.007.032.024.05 λλλλ ∆−∆+∆−∆+=d

max

sum

λ∆+ 8.04.0λ∆− 7.15.0

λ∆− 9.09.0

sum1.0 at(∆λ)

sum

λ∆+ 3.01.0λ∆+ 4.02.0

λ∆+ 7.03.0

max

sum sum

at(∆λ)

sum

∆λ

at


Tractable max computations

• Given: convex n-piece affine function .

• Compute: single affine function .

• Such that: in some sense

• Example: Assume Gaussianity for all parameters. Compute Y to match first two moments of X. Lots of papers.

)(max)( 0,...,1

λλ ∆+=∆=

Tii

nixxX

λλ ∆+=∆ Tjj yyY 0)(

)()( λλ ∆≥∆ XY

∆λ


Electrical Analysis Stack

• Practical question: how to get the parametric delay models from all this stuff?

Synthesis, Optimization, ECO

Timing

Extraction

Cell Characterization

Parasitic Reduction

Transistor-LevelSimulation

Delay Calculation

Device/Interconnect Characterization

124.05 λ∆+=rcT

→∆← W

Proc

ess

Mod

elin

g

Envi

ronm

enta

l M

odel

ing


Model Construction Challenge

• Black-box approaches: post-process analysis data

– Finite-differencing for sensitivities

– Response-surface models (RSMs) and other curve-fitting approaches

VT

Delay

• Problems – Most programs produce non-smooth output

[timing, SI, circuit simulation, field solvers, extraction, parasitic reduction]

– Slow. Multiple runs per coefficient in best case. Numerical noise requires heavy over-sampling excessive number of analysis runs.


Tools in the Bag

• Perturbation Theory

– Taylor series, Volterra series, orthogonal polynomial representations

• Data Compression

– Principal Components (PCA) / Singular Value Decomposition (SVD)

– Adjoint methods


Perturbation Theory


Basic Perturbation Analysis, I

• Consider solving nonlinear circuit equations (KCL)

• Suppose input is decomposed into nominal plus perturbation (assumed small)

• Assume response (circuit node voltages) can be decomposed into operating point (bias) + perturbation (assumed small)

mg

uvi =)(

• Assume current-voltage relation can be treated perturbatively as well [e.g., Taylor series]

vvivivi ∆

∂∂+= )()( 0

uuu ∆+= 0

vvv ∆+= 0


Basic Perturbation Analysis, II

• Collect first-order terms equation for perturbation

• Physical interpretation:

– LHS: small-signal circuit model

– RHS: equivalent “perturbation” sources

mg

• Substitute series expansions into original equation

• Collect zero-order terms equation for bias point

uuvvivi ∆+=⎥⎦

⎤⎢⎣⎡ ∆

∂∂+)( 0

00 )( uvi =

uvvi ∆=∆

∂∂


Perturbation Analysis, Generalized

• Nonlinear Response (higher-order terms)

• Parameter Variation

• Time-Varying Operating Point

λλ

∆∂∂+∆

∂∂+= ivvivivi )()( 0

...)()()( 2

2

0 tohvvv

iivvivivi +∆⊗∆

∂∂+∆

∂∂+∆

∂∂+= λ

λ

DIstortionSources

MismatchSources

)1(mg

)2(mg )3(

mg .etc

)())((),()(0

0 tvvitvitvi

tv

∆∂∂+=

)())((),()(0

0 tvvqtvqtvq

tv

∆∂∂+=


Notable Applications

• AC Noise Analysis

• RF Noise Analysis

• Volterra-based distortion

• Time-varying / Weakly nonlinear automated macromodeling

• Parametric interconnect reduction

• Mismatch analysis

• Mismatch parameter extraction

• Parametric cell delay characterization

• Parametric cell delay calculation


General Observations • Decomposition of Nonlinearity

– Assumes circuit responds to perturbations (noise, process variation) in weakly nonlinear way, but includes strongly nonlinear circuitbiasing

• Matrix Equation Structure

– Basically similar for all orders of expansion (recursive structure)

– Basically similar for all applications

– Basically similar regardless of derivation

[ ] ),()( )1(,0

)(0

−∆=∆ kk vvRHSvvY K

Zero-PerturbationAdmittance Matrix

Reponse to order k

Sources from response up to

order k-1


Interactions of Models and Statistics

• Given parametrized models…

• Statistics can be obtained

– Through final analysis / simulation

– Often using standard linear algebra identities

• Please do not embed statistical assumptions in the model derivation process!!!!

L+∆+∆+= tvtLdd VcLcTT )0(


Cell Models


Table-Based Delay Model (.lib)

• Waveform model: linear ramp

• Load model: lumped capacitance

• Cell model

– Pin-pin delay

– Output slew

• Delays, output slews tabulated for each pin-pin arc as functions of input slew, output load

slew sCL

0.94920.95760.95940.6

0.35280.35880.35970.2

0.14400.14920.14980.03

0.30.10.03CL\ s

• Issues:

– Lumped capacitance bad model of interconnect

– Real waveforms not ramps (tails, non-monotonic)

• Hack: Ceff.. . Try to transform interconnect into “effective”capacitance seen by gate depending on…..


Ceff Methodology (idealized)

• Variables: slew, effective cap, output waveform points

• Model output must match at table characterization points

• Require equality of average current drawn by “actual” load and effective capacitance model (as a function of interconnect parameter variation) !

effC)(svm

),,( Cstyout

s 1d 2d

VddaCsCdyout 11 ),),(( =

)(),( λπIsCIC =


Perturbation Analysis: Non-Intuitive, but Possible!

• Base equations – Assume we solve these for some s, C

• Assume perturbation solution

VddCsCdyCsCdy outout α=− ),),((),),(( 12

)(),( λπIsCIC =

CCys

syC

Cd

dyCsCdyCsCdyout ∆

∂∂+∆

∂∂+∆

∂∂

∂∂+→ ),),((),),(( 000

k

p

k k

CCC

II

ss

sCIC

CsCI

sCI

λλ

λλ π

π ∑=

∆∂

∂→

∆∂

∂+∆

∂∂

→

1

)()(

),(),(),(


Analytic Ceff equations

• Solve small matrix equation

• Final Computations

– Ceff perturbation

– from tables

⎥⎦

⎤⎢⎣

⎡=⎥

⎦

⎤⎢⎣

⎡∆∆

⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡

∂∂

∂∂

∂∂+

∂∂

∂∂

∂∂

10

eff

drv

CC Cs

CI

sI

Cy

Cd

dy

sy

sd

Cd

∂∂

∂∂ ,

k

Iλ

λπ

∂∂ )(

(from interconnect sensitivity computation)

(model parameters)

λλ ∂∂

∂∂ ds ,

)()(

parametersslewparametersdelay


Current-Source Driver Models • Much better at dealing with

real-world interconnect effects

– Blade/Razor [Croix/Wong]

– ECSM : equivalent current source model [Cadence]

– CCSM : composite current source model [Synopsys]

),(or )(

outin

out

vvivi

-+

-

+outv

inv load

VCCS:

• Parametric analysis can be performed by similar exercise in perturbation theory to obtain ∆vout as function of parameters

∆v

∆t

tc

Threshold

Histogram

TimePDF

t

∆v(tc)SR(tc)

∆t =

Hist

ogra

m

VoltagePDF

v

∆v

∆t

tc

Threshold

Histogram

TimePDF

t

∆v(tc)SR(tc)

∆t = ∆v(tc)SR(tc)

∆t =

Hist

ogra

m

VoltagePDF

v

Fig. courtesyK. Kundert


Interconnect Models


Base Equations for RC Model

[ ]htswDuLxy

BuxGdtdxC

=+=

=+

λ

λλ

,

)()(

w

s

th

Variation-Aware Model Order Reduction

L

L

+∆+∆+=+∆+∆+=

22110

22110

)()(

λλλλλλ

GGGGCCCC

Example parametric form:

Goal is to compute reduced model in similar form that is amenable to fast delay calculation (previously described)

Reduced interconnect models by themselves are not so useful.


Generating Parametric Reduced Models

• Consider constant matrices

• Affine models in affine models out! – (yes, intra-die is still possible)

)(λG )(ˆ λGRVT

LV

Projection-based reduction approach

[ ]

L

L

L

+∆+∆+=

+∆+∆+=

+∆+∆+=

22110

22110

22110

ˆˆˆ

)(ˆ

λλ

λλλλλ

GGG

VGVVGVVGV

VGGGVGTTT

T


Picking Projection Matrices : Moment Matching

• Krylov family (interpolation-like) – Choose projection matrices to match moments of transfer function at

selected frequency points

– Extensions to parametric case conceptually easy, problematic in computational application

,)(,)(colspV 12

11 KpAIspAIs −− −−⊃

[ ]L

K

Km

mlk

lkmlk

n

sMBGsC

sx

2,...,,

1,,,

11

)()(

),,(

λλλλ

λλ

∑=+= −

K,,,colspV mlkM⊃


Projection Spaces Via n-D Moments

• Issues– Exponentially

increasing cost with order if all moments kept

– Not clear how to “prune” moments

– Hard to achieve good error / effort tradeoff

Practical

What we need


• Option 1: Ignore the problem. – Use the nominal-case projection matrices and hope for the best. Works

more often than you might think.

• Option 2: CORE (X. Li et al) – Combination of n-D moment matching and Volterra series

(perturbation)

– Exposes special structure in n-D moments

• Option 3: V-PMTBR (Phillips et al) – Compress data in operator range

– Based on approximate computation of stochastic Grammian

[ ] [ ]∫ ∫∞

∞−

−− ++= λωλωλλλλ ddpGsCGsCX H ),()()()()( 1

Avoiding Moment Explosions


PMTBR Visually Speaking RR ∆+ 10 λ

020 CC ∆+ λ

131 CC ∆+ λ

Ω3

~1MHz fF7.2fF0.5

~10GHz

Ω2.3fF1.5 fF5.2

~1GHz

Ω9.2

fF5.5 fF2.2

Compress

Simulate

Sample

Projection Vectors


2 2.5 3 3.5 4 4.5 5 5.5 610

−5

10−4

10−3

10−2

10−1

100

order

rela

tive

erro

r

PMTBR Convergence Behavior

Number of Samples

Variation case:550 nodes31 parameters

Rel

ativ

e Er

ror i

n Lo

g Sc

ale


−9 −8 −7 −6 −5 −4 −3 −2 −10

200

400

600

800

1000

1200

1400

Relative Rrror in Log10

Scale

Num

ber

of C

ircui

ts

Error Histogram With Small Fixed Order

Relative Error in Log10-Scale

Num

ber o

f Circ

uits

~40k nets # Samples = 2


Model Complexity Comparison

• PMTBR algorithm with automatic order selection compared on several thousand large nets with >> 20 process parameters

• Model size increases 40-70% on average(depends on parameter ranges)

– Roughly correlates to computational overhead of parametric models in parasitic reduction for SSTA

Nominal Parametric


Summary

• Variability analysis is becoming a first-order concern

– Power (esp. leakage), timing, physical/functional yield interaction

• Methodologies are still being developed

– “Full statistical” is a big change –some value to it, but not the whole story

• Inevitable that models will become richer

– While keeping analysis times under control

– While fitting into very complex analysis/optimization stack

Documents

Modeling for Statistical Timing Applications · Affine Delay Models • Why model delays as linear functions of parameters? – Digital circuits are strongly nonlinear with respect