MIPS Single-Cycle CPU

MIPS Single-Cycle CPU Group 22BNguyễn Bình NamHồ Anh TrangNguyễn Bảo Trung

MIPS Single-Cycle CPU• design a simple 32-bit MIPS Single-Cycle

CPU. • The design includes support for execution of:- memory-reference instructions: lw, sw- arithmetic-logical instructions: add, sub,

slt,xori- control flow instructions: bne, j, jr

MIPS Single-Cycle CPU- CPU executes each instruction in only one

clock cycle time.- a clock cycle time must be chosen such that

the longest instruction can be executed in one clock cycle.

- Require 2 memories( data and instruction).

MIPS Single-Cycle CPU• Generic implementation- Use the program counter (PC) to supply

instruction address.- Get the instruction from memory.- Read registers.- Use the instruction to decide exactly what to

do.

MIPS Single-Cycle CPUBuilding Blocks

MIPS Single-Cycle CPU

MIPS Single-Cycle CPU

• op • rs • rt • rd • shamt • funct

• 31:26 • 25:21 • 20:16 • 15:11 • 10:6 • 5:0

• op • rs • rt • address

• 31:26 • 25:21 • 20:16 • 15:0

• op • target

• 31:26 • 25:0

• R-Type: op=0

• Load/Store: op=35 or 43

• Jump: op=2

MIPS Single-Cycle CPU Design

- Data memory.- Instructions memory.- Register file.- ALU.- PC Block.- Control block.- Extend-sign block and shift-left2 block.


- Data memory.- Instructions memory.- Register file.- ALU.PC Block.- Control block.- Extend-sign block and shift-left2 block.

PC block

Fetching instructions:• ADD, SUB, SLT, XORI, LW, SW:

PC’ = PC +4• BNE: PC’ = PC + 4 + offset x 4• J:

PC’ = PC[32-28]_26bit target_00• Jr: PC’ = rs x 4

PC block


- Data memory.- Instructions memory.- Register file.- ALU.- PC Block.Control block.- Extend-sign block and shift-left2 block.

Control block- Select the registers to be read (always read

two)- Select the 2nd ALU input - Select the operation to be performed by ALU- Select if data memory is to be read or written- Select what is written and where in the register

file- Select what goes in PC

Control block

Control block

Control block

Control blockmodule Control(Opcode, //Input

RegDst,Jump,Branch,MemRead,MemtoReg, //Output ALUOp,MemWrite,ALUSrc,RegWrite,Extend //Output );

input [5:0] Opcode;output RegDst, Jump, Branch, MemRead, MemtoReg, MemWrite, ALUSrc, RegWrite, Extend;output [1:0] ALUOp;reg RegDst1,Jump1,Branch1,MemRead1,MemtoReg1,MemWrite1,ALUSrc1,RegWrite1,Extend1;reg [1:0] ALUOp1;

buf #50 buf0(RegDst,RegDst1);buf #50 buf1(Jump,Jump1);buf #50 buf2(Branch,Branch1);buf #50 buf3(MemRead,MemRead1);buf #50 buf4(MemtoReg,MemtoReg1);buf #50 buf5(MemWrite,MemWrite1);buf #50 buf6(ALUSrc,ALUSrc1);buf #50 buf7(RegWrite,RegWrite1);buf #50 buf8(Extend,Extend1);buf #50 buf9(ALUOp[1],ALUOp1[1]);buf #50 buf10(ALUOp[0],ALUOp1[0]);

Control blockalways @(Opcode) begincase (Opcode)

6'b000000 : begin // Rtype#100RegDst1 = 1'b1;Jump1 = 1'b0;

.

.

.

.default : begin //others

#100RegDst1 = 1'bx;Jump1 = 1'b0;Branch1 = 1'b0;MemRead1 = 1'bx;MemtoReg1 = 1'bx;ALUOp1 = 2'bxx;MemWrite1 = 1'b0;ALUSrc1 = 1'bx;RegWrite1 = 1'b0;Extend1 = 1'bx;end

endcaseendendmodule

Control block


- Data memory.- Instructions memory.- Register file.- ALU.- PC Block.- Control block.Extend-sign block and shift-left2 block.

Extend-sign block&shift-left2 block.Extend-sign ( for BNE instruction )• MSB = 0 => add 16 0-bits in front of.• MSB = 1 => add16 1-bits in front of.Extend-0 ( for XORI instruction)Add 16 0-bits in front of regardless of MSB.Shift-left2• digit’ = digit_00

MIPS Single-Cycle CPU DesignCalculate cycle time assuming negligible delays except:

- Memory (2ns), ALU and adders (2ns), Register file access (1ns)

Thank for your listening !

Simulation

Documents

MIPS Single-Cycle CPU