Midterm Review - users.soe.ucsc.edurebecca/comp_arch/... · Midterm Review CMPE 012: Computer Systems and Assembly Language University of California, Santa Cruz Created by Rebecca

Midterm Review

CMPE 012: Computer Systems and Assembly Language

University of California, Santa Cruz

Created by Rebecca Rashkin

Presented on 11 May 2018

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Midterm Review Page 1 of 21 UCSC CMPE 012

Numbering Systems

Count

Decimal Hexadecimal Octal Binary

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Positional Number System Equation

umbern = ∑n−1

i=0di · b

i

d = ____________________ b = ____________________ n = ____________________

Example

183210 = (1 * _____ + 8 * _____ + 3 * _____ + 2 * _____)

Number System Conversion

Conversion to Decimal

0xA3 = (A * _____ + 3 * _____) =


Conversion from Decimal

Example

Convert 2710 to octal (base 8)

_____ _____ _____ _____ _____

i: 4 3 2 1 0

_________________________________

i = 0 --------------------

N =

q =

r =

Does q = 0?

i = 1 --------------------

N =

q =

r =

Does q = 0?

i = 2 --------------------

N =

q =

r =

Does q = 0?

Easy Binary Conversions

Some numbering systems are easy to convert to and from binary:

Binary <-> Octal

When converting binary to octal, separate bits in groups of _____

What happens if the number of binary digits are not divisible by _____?


Example

Convert 11011112 to octal

= _____ _____ _____

Convert 318 to binary

3 1

= _____ _____

Convert 110011012 to octal

Convert 1758 to binary

Binary <-> Hexadecimal

When converting binary to decimal, separate bits in groups of _____

Convert these groups to hexadecimal digits.

Example

Convert 11011112 to hexadecimal

Convert 0xBB8 to binary

Octal <-> Hexadecimal

First convert to binary, then to the other base.

Example

Convert 0xC3B0 to octal

Convert 1118 to hexadecimal

Note

“10” in any base system is equal to the value of the _______________

0x10 =

108 = 10

2 =

Know your powers of 2!!

20 21 22 23 24 25 26 27 28 29 210

211 212

1 2


MOSFET Transistor

Draw a PMOS

Closes when gate = _____

Draw an NMOS

Closes when gate = _____

TRANSISTOR CIRCUIT SWITCH REPRESENTATION

IN = 0

OUT = ?

IN = 1

OUT = ?

Logic Gates

Draw:

A B NOT AND NAND OR NOR XOR XNOR

0 0

0 1

1 0

1 1


Combining MOSFETS

SCHEMATIC TRUTH TABLE

Draw 2 NMOS in series, with one end connected to

ground and the other connected to out

___ out

⏚ gnd

What are we missing?

A B Out =

0 0

0 1

1 0

1 1

Draw 2 NMOS in parallel, with one end connected to

ground and the other connected to out

___ out

⏚ ⏚ gnd


A B Out =

0 0

0 1

1 0

1 1

Draw 2 PMOS in series, with one end connected to

power and the other connected to out

___ pwr

___ out


A B Out =

0 0

0 1

1 0

1 1

Draw 2 NMOS in parallel, with one end connected

power and the other connected to out

___ ___ pwr

___ out


A B Out =

0 0

0 1

1 0

1 1


CMOS Logic

Create a NOT gate from MOSFETS

Create a NAND gate from MOSFETS

Create an AND gate from MOSFETS

Create a NOR gate from MOSFETS

Create an OR gate from MOSFETS

Boolean Identities

Logical Inverse ~0 = 1

~1 = 0

Involution ~~A = A


Dominance A + 1 = 1

A ⋅ 0 = 0

Identity A + 0 = A

A ⋅ 1 = A

Idempotence A + A = A

A ⋅ A = A

Complementarity A + ~A = 1

A ⋅ ~ A = 0

Commutativity A + B = B + A

A ⋅ B = B ⋅ A

Associativity (A + B) + C = A + (B + C)

(A ⋅ B) ⋅ C = A ⋅ (B ⋅ C)

Distributivity A + (B ⋅C) = (A + B) ⋅ (A + C)

A ⋅ (B + C)=(A ⋅ B) + (A ⋅ C)

Absorption A ⋅ (A + B) = A

A ⋅ (A + B) = A

DeMorgan's A + B = ~(~A⋅~B)

A ⋅ B = ~(~A + ~B)

Images source: https://www.allaboutcircuits.com/technical-articles/boolean-identities/


De Morgan’s Law

Let’s convince ourselves of De Morgan’s Law with a truth table:

A + B = ~(~A⋅~B)

A + B

A B A + B

0 0

0 1

1 0

1 1

~(~A⋅~B)

A B ~A ~B ~A⋅~B ~(~A⋅~B)

0 0

0 1

1 0

1 1

Do the truth tables match?

A ⋅ B = ~(~A + ~B)

A ⋅ B

A B A ⋅ B

0 0

0 1

1 0

1 1

~(~A + ~B)

A B ~A ~B ~A + ~B ~(~A + ~B)

0 0

0 1

1 0

1 1

Do the truth tables match?

Example: What is the equivalent function after implementing De Morgan’s Law?

~(A ⋅ ~B) =

~A + B + C =


Logical Completeness

You can complete ANY truth table with only AND, OR, NOT.

In addition, you can complete any truth table with only NAND. You can also complete any truth table with only

NOR gates.

Draw a NOT gate using only NAND gates:

Draw an AND gate using only NAND gates:

Draw an OR gate using only NAND gates:

(hint: use DeMorgan’s Law)

Draw a NOR gate using only NAND gates:

(hint: use DeMorgan’s Law)


2-1 Multiplexer

Output selects one of the inputs determined by the ____________________ (_____) line.

Functionality

if (_______________):

out = _____

else:

out = _____

Note that the truth table contains all possible combinations of inputs.

How many inputs do we have? _____

Therefore, we have _____ lines in the truth table.

Draw the schematic here: Complete the truth table:

S A B Out =

0 0 0 0

0 0 1 0

0 1 0 0

Show the sum of products solution:

Show the product of sums solution:


Bitwise Operations

Apply a function to each bit in a binary word.

Example: bitwise operations on values 01001101 and 01001001

01001101 AND 01001001

0 1 0 0 1 1 0 1

• 0 1 0 0 1 0 0 1

01001101 OR 01001001

0 1 0 0 1 1 0 1

+ 0 1 0 0 1 0 0 1

01001101 XOR 01001001

0 1 0 0 1 1 0 1

⊕ 0 1 0 0 1 0 0 1

NOT 01001101

~ 0 1 0 0 1 1 0 1

0xAA AND 0xF0

AA: __ __ __ __ __ __ __ __

F0: __ __ __ __ __ __ __ __

•________________________

__ __ __ __ __ __ __ __

0xAA OR 0xF0:

AA: __ __ __ __ __ __ __ __

F0: __ __ __ __ __ __ __ __

+________________________

__ __ __ __ __ __ __ __

Reduction Operation

Example: perform the reduction operation on 01001101 and 01001001

AND 01001001

0 • 1 • 0 • 0 • 1 • 0 • 0 • 1 =

XOR 01001101

0 ⊕ 1 ⊕ 0 ⊕ 0 ⊕ 1 ⊕ 1 ⊕ 0 ⊕ 1 =

Bit Significance

MSB: M__________________ S__________________ B__________________

LSB: L__________________ S__________________ B__________________

Example: label the bit numbers, MSB, and LSB

0 1 0 0 1 0 0 1

bit

0xBA


Addition

Example: perform addition and label digits for sum, carry out, and carry in

Perform decimal addition

9 9 9 8

+ 5 0 2 1

Perform binary addition

1 1 0 0 1 1 0 1

+ 0 1 0 0 1 0 0 1

Half-Adder

2 inputs: A, B

2 outputs: ( ) and ( )


A B

Full Adder

3 inputs: A, B, ( )

2 outputs: ( ) and ( )


A B


Four-Bit Ripple Carry Adder

Draw the schematic for a 4-bit ripple carry adder:

Largest Number

Example

What is the largest number we can represent with 5 bits?

_____ _____ _____ _____ _____

Generalized Concept

What is the largest number we can represent with n bits?

Representing Negative Numbers

Example: convert 0xFA to decimal

NOTATION NOTES 0XFA IN DECIMAL

unsigned

signed

magnitude

one’s

complement

two’s

complement


excess

notation

NOTATION RANGE ADDITIVE INVERSE NOTES

unsigned

signed magnitude

one’s complement

two’s complement

excess notation

Overflow

Overflow occurs when you have a ____________________ from the __________ resulting in:

Examples

Assume you have a 4 bit register to store the value from unsigned integers 1010 + 1111

1 0 1 0 ← _____ in decimal

+ 1 1 1 1 ← _____ in decimal

___ ___ ___ ___ ___

Assume you have a 4 bit register to store the value from two’s complement integers 1010 + 1111

1 0 1 0 ← _____ in decimal

+ 1 1 1 1 ← _____ in decimal

___ ___ ___ ___ ___ ← _____ in decimal Is this overflow?


Sign Extension

NOTATION EXTEND 0xA4 TO 12 BITS

unsigned

signed magnitude

one’s complement

two’s complement

Logical Shift

Right: replace _____ with _____ Left: replace _____ with _____

Shift 0x5F by 3 bits to the right

Shift 0x5F by 3 bits to the left

Arithmetic Shift

Right: replace _____ with _____ Left: replace _____ with _____

Shift 0xA7 by 3 bits to the right

Shift 0xA7 by 3 bits to the right

Arithmetic shifts are used for ____________________ and ____________________

Rotate

Rotate 0xA7 by 3 bits to the right

Rotate 0xA7 by 3 bits to the right


Sequential Logic

S__________ R__________ (SR) Latch

An SR latch is a ____________________ device. SR latches are ____________________ sensitive.

This logic circuit has two versions: active _______________ and active _______________

Active __________


~S ~R Action

0 0

0 1

1 0

1 1

Draw the logic circuit here:

Complete the truth table:

~S ~R Q ~Q

0 0

0 1

1 0

1 1

Fill in the timing diagram below:

~S

~R

Q

~Q


Active __________

Draw the schematic here:

~S ~R Q ~Q

0 0

0 1

1 0

1 1


S

R

Q

~Q

D Flip Flop

Flip flops are ____________________ sensitive

Draw the schematic here:

CLK D Q ~Q

↑ 1 0

other X


CLK

D

Q

~Q


Memory Analogy

Memory

ADDRESS CONTENTS

0xFF

...

0x02

0x01

0x00

Address space: total number of

____________________ ____________________

If a memory address is 28 bits, there is an address

space of ____________________ locations

In MIPS, addresses are __________ bits

Addressability

Byte addressable: Each memory location holds __________ __________ of data

Word: the basic unit of data used by the ____________________ ____________________

In MIPS, words are __________ bits (__________ bytes)

Byte addressable

ADDRESS CONTENTS

0xFF

...

0x04

0x03

0x02

0x01

0x00

Word addressable

ADDRESS CONTENTS

0xFF

...

0x04

0x03

0x02

0x01

0x00


MIPS Address Space

Instructions

Data Movement

Load / Store Word

Loads __________ and stores it in a _______________

LW $t3 (0x1010)

SW $t3 (0x1014)

Load / Store Half Word

Loads __________

Uses ____________________ ____________________

LH $t5 (0x1012)

SH $t5 (0x1016)

Load / Store Half Word

Uses ____________________ ____________________

LB $t6 (0x1016)

SB $t6 (0x1010)

ADDRESS CONTENTS

0x1017

0x1016

0x1015

0x1014

0x1013 0xC0

0x1012 0xFF

0x1011 0xEE

0x1010 0xEE

Operate

LI $t3 0xFEED

ANDI $t5 $t3 0x0F00

SLL $t6 $t5 0x8

Control

SOME_LABEL:

… #stuff

BGT $t5 $t0 SOME_LABEL


Addressing Mode

Effective address: the memory address used

Immediate

Address is ____________________ in instruction.

Write an example instruction using immediate addressing.

Indirect

Address is contained in a ____________________.

Write an example instruction using indirect addressing.

Base + Offset

Address is ____________________ from the value stored in a ____________________ and an

________________________________________.

Write an example instruction using base + offset addressing.

Example

ADDI $t0 $zero 0x1010

LW $t1 ($t0)

SW $t1 4($t0)

LH $t5 (0x1016)

SW $t5 ($t0)

LB $t6 6($t0)

SB $t6 (0x1014)

ADDRESS CONTENTS

0x1017

0x1016

0x1015

0x1014

0x1013 0xC0

0x1012 0xFF

0x1011 0xEE

0x1010 0xEE


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Midterm Review - users.soe.ucsc.edurebecca/comp_arch/... · Midterm Review CMPE 012: Computer Systems and Assembly Language University of California, Santa Cruz Created by Rebecca