MEMS Foundry Services

ESS4810 LectureFall 2010

MetalMUMPs• Electroplated nickel micromachining

process

MetalMUMPs

• Electroplated nickel as the primary structural material and electrical interconnect layer

• Doped poly-silicon for resistors, additional mechanical structures, and/or cross-over electrical routing

• A trench layer in the silicon substrate for additional thermal and electrical isolation

• Gold overplate to coat the sidewalls of nickel structures with a low contact resistance material

MetalMUMPs

• The thicknesses were chosen to suit most users

Process Flow

• Isolation oxide (grown)• Oxide 1 (deposited PSG)

Process Flow

• Pattern Oxide 1 by wet etching

Process Flow

• Deposit Nitride 1• Deposit Poly

Process Flow

• Pattern Poly by reactive ion etching

Process Flow

• Deposit Nitride 2

Process Flow

• Pattern Nitride 1 and 2 by RIE• Poly is not etched

Process Flow

• Deposit and pattern Oxide 2• Deposit and pattern Anchor Metal

Process Flow

• Deposit Plating Base• Deposit and pattern thick photoresist

Process Flow

• Electroplate Nickel and Gold

Process Flow

• Remove thick photoresist

Process Flow• Deposit photoresist• Pattern Plating Base

Process Flow

• Deposit Gold

Process Flow

• Remove photoresist

Process Flow

• Remove Plating Base• Release the structure

Process Flow

• Bulk etching

Applications

• Based on a proven process flow, one that has been used to fabricate high volume commercial switch and relay products

• This process flow was originally developed for the fabrication of MEMS micro-relay devices based on a thermal actuator technology

Standard cost is per 1cm x 1cm die location with 15 chips delivered

MEMS Integration

ESS4810 LectureFall 2010

MEMS-CMOS Integration

• Improved device performance and reliability

• Reduced size and power consumption• Lower manufacturing cost• Reduced package complexity

Challenges

• Thermal budget• Materials incompatibilities• Surface topography of MEMS• Passivation of CMOS during MEMS

etching and release steps• Yield losses multiplied

MEMS-CMOS Integration

Thermal Budget

• Critical temperatures for Al metallization– Degradation at T > 400-450°C– Junction migration at T = 950°C– Junction spiking

• Critical process temperatures for MEMS

Modular Processes

• CMOS before MEMS– IC foundry can be used– Chip area may be minimized– Thermal budget is an issue

• MEMS before CMOS– No thermal budget issues– Microstructure topography is an issue– Electronics and MEMS cannot be easily

stacked– IC foundries are wary of pre-processed

wafers (materials constraints)

UCB Process (CMOS first)

• Refractory metallization (e.g. tungsten) makes high-temperature post-processing possible

• Double-poly and single-metal CMOS is protected with PSG• Low-stress nitride for protection from release etch• MEMS ground poly to CMOS gate poly for interconnection

SOI Process (CMOS first)

Sandia Embedded Process

Interleaved and Foundry Processes

• CMOS and MEMS mixed– More control over materials and processes– Optimize or compromise mechanical and

electrical components– Higher manufacturing cost

• Foundry processes– Lower cost, more reliable, and higher yield– Simple post processing step to release

MEMS structures– Cost of increased chip area– Mechanical properties of CMOS layers

compromised

Analog Devices BiMEMS Process

• ADXL50 accelerometer– Interleaved MEMS and 4 um BiMOS fabrication– MEMS-CMOS interconnect by diffused n+ runners– Relatively deep junctions allow for MEMS poly

stress anneal– Acceleration to volt transducer

Integration by Foundry CMOS

• Process– Laminated metal/insulator MEMS– Made using HP 0.8um, 3-metal CMOS process at

MOSIS foundry– Top metal layer used as mask for CHF3/O2 oxide etch– Final SF6 isotropic etch releases structures

• Features– Independent

electrostatic actuation possible due to multiple insulated metal layers

Front-side wet etched Back-side wet etched

Front-side dry etched with CMOS metal mask

Back-side electrochemical etch stop on n-well

Front-side dry etched with photoresist mask

Front-side silicon DRIE

Sacrificial oxide etch Sacrificial aluminum etch

TSMC 0.35um 2P4M CMOS MEMS• There are two poly-silicon layers and four

metal layers fabricated in this process

TSMC 0.35um 2P4M CMOS MEMS

• Two micromachining processes based on a user-defined RLS mask are performed

• 1 - the silicon dioxide films under the RLS mask are removed by anisotropic etching

• 2 - silicon substrate is removed by isotropic etching via the open-windows resulted from the first step

• Another user-defined PAD mask is used to open the PASS layer around the MEMS device region

• An additional 0.7um oxide is deposited before oxide and silicon etching to improve the selectivity between photoresist and oxide layers

• After the post-process, this additional oxide layer will be thoroughly removed

TSMC 0.35um 2P4M CMOS MEMS

Summary• CMOS first

– State-of-the-art CMOS foundries can be used– Thermal budget of metallization to be

accounted for• MEMS first

– No thermal budget to worry about– Possible materials incompatibilites (high

dopant structural layers, piezoelectrics, …)– Topography to overcome

• Interleaved– Potentially greater control over process steps– First commercially proven integrated process– Possibly compromises both CMOS and MEMS

MEMS Assembly

• Extend MEMS beyond the confines of micro-machining

• Serial micro-assembly• Parallel micro-assembly• Furnish reliable mechanical bonds

and electrical interconnection between the component and the target substrate or subassembly

Micro-Assembly

• The limitations of lithography and etching as the universal platform for MEMS fabrication

• Monolithic integration of electronics and micromechanics inevitably compromise both subsystems

• Even modularized processes suffer from yield losses due to very high mask counts and wafer size differences

CMOS electronics

Photonic devices

Microstructures

Serial Micro-Assembly

• Requiring an infrastructure of micro-tools and micro-parts designed to interface with each other and the macroscopic world

Serial Micro-Assembly

• More difficult to make the desired shapes with the necessary tolerances given the technology of micro-machining available today

• Gravity is usually negligible• Surface adhesion and electro-static

forces dominate• Tweezers with integrated actuators

and force sensors

Adhesion Problems• Adhesive forces between gripper and object

can be significant compared to gravitational forces

• Arise primarily from surface tension, van derWaals, and electrostatic attractions– Electrostatic forces due to surface charges

or ions in the ambient must be minimized– Adhesion of the part to the unclamped

gripper surfaces should be less than the adhesion of the part to the substrate

– The target spot on the work-piece must have a surface coating that provides sufficiently strong adhesion to exceed that between the part and the unclamped gripper

Assembly of Hinged Structures

• Manual assembly• Fluidic agitation• On-chip MEMS actuation• Parallel external methods

On-Chip MEMS Actuation

• Using actuators, such as comb drives, vibromotors, and scratch drives, to push structures into assembled position

Parallel External Methods

• Fluidic agitation• Ultrasonic forces• Magnetic deflection• Polymer shrinkage• Surface tension

Deterministic Parallel Assembly

• Direct wafer-to-wafer transfer• The placement of structures is pre-

determined by the layout on donor wafer• The challenge lies in bonding structures

to the target• Two key features

– Compatibility– Throughput

Stochastic Parallel Assembly• Mediated by thermal motion and inter-

facial forces• Evolving toward a state of minimal

potential energy

Capillary Forces

• Separate surfaces into hydrophobic and hydrophilic regions

• Match hydrophobic binding sites• Coat substrate sites selectively with

hydrophobic liquid

Self Assembly

• Oxidize and glass surfaces: hydrophilic• Self-assemble monolayer on gold:

hydrophobic

Self Assembly

• Patterned substrate is passed through hydrocarbon adhesive-water interface

Self Assembly

Thick PR Process and Micro Plating Lab

ESS4810 LectureFall 2010

Lab 3: Evaporation andBulk micromachining

Lab 2-2: 1. Break wafer into A, B2. BOE wet etching B, RIE

dry etch A3. PR strip,wafer cleaning

Part A Part B

Si

Dry etch wet etchPart A Part B

Si

Dry etch wet etch

Si

Dry etch wet etch

Lab 3: 1. E-beam evaporate Cr/Ni

0.05/0.15μm on A2. TMAH bulk etch BSi

Cr/Ni

Si

Cr/Ni

Si

AZ4620Ni

SiSiSi

AZ4620Ni

SiSiSi

Process Flow

Lab 3: 1. E-beam evaporate Cr/Ni

0.05/0.15μm on A2. TMAH bulk etch B

Lab 4-1: • Lithography patterning Ni

by wet etching (mask #3)

Lab 4-2• AZ4620 lithography• Plating

Si

Cr/Ni

Si

Cr/Ni