Upload
arun-gopinath-g
View
230
Download
0
Embed Size (px)
Citation preview
7/30/2019 Memory Unit Design 01
1/25
Abdu Rahiman VLecturer in ECE
Govt. College of Engineering,
Kannur, Kerala, India
Abdu Rahiman V. Govt. College of Engg. Kannur.
7/30/2019 Memory Unit Design 01
2/25
Memory Store instruction and data
Memory requirements
Should be as fast as processor Large size
Low cost
Essential in any processing unit
Abdu Rahiman V. Govt. College of Engg. Kannur.
7/30/2019 Memory Unit Design 01
3/25
Processor and memory interface
Abdu Rahiman V. Govt. College of Engg. Kannur.
Memory
Upto2k addressable
locations
Word length n bits
MAR
MDR
Control bus
n bit Data bus
kBit address bus
7/30/2019 Memory Unit Design 01
4/25
Memory Units used with memory
Byte, KB, MB, GB, TB
Memory access time- time between giving read signal andreceiving MFC
Memory cycle time minimum time required between twosuccessive read signals
Random access memory any location can be read or written ina fixed time
Serial access memory memory access time depends on the
position of data Types of memory
Main memory or primary memory Secondary memory Cache memory
Abdu Rahiman V. Govt. College of Engg. Kannur.
7/30/2019 Memory Unit Design 01
5/25
Organization of memory cells in a
memory unit - Example
Abdu Rahiman V. Govt. College of Engg. Kannur.
Sense/Write
Sense/Write
Sense/Write
b7 b7 b1 b1 b0 b0
. . .
. . .
. . .
FF
W0
W1
W15
A0
A1
A2
A3Addressdecoder
RD/WR
RD/WR RD/WR
b0b7 b1
7/30/2019 Memory Unit Design 01
6/25
Bipolar Memory Cell T1 OFF & T2 ON Logic 1 T1 ON & T2 OFF Logic 0 Read operation
Make word line zero volt A voltage is applied on bit
lines Diode near the transistor in
ON state will draw a current
Write Operation
Set voltages on the bits linesand make word line low Respective transistor will
turn ON and the other willbecome OFF
Abdu Rahiman V. Govt. College of Engg. Kannur.
Vcc
Bit Line Bit Line
Word
Line
T1 T2
D1
R1
D2
R2
7/30/2019 Memory Unit Design 01
7/25
CMOS Memory Cell T1 OFF & T2 ON Logic 1
T1 ON & T2 OFF Logic 0
Read operation
Make word line high
T5 & T6 ON, voltages atthe points are availableon bit lines
Write Operation Set voltages on the bit
lines and make word linehigh
Abdu Rahiman V. Govt. College of Engg. Kannur.
Vcc
Ground
Bit Line Bit Line
Word
Line
T1 T2
T4
T6T5
T3
7/30/2019 Memory Unit Design 01
8/25
Dynamic Memory Minimum number of
transistors required
High density memoryfabrication is possible
Volatile
Refresh circuitry is
required Low cost per bit
Abdu Rahiman V. Govt. College of Engg. Kannur.
Bit Line
Word
Line
7/30/2019 Memory Unit Design 01
9/25
Addressing multiple module
memory system
Abdu Rahiman V. Govt. College of Engg. Kannur.
ABR DBR ABR DBR ABR DBR
Module Address in Module
. . . . . .
DataBus
ABR- Address Buffer RegisterDBR- Data Buffer Register
Consecutive memory locations
are stored in same module
7/30/2019 Memory Unit Design 01
10/25
Addressing multiple module
memory system
Abdu Rahiman V. Govt. College of Engg. Kannur.
ABR DBR ABR DBR ABR DBR
ModuleAddress in Module
. . . . . .
DataBus
ABR- Address Buffer RegisterDBR- Data Buffer Register
Consecutive memory locations are stored in same consecutivemodule
Memory interleaving
7/30/2019 Memory Unit Design 01
11/25
Memory interleaving
It is possible to access multiple words in one cycle
Reduces the total time to read the required data
Abdu Rahiman V. Govt. College of Engg. Kannur.
7/30/2019 Memory Unit Design 01
12/25
Cache Memory
Abdu Rahiman V. Govt. College of Engg. Kannur.
ProcessorCache
memoryMain
MemorySecondaryMemory
Small sizeHigh speedHigh cost
Medium sizeMedium speedMedium cost
Large sizelow speedLow cost
7/30/2019 Memory Unit Design 01
13/25
Cache Memory Locality of reference
Spatial:-the instructions stored in nearby locations arelikely to be executed repeatedly
Temporal:- the instructions executed recently are
likely to be executed repeatedly
Abdu Rahiman V. Govt. College of Engg. Kannur.
7/30/2019 Memory Unit Design 01
14/25
Cache Memory High speed memory to store small portion of main
memory
Cache and main memories are divide in to smallblocks
Block containing the data referenced is brought in tothe cache memory
Abdu Rahiman V. Govt. College of Engg. Kannur.
7/30/2019 Memory Unit Design 01
15/25
Abdu Rahiman V. Govt. College of Engg. Kannur.
Cache memory
Main memory
Block 0
Block 1
.
.
Block m-1Block m
Block m+1
.
.
Block 2m-1
Block 2m
Block 2m+1
.
.
Block pm-1
Block 0
Block 1
.
.
Block m-1
7/30/2019 Memory Unit Design 01
16/25
Cache MemoryAny modification made in cache has to be made in
main memory also
Write through : write to main memory along with thewrite to cache
Write back : write to cache, if it is modified, beforediscarding the cache content
Dirty/modified bit: set to 1 if the content of cache ismodified
Valid bit:- to indicate cache contain valid data
Abdu Rahiman V. Govt. College of Engg. Kannur.
7/30/2019 Memory Unit Design 01
17/25
Cache memory mapping functions Direct Mapping
Searching is easy
Tag field used to identifythe block
Abdu Rahiman V. Govt. College of Engg. Kannur.
Block 0
Block 1
.
.
Block m-1
Block m
Block m+1
.
.
Block 2m-1
Block 2m
Block 2m+1
.
.
Block pm-1
Block 0
Block 1
.
.
Block m-1
TagCacheblock
Word Address
Main Memory Address
7/30/2019 Memory Unit Design 01
18/25
Direct mapping - Example Block size 16 bytes
Total main memory 16
KB
Number of blocks in
main memory 1024
Cache size 1 KB, 64
blocks
Abdu Rahiman V. Govt. College of Engg. Kannur.
Block 0
Block 1
.
.
Block 63
Block 64
Block 65
.
.
Block 127
Block 128
Block 129
.
.
Block 1023
Block 0
Block 1
.
.
Block 63
Tag4 bits
Cacheblock6 bits
Word Address4 bits
Main Memory Address
7/30/2019 Memory Unit Design 01
19/25
Associative mappingAny block can be loaded
to any available block incache
Abdu Rahiman V. Govt. College of Engg. Kannur.
Block 0
Block 1
.
.
Block m-1
Block m
Block m+1
.
.
Block 2m-1
Block 2m
Block 2m+1
.
.
Block pm-1
Block 0
Block 1
.
.
Block m-1
Tag Word Address
Main Memory Address
7/30/2019 Memory Unit Design 01
20/25
Associative mapping - Example Block size 16 bytes
Total main memory 16
KB
Number of blocks in
main memory 1024
Cache size 1 KB, 64
blocks
Abdu Rahiman V. Govt. College of Engg. Kannur.
Block 0
Block 1
.
.
Block 63
Block 64
Block 65
.
.
Block 127
Block 128
Block 129
.
.
Block 1023
Block 0
Block 1
.
.
Block 63
Tag10 bits
Word Address4 bits
Main Memory Address
7/30/2019 Memory Unit Design 01
21/25
Set Associative mapping Blocks can be moved
to free blocks in theset
Abdu Rahiman V. Govt. College of Engg. Kannur.
Tag Set Number Word Address
Main Memory Address
Block 0
Block 1
.
.
Block m-1
Block m
Block m+1
.
.
Block 2m-1
Block 2m
Block 2m+1
.
.
Block pm-1
Block 0
Block 1
.
.
Block m-2
Block m-1
Block 2
Block 3
Set 1
Set 2
Set p
7/30/2019 Memory Unit Design 01
22/25
Set Associative mapping - Example
Block size 16 bytes
Total main memory 16
KB
Number of blocks in
main memory 1024
Cache size 1 KB, 64
blocks and 32 sets Two way set associative
mapping
Abdu Rahiman V. Govt. College of Engg. Kannur.
Tag5 bits
Set No.5 bits
Word Address4 bits
Main Memory Address
Block 0
Block 1
.
.
Block 63
Block 64
Block 65
.
.
Block 127
Block 128
Block 129
.
.
Block 1023
Block 0
Block 1
.
.
Block m-2
Block 63
Block 2
Block 3
Set 0
Set 2
Set 31
7/30/2019 Memory Unit Design 01
23/25
Cache memory Cache hit - accessed data is present in cache
Cache miss accessed data is not present in cache
Hit rate Number of hits / total access attemps In case of cache miss, new data block has to be moved
to cache memory
Miss penaltyThe delay to fetch the block after cache
miss
Abdu Rahiman V. Govt. College of Engg. Kannur.
7/30/2019 Memory Unit Design 01
24/25
Cache Replacement Schemes Least Recently Used :- Remove the LRU block and
replace with the new one
Oldest block:- Remove the oldest block and copy thenew one
Performance of this method is very poor
Random replacement:- Randomly select the block to
be replace. This method has relatively good performance
Abdu Rahiman V. Govt. College of Engg. Kannur.
7/30/2019 Memory Unit Design 01
25/25
Thank You
Abdu Rahiman V Govt College of Engg Kannur