MEMORY ORGANISATION:

MEMORY ORGANIZATION Memory organization is two-fold. First we discuss the hardware (physical) organization, then the internal architecture. The type of computer and its size do not reflect the type of memories that the computer uses. Some computers have a mixture of memory types. For example, they may use some type of magnetic memory (core or film) and also a semiconductor memory (static or dynamic). They also have a read-only memory which is usually a part of the CPU. Memory in a computer can vary from one or more modules  to one or more pcb’s, depending  on  the computer type. The larger mainframe computers use the modular arrangement, multiple modules (four or more),   to   make   up   their   memories.   Whereas, minicomputers and microcomputers use chassis or assemblies,  cages  or  racks,  and  motherboard  or backplane arrangements.   Minis   and   micros   use multiple components on one pcb or groups of pcb’s to form  the  memoryThere are several ways to organise memories with respect to the way they are connected to the cache:one-word-wide memory organisationwide memory organisationinterleaved memory organisationindependent memory organization

One-Word-WideThe memory is one word wide and connected via a one word wide bus to the cache.WideThe memory is more than one word wide (usually four words wide) and connected by an equally wide bus to the low level cache (which is also wide). From the cache multiple busses of one word wide go to a MUX which selects the correct bus to connect to the high level cache.InterleavedThere are several memory banks which are one word wide, and one one word wide bus. There is some logic in the memory that selects the correct bank to use when the memory gets accessed by the cache.Memory interleaving is a way to distribute individual addresses over memory modules. Its aim is to keep the most of modules busy as computations proceed. With memory interleaving, the low-order k bits of the memory address select a module, and the high-order m bits name a location within that module. Hence, consecutive addresses are located in successive modules. A request to access consecutive memory locations can keep several modules busy at the same time.IndependentThere are several banks, which can all be accessed simultaneously by several buses.Memory geometryIn the design of modern personal computers, memory geometry describes the internal structure of random-access memory. Memory geometry is of concern to consumers upgrading their computers, since older memory controllers may not be compatible with later products. Memory geometry terminology can be confusing because of the number of overlapping terms.

Physical featuresMemory geometry describes the logical configuration of a RAM module, but consumers will always find it easiest to grasp the physical configuration. Much of the confusion surrounding memory geometry occurs when the physical configuration obfuscates the logical configuration. The first defining feature of RAM is form factor. RAM modules can be in compact SO-DIMM form for space constrained applications like laptops, printers, embedded computers, and small form factor computers, and in DIMM format, which is used in most desktops.The other physical characteristic determine with by physical examination are the number of memory chips, and whether both sides of the memory "stick" are populated. If 4 is a factor of the number of memory devices or chips (or more generally, a power of two), then the module does not feature ECC, if 9 is a factor of the number of memory chips (or one more than a power of two), then the module does. RAM modules are 'keyed' by indentations on the sides, and along the bottom of the module. This determines the technology, and classification of the modules, for instance whether it is DDR2, or DDR3, and whether it is suitable for desktops, or for servers. It is important to make sure that the keying of the module matches the key of the slot it is intended to occupy. Additional, non-memory chips on the module are an indication that it could be designed for high capacity memory systems for servers, and that the module may be incompatible with desktop systems.As the next section of this article will cover the logical architecture, which covers the logical structure spanning every populated slot in a system, the physical features of the slots themselves becomes important. By consulting the documentation of your motherboard, or reading the labels on the board itself, you can determine the underlying logical structure of the slots. When there is more than one slot, they are numbered, and when there is more than one channel, the different slots are separated in that way as well - usually color-coded.[edit] Logical featuresIn the 90s specialized computers were released where two computers that each had their own memory controller could be networked at such a low level that the software run could use the memory, or CPU of either computer as if they were one unit. With AMD's release of the Opteron, and Intel's corresponding systems systems that share more than one memory controller in a single system have become common in applications that require the power of more than one common desktop. For these systems schemes like Non-Unified Memory Architecture are used.Channels are the highest level structure at the local memory controller level. Modern computers can have two, three or even more channels. It is usually important that, for each module in any one channel, there is a logically identical module in the same location on each of the other populated channels.Module capacity is the aggregate space in a module measured in byte, or - more generally - in words. Module capacity is equal to the product of the rank density and the number of ranks, and where the rank density is the product of rank depth, and rank width[1]. The standard format for expressing this specification is (rank density) Mbit x (rank width)x(number of ranks).Banks are one of the chief sources of physical/logical confusion. Banks are a logical distinction that corresponds to CSRows in low level addressing, for more details on the

addressing of RAM in this POV, see dynamic random access memory. As memory density has increased, the numbers of ranks in each chip has also increased. As an example of a simple configuration, say there is one module with 8 chips, or devices, on each side, and one rank in each of the 16 chips, and each bank was 8 bits wide, that module would have one bank for each side. One bank on one side, and one bank on the back. Today you could have a module composed of Micron MT47H128M16 chips with the organization 16Mb x 16 x 8 with a bank width of 16. With a module which has of 8 of those on each side, there would be 2 "x16" "banks" on each side. Memory controllers such as the Intel 945 Chipset list the configurations they support: "Supports 256-Mb, 512-Mb, and 1-Gb DDR2 technologies for x8 and x16 devices." "Supports four banks for all DDR2 devices up to 512-Mbit density. Supports eight banks for 1-Gbit DDR2 devices." As an example, take an i945 memory controller with 4 Kingston KHX6400D2/1Gs.Kingston describes each module as having a geometry of 128Mx64, meaning that each one has 64 bits 128 million deep, equaling 8.192 billion bits, or 1.024 Gigabytes. Kingston describes each "device", or chip as having a geometry of 64Mx8, so each module has four banks. So from the MCH POV when there are 4 1GB modules, it sees 2 channels, each with 8 banks.Hierarchy of organizationMemory chipThe lowest form of organization covered by memory geometry, sometimes called "memory device". These are the component ICs that make up each module, or module of RAM. The most important measurement of a chip is its density, measured in bits. Because memory bus width is usually larger than the number of chips, most chips are designed to have width, meaning that they are divided into equal parts internally, and when one address "depth" is called up, instead of returning just one value, more than one value is returned. In addition to the depth, a second addressing dimension has been added at the chip level, banks. Banks allow one bank to be available, while another bank is unavailable because it is refreshing. An example of chip notation is 64Mb (depth) X 8 (width) X 8 Banks.[edit] Memory moduleSome measurements of modules are size, width, speed, and latency. A memory module consists of a multiple of the memory chips to equal the desired module width. So a 32 bit SIMM module could be composed of four 8-bit wide (x8) chips. As noted in the memory channel part, one physical module can be made up of one or more logical ranks. If that 32 bit simm were composed of eight 8-bit chips the simm would have two ranks. An example of Module notation is 128Mb x 64-bit.[edit] Memory channelA memory channel is made up of ranks. Physically a memory channel with just one memory module might present itself as having one or more logical ranks.[edit] Controller organizationThis is the highest level. In a typical computer there will only be a single memory controller with only one or two channels. The logical features section described NUMA configurations, which can take the form of a network of memory controllers. For example, each socket of a two socket AMD K8 can have a two channel memory controller, giving the system a total of four memory channels.

Random-access memoryRandom-access memory (RAM) is a form of computer data storage. Today, it takes the form of integrated circuits that allow stored data to be accessed in any order (that is, at random). "Random" refers to the idea that any piece of data can be returned in a constant time, regardless of its physical location and whether it is related to the previous piece of data.[1]The word "RAM" is often associated with volatile types of memory (such as DRAM memory modules), where the information is lost after the power is switched off. Many other types of memory are RAM as well, including most types of ROM and a type of flash memory called NOR-Flash.Types of RAMModern types of writable RAM generally store a bit of data in either the state of a flip-flop, as in SRAM (static RAM), or as a charge in a capacitor (or transistor gate), as in DRAM (dynamic RAM), EPROM, EEPROM and Flash. Some types have circuitry to detect and/or correct random faults called memory errors in the stored data, using parity bits or error correction codes. RAM of the read-only type, ROM, instead uses a metal mask to permanently enable/disable selected transistors, instead of storing a charge in them. Of special consideration is SIMM and DIMM memory modules.SRAM and DRAM are volatile. Other forms of computer storage, such as disks and magnetic tapes, have been used as persistent storage. Many newer products instead rely on flash memory to maintain data when not in use, such as PDAs or small music players. Certain personal computers, such as many rugged computers and netbooks, have also replaced magnetic disks with flash drives. With flash memory, only the NOR type is capable of true random access, allowing direct code execution, and is therefore often used instead of ROM; the lower cost NAND type is commonly used for bulk storage in memory cards and solid-state drives. A memory chip is an integrated circuit (IC) made of millions of transistors and capacitors. In the most common form of computer memory, dynamic random access memory (DRAM), a transistor and a capacitor are paired to create a memory cell, which represents a single bit of data. The capacitor holds the bit of information — a 0 or a 1 . The transistor acts as a switch that lets the control circuitry on the memory chip read the capacitor or change its state.Memory hierarchyMany computer systems have a memory hierarchy consisting of CPU registers, on-die SRAM caches, external caches, DRAM, paging systems, and virtual memory or swap space on a hard drive. This entire pool of memory may be referred to as "RAM" by many developers, even though the various subsystems can have very different access times, violating the original concept behind the random access term in RAM. Even within a hierarchy level such as DRAM, the specific row, column, bank, rank, channel, or interleave organization of the components make the access time variable, although not to the extent that rotating storage media or a tape is variable. The overall goal of using a memory hierarchy is to obtain the higher possible average access performance while minimizing the total cost of the entire memory system (generally, the memory hierarchy follows the access time with the fast CPU registers at the top and the slow hard drive at the bottom).In many modern personal computers, the RAM comes in an easily upgraded form of modules called memory modules or DRAM modules about the size of a few sticks of

chewing gum. These can quickly be replaced should they become damaged or when changing needs demand more storage capacity. As suggested above, smaller amounts of RAM (mostly SRAM) are also integrated in the CPU and other ICs on the motherboard, as well as in hard-drives, CD-ROMs, and several other parts of the computer system.By convention, bus and network data rates are denoted either in bit/s (bits per second) or byte/s (bytes per second). In general, parallel interfaces are quoted in byte/s and serial in bit/s. The more commonly used is shown below in bold type.On devices like modems, bytes may be more than 8 bits long because they may be individually padded out with additional start and stop bits; the figures below will reflect this. Where channels use line codes (such as Ethernet, Serial ATA and PCI Express), quoted rates are for the decoded signal.The figures below are simplex data rates, which may conflict with the duplex rates vendors sometimes use in promotional materials. Where two values are listed, the first value is the downstream rate and the second value is the upstream rate.All quoted figures are in metric decimal units, where:1 Byte = 8 bit1 kbit/s = 1,024 bit/s1 Mbit/s = 1,048,576 bit/s1 Gbit/s = 1,073,741,824 bit/s1 kB/s = 1,024 Byte/s1 MB/s = 1,048,576 Byte/s1 GB/s = 1,073,741,824 Byte/s1 TB/s = 1,099,511,627,776 Byte/sThese decimal prefixes have been established in data communications for long time, also before 1998 when IEC and other organizations tried to make it standard for all computing applications, and introduced new binary prefixes.

MEMORY SYSTEM Memory in a computer system is required for storage and subsequent retrieval of the instructions and data. A computer system uses variety of devices for storing these instructions and data which are required for its operations. Normally we classify the information to be stored on computer in two basic categories: Data and the Instructions. "The storage devices along with the algorithm or information on how to control and manage these storage devices constitute the memory system of a computer." A memory system is a very simple system yet it exhibits a wide range of technology and types. The basic objective of a computer system is to increase the speed of computation. Likewise the basic objective of a memory system is to provide fast, uninterrupted access by the processor to the memory such that the processor can operate at the speed it is expected to work. But does this kind of technology where there is no speed gap between processor and memory speed exist? The answer is yes they do, but unfortunately as the access time (time taken by CPU to access a location in memory) becomes less and less the cost per bit of memory becomes increasingly higher. In addition, normally these memories require power supply till the information need to be stored. Both these things are not very

convenient, but on the other hand the memories with smaller cost have very high access time which will result in slower operation of the CPU. Thus, the cost vs access time anomaly has lead to a hierarchy of memory where we supplement fast memories with larger, cheaper, slower memories. These memory units may have very different physical and operational\ characteristics, therefore, making the memory system very diverse in type, cost,\ organisation, technology and performance. This memory hierarchy will work only if the frequency of access to the slower memories are significantly less than the faster memories. Internal Processor Memories: These consist of the small set of high speed registers which are internal to a processor and are used as temporary locations where actual processing is done. This will be covered in greater details in Block 2.

b. Primary Memory or Main Memory: It is a large memory which is fast but not as fast as internal processor memory. This memory is accessed directly by the processor. It is mainly based on integrated circuits.Secondary Memory/Auxiliary Memory/Backing Store: Auxiliary memory in fact is much larger in size than main memory but is slower than main memory. It normally stores system programs (programs which are used by system to perform various operational functions), other instructions, programs and data files. Secondary memory can also he used as an overflow memory in case the main memory capacity has been exceeded. (How? The answer is not supplied in the block. You need to refer to further readings to get this answer). Secondary memories cannot be accessed directly by a processor. First the information of these memories is transferred to the main memory and then the information can be accessed as the information of main memory. There is another kind of memory which is increasingly being used in modern computers, this is called Cache memory. It is logically positioned between the internal memory (registers) and main memory. It stores or catches some of the content of the main memory which is currently in use of the processor. We will discuss about this memory in greater details in a subsequent section of this unit. Before discussing more about these memories let us first discuss the technological terms commonly used in defining and accessing the memory.

2. CHARACTERISTICS TERMS FOR VARIOUS MEMORY DEVICES

The following terms are most commonly used for identifying comparative behaviour of various memory devices and technologies. Storage Capacity: It is a representative of the size of the memory. The capacity of internal memory and main memory can be expressed in terms of number of words or bytes. The storage capacity of external memory is normally measured in terms of bytes. Unit of transfer: Unit of transfer is defined as the number of bits read in or out of the memory in a single read or write operation, For main memory and internal memory, the normal unit of transfer of information is equal to the word length of a processor. In fact it depends on number of data lines in and out of the memory module. (Why?) In general, these lines are kept equal to the word size of the processor. What is a word? You have already learnt about this term in Unit 1 of this block. The unit of transfer of external

memory is normally quite large (Why? You will find the answer to this question later in this unit) and is referred to as block of data. Access Modes: Once we have defined the unit of transfer next important characteristics is the access mode in which the information is accessed from the memory. A memory is considered to consist of various memory locations. The information from memory devices can be accessed in the following ways

Random Access Memory (RAM): It is the mode in which any memory location can be accessed in any order in the same amount of time. Ferrite and Semiconductor memories which generally constitute main memory are of this nature. The storage locations can he accessed independently and there exist separate access mechanism for each location. Sequential access: On the other hand we have memories which can be accessed in a pre-defined sequences for example, the songs stored on a cassette can be accessed only one by one. The example of sequential access memory is Magnetic Tape. Here the access mechanism need to be shared among different locations. Thus, either the location or the read/write head or both should be moved to access the desired location. Direct Access: In certain cases the information is neither accessed randomly nor in sequence but something in between. In these kind of access, a separate read/write head exist for a track and on a track the information can be accessed serially. This semi-random mode of operation exist in magnetic disks.

Access Time: The access time is the time required between the request made for a read or write operation till the time the data is made available or written at the requested location. Normally it is measured for read operation. The access time depends on the physical characteristics and access mode used for that device. Permanence or Storage: Is it Possible to lose information by the memories over a period of time? If yes then what can be the reasons of the loss of information and what should bedone to avoid it? There arc several reasons for information destruction, these are destructive readout, dynamic storage, volatility and hardware failure. If for a particular memory the reading process destroys the stored information. we call it Destructive readout. In such memories the information has to be written back on the same location from which it had been read after each read operation. The reading process where the data is not destroyed on reading are referred to as Non-destructive readout. There can be some memories where the stored 1 looses its strength to become 0 over a period of time. These kind of memories require refreshing. The memories which require refreshing are termed as dynamic memories. In contrast, the memories which do not require refreshing are called static memories. Another factor which can destroy the contents is die presence and absence of electricity. The memories which loses their content on failure of power am armed as volatile memories, those which do not are called non-volatile. Magnetic memories are non-volatile and semiconductor main memories am volatile in nature. Cycle Time: It is defined as the minimum time elapsed between two consecutive read

requests. Is it equal to access time? Yes, for most of the memories except the ones in which destructive readout is encountered. Cycle time for such memories is the access time (time elapsed when a read request is made available) plus writing time as after the data has been made available the information has to be written back in the same memory location as the previous value has been destroyed by reading. But for most of the commonly used semiconductor memories cycle time is equal to the access time

DELAY BUFFER:

This section describes PJMEDIA's implementation of delay buffer. Delay buffer works quite similarly like a fixed jitter buffer, that is it will delay the frame retrieval by some interval so that caller will get continuous frame from the buffer. This can be useful when the operations are not evenly interleaved, for example when caller performs burst of put() operations and then followed by burst of operations. With using this delay buffer, the buffer will put the burst frames into a buffer so that get() operations will always get a frame from the buffer (assuming that the number of get() and put() are matched).The buffer is adaptive, that is it continuously learns the optimal delay to be applied to the audio flow at run-time. Once the optimal delay has been learned, the delay buffer will apply this delay to the audio flow, expanding or shrinking the audio samples as necessary when the actual audio samples in the buffer are too low or too high.

EXISTING TECHNIQUE:

INPUT BUFFER:The Input buffer is also commonly known as the input area or input block. When referring to computer memory, the input buffer is a location that holds all incoming information before it continues to the CPU for processing. Input buffer can be also used to describe various other hardware or software buffers used to store information before it is processed.Some scanners (such as those which support “include” files) require reading from several input streams. As flex scanners do a large amount of buffering, one cannot control where the next input will be read from by simply writing a YY_INPUT() which is sensitive to the scanning context. YY_INPUT() is only called when the scanner reaches the end of its buffer, which may be a long time after scanning a statement such as an include statement which requires switching the input source.

2:1

FIG1: INPUT BUFFER

MEMORY BLOCK: (RAM) Random-access memory (RAM) is a form of computer data storage. Today, it takes the form of integrated circuits that allow stored data to be accessed in any order (that is, at random). "Random" refers to the idea that any piece of data can be returned in a constant time, regardless of its physical location and whether it is related to the previous piece of data. The word "RAM" is often associated with volatile types of memory (such as DRAM memory modules), where the information is lost after the power is switched off. Many other types of memory are RAM as well, including most types of ROM and a type of flash memory called NOR-Flash.

Scan design has been the backbone of design for testability (DFT) in industry for about three decades because scan-based design can successfully obtain controllability and observability for flip-flops. Serial Scan design has dominated the test architecture because it is convenient to build. However, the serial scan design causes unnecessary switching activity during testing which induce unnecessarily enormous power dissipation. The test time also increases dramatically with the continuously increasing number of flip-flops in large sequential circuits even using multiple scan chain architecture. An alternate to serial scan architecture is Random Access Scan (RAS). In RAS, flip-flops work as addressable memory elements in the test mode which is a similar fashion as random access memory (RAM). This approach reduces the time of setting and observing the flip-flop states but requires a large overhead both in gates and test pins. Despite of these drawbacks, the RAS was paid attention by many researchers in these years. This paper takes a view of recently published papers on RAS and rejuvenates the random access scan as a DFT method that simultaneously address three limitations of the traditional serial scan namely, test data volume, test application time, and test power.2 Random Access Scan Fig 1. shows the basic architecture of the RAS. A Decoder is used to address every FF. The RAS allows reading or writing of any flip-flop using address bits where “n” is the number of scanned flip-flops when the address is applied, the address decoder produces a scan enable signal to the corresponding flip-flop needed to be placed with a data from the scan-in. In this technique, the scan function is implemented as a random-access memory. Hence at every given time only one FF is accessed while other FFs retain their state. The architectures described in most literatures mainly consists of a scan-in signal that is broadcasted to every FF, a test control signal that is broadcasted to all FFs, and a unique decoder signal from the decoder to every FF. A more feasible decoder has been designed. The grid architecture shown in Fig2 is one efficient way to layout the decoders. With a minimum of two layers of metal routing, the row wires can be accommodated within the channel in between the cell rows and the column wires can be routed over the cell in the next metal layer. Hence there will

be an increase of one track per channel (assuming m channels) and n tracks that are routed on the next metal layer.

Figure 1. Design of RAS as described in

Figure 2. Decoder design

In those two decoder structures, suppose there are Nff flip-flops in the circuit. In Figure 1, there will be Nff - address wires to those N flip-flops. Compared to Figure 1,

there are only Nff address wires to N-ffs in Figure 2. Although this structure need both row decoder and column decoder when only one decoder is used in Figure 1, the hardware overhead reduced greatly using structure 2.How Random Access Memory (RAM) Works

Common RAM Memory Types:SRAM - Static random access memory uses multiple transistors, typically four to six, for each memory cell but doesn't have a capacitor in each cell. It is used primarily for cache. DRAM - Dynamic random access memory has memory cells with a paired transistor and capacitor requiring constant refreshing. FPM DRAM - Fast page mode dynamic random access memory was the original form of DRAM. It waits through the entire process of locating a bit of data by column and row and then reading the bit before it starts on the next bit. Maximum transfer rate to L2 cache is approximately 176 megabytes per second.

EDO DRAM - Extended data-out dynamic random access memory does not wait for all of the processing of the first bit before continuing to the next one. As soon as the address of the first bit is located, EDO DRAM begins looking for the next bit. It is about five percent faster than FPM. Maximum transfer rate to L2 cache is approximately 264 megabytes per second. SDRAM - Synchronous dynamic random access memory takes advantage of the burst mode concept to greatly improve performance. It does this by staying on the row containing the requested bit and moving rapidly through the columns, reading each bit as it goes. The idea is that most of the time the data needed by the CPU will be in sequence. SDRAM is about five percent faster than EDO RAM and is the most common form in desktops today. Maximum transfer rate to L2 cache is approximately 528 megabytes per second. RDRAM - Rambus dynamic random access memory is a radical departure from the previous DRAM architecture. Designed by Rambus, RDRAM uses a Rambus in-line memory module (RIMM), which is similar in size and pin configuration to a standard DIMM. What makes RDRAM so different is its use of a special high-speed data bus called the Rambus channel. RDRAM memory chips work in parallel to achieve a data rate of 800 MHz. Credit Card Memory - Proprietary self-contained DRAM memory module that plugs into a special slot for use in notebook computers. PCMCIA Memory Card - Another self-contained DRAM module for notebooks. Cards of this type are not proprietary and should work with any notebook computer whose system bus matches the memory card's configuration. FlashRAM - A generic term for the small amount of memory used by devices like TVs, VCRs and car radios to maintain custom information. Even when these items are turned off, they draw a tiny amount of power to refresh the contents of their memory. This is why every time the power flickers, the VCR blinks 12:00. It's also why you lose all presets on your radio when your car battery dies! Your computer has FlashRAM to remember things like hard disk settings -- see Question 319 for details. VRAM - VideoRAM, also known as multiport dynamic random access memory (MPDRAM), is a type of RAM used specifically for video adapters or 3-D accelerators. The "multiport" part comes from the fact that VRAM normally has both random access memory and serial access memory. VRAM is located on the graphics card and comes in a variety of formats, many of which are proprietary. The amount of VRAM is a determining factor in the resolution and color depth of the display. VRAM is also used to hold graphics-specific information such as 3-D geometry data and texture maps.

Random access memory (RAM) is the best known form of computer memory. But the way it works and what the different terms mean can be very confusing.RAM is considered "random access" because you can access any memory cell directly if you know the row and column that intersect at that cell. The opposite of RAM is serial access memory (SAM). SAM stores data as a series of memory cells that can only be accessed sequentially (like a cassette tape). If the data is not in the current location, each memory cell is checked until the needed data is found. SAM works very well for memory

buffers, where the data is normally stored in the order it will be used. A good example is the texture buffer memory on a video card. How RAM Works

Similar to a microprocessor, a memory chip is an integrated circuit (IC) made of millions of transistors and capacitors. In the most common form of computer memory, dynamic random access memory (DRAM), a transistor and a capacitor are paired to create a memory cell, which represents a single bit of data. The capacitor holds the bit of information -- a 0 or a 1 (see How Bits and Bytes Work for information on bits). The transistor acts as a switch that lets the control circuitry on the memory chip read the capacitor or change its state. A capacitor is like a small bucket that is able to store electrons. To store a 1 in the memory cell, the bucket is filled with electrons. To store a 0, it is emptied. The problem with the capacitor's bucket is that it has a leak. In a matter of a few milliseconds a full bucket becomes empty. Therefore, for dynamic memory to work, either the CPU or the memory controller has to come along and recharge all of the capacitors holding a 1 before they discharge. To do this, the memory controller reads the memory and then writes it right back. This refresh operation happens automatically thousands of times per second. This refresh operation is where dynamic RAM gets its name. Dynamic RAM has to be dynamically refreshed all of the time or it forgets what it is holding. The downside of all of this refreshing is that it takes time and slows down the memory. Memory cells are etched onto a silicon wafer in an array of columns (bitlines) and rows (wordlines). The intersection of a bitline and wordline constitutes the address of the memory cell.DRAM works by sending a charge through the appropriate column (CAS) to activate the transistor at each bit in the column. When writing, the row lines contain the state the capacitor should take on. When reading: the sense-amplifier determines the level of charge in the capacitor. If it is more than 50% it reads it as a 1, otherwise as a zero. The counter tracks the refresh sequence based on which rows have been accessed in what order. The length of time necessary to do all this is so short that it is expressed in nanoseconds (billionths of a second). A memory chip rating of 70ns means that it takes 70 nanoseconds to completely read and recharge each cell. Memory cells alone would be worthless without some way to get information in and out of them. So the memory cells have a whole support infrastructure of other specialized circuits. These circuits perform functions such as: identifying each row (row address select or RAS) and column (column address select or CAS) keeping track of the refresh sequence (counter) reading and restoring the signal from a cell (sense amplifier) telling a cell whether it should take a charge or not (write enable). Other functions of the memory controller include a series of tasks that include identifying the type, speed and amount of memory and checking for errors. Static RAM uses a completely different technology. In static RAM, a form of flip-flop holds each bit of memory (see How Boolean Gates Work for detail on flip-flops). A flip-flop for a memory cell takes 4 or 6 transistors along with some wiring, but never has to

be refreshed. This makes static RAM significantly faster than dynamic RAM. However, because it has more parts, a static memory cell takes a lot more space on a chip than a dynamic memory cell. Therefore you get less memory per chip, and that makes static RAM a lot more expensive. So static RAM is fast and expensive, and dynamic RAM is less expensive and slower. Therefore static RAM is used to create the CPU's speed-sensitive cache, while dynamic RAM forms the larger system RAM space. Question: In my computer I know it uses DRAM (dynamic RAM) for the main memory. I have also heard of static RAM. What is the difference, and why are there two kinds? Answer: Your computer probably uses both static RAM and dynamic RAM at the same time, but it uses them for different reasons because of the cost difference between the two types. If you understand how dynamic RAM and static RAM chips work inside, it is easy to see why the cost difference is there, and you can also understand the names. Dynamic RAM is the most common type of memory in use today. Inside a dynamic RAM chip, each memory cell holds one bit of information and is made up of two parts: a transistor and a capacitor. These are, of course, extremely small transistors and capacitors so that millions of them can fit on a single memory chip. The capacitor holds the bit of information -- a 0 or a 1 (see How Bits and Bytes Work for information on bits). The transistor acts as a switch that lets the control circuitry on the memory chip read the capacitor or change its state. A capacitor is like a small bucket that is able to store electrons. To store a 1 in the memory cell, the bucket is filled with electrons. To store a 0, it is emptied. The problem with the capacitor's bucket is that it has a leak. In a matter of a few milliseconds a full bucket becomes empty. Therefore, for dynamic memory to work, either the CPU or the memory controller has to come along and recharge all of the capacitors holding a 1 before they discharge. To do this, the memory controller reads the memory and then writes it right back. This refresh operation happens automatically thousands of times per second. This refresh operation is where dynamic RAM gets its name. Dynamic RAM has to be dynamically refreshed all of the time or it forgets what it is holding. The downside of all of this refreshing is that it takes time and slows down the memory. Static RAM uses a completely different technology. In static RAM, a form of flip-flop holds each bit of memory (see How Boolean Gates Work for detail on flip-flops). A flip-flop for a memory cell takes 4 or 6 transistors along with some wiring, but never has to be refreshed. This makes static RAM significantly faster than dynamic RAM. However, because it has more parts, a static memory cell takes a lot more space on a chip than a dynamic memory cell. Therefore you get less memory per chip, and that makes static RAM a lot more expensive. So static RAM is fast and expensive, and dynamic RAM is less expensive and slower. Therefore static RAM is used to create the CPU's speed-sensitive cache, while dynamic RAM forms the larger system RAM space. How Flash Memory WorksElectronic memory comes in a variety of forms, to serve a variety of purposes. Flash memory is used for easy and fast information storage in such devices as digital cameras

and home video game consoles. It is used more as a hard drive than as RAM. In fact, Flash memory is considered a solid state storage device. Solid state means that there are no moving parts -- everything is electronic instead of mechanical. Here are a few examples of Flash memory: Your computer's BIOS chip CompactFlash (most often found in digital cameras) SmartMedia (most often found in digital cameras) Memory Stick (most often found in digital cameras) PCMCIA Type I and Type II memory cards (used as solid-state disks in laptops) Memory cards for video game consoles Flash memory is a type of EEPROM chip. It has a grid of columns and rows with a cell that has two transistors at each intersection (Figure 1). The two transistors are separated from each other by a thin oxide layer. One of transistors is known as a floating gate and the other one is the control gate. The floating gate's only link to the row, or wordline, is through the control gate. As long as this link is in place, the cell has a value of "1". To change the value to a "0" requires a curious process called Fowler-Nordheim tunneling. Tunneling is used to alter the placement of electrons in the floating gate. An electrical charge, usually 10-13 volts, is applied to the floating gate. The charge comes from the column, or bitline, enters the floating gate and drains to a ground. This charge causes the floating gate transistor to act like an electron gun. The excited electrons are pushed through and trapped on other side of the thin oxide layer, giving it a negative charge. These negatively charged electrons act as a barrier between the control gate and the floating gate. A special device called a cell sensor monitors the level of the charge passing through the floating gate. If the flow through the gate is greater than fifty percent of the charge, it has a value of "1". When the charge passing through drops below the fifty percent threshold: the value changes to "0". A blank EPROM has all of the gates fully open, giving each cell a value of "1".

Question: Does adding more RAM to your computer make it faster?

Answer Up to a point, adding RAM (Random Access Memory) will normally cause your computer to feel faster on certain types of operations. The reason why RAM is important because of an operating system component called the virtual memory manager. When you run a program like a word processor or an internet browser, the microprocessor in your computer pulls the executable file off the hard disk and loads it into RAM. In the case of a big program like Microsoft Word or Excel, the EXE consumes about 5 megabytes. The microprocessor also pulls in a number of shared DLLs (Dynamic Link Libraries) - shared pieces of code used by multiple applications. The DLLs might total 20 or 30 megabytes. Then the microprocessor loads in the data files that you want to look at, which might total several megabytes if you are looking at several documents or browsing a page with a lot of graphics. So a normal application needs between 10 and 30

megabytes of RAM space to run. On my machine at any given time I might have the following applications running:

A word processor A spreadsheet A DOS prompt An email program A drawing program 3 or 4 browser windows A Fax program A Telnet session Besides all of those applications, the operating system itself is taking up a good bit of space. Those programs together might need 100 to 150 megabytes or RAM, but my computer only has 64 megabytes of RAM installed. The extra space is created by the virtual memory manager. The VMM looks at RAM and finds sections of RAM that are not currently needed. It puts these sections of RAM in a place called the swap file on the hard disk. For example, even though I have my email program open, I haven't looked at email in the last 45 minutes. So the VMM moves all of the bytes making up the email program's EXE, DLLs and data out to the hard disk. That is called swapping out the program. The next time I click on the email program, the VMM will swap in all of its bytes from the hard disk, and probably in the process swap something else out. Because the hard disk is slow relative to RAM, the act of swapping things in and out causes a noticable delay.

If you have a very small amount of RAM (say 16 megabytes), then the VMM is always swapping things in and out to get anything done. In that case your computer feels like it is crawling. As you add more RAM you get to a point where you only notice the swapping when you load a new program or change windows. If you were to put 256 megabytes of RAM in your computer the VMM would have plenty of room and you would never see it swapping anything. That is as fast as things get. If you added more RAM it would have no effect.

Some applications (things like Photoshop, many compilers, most film editing and animation packages, etc.) needs tons of RAM to do their job. If you run them on a machine with too little RAM, they swap constantly and run very slowly. You can get a huge speed boost by adding enough RAM to eliminate the swapping. Programs like these may run 10 to 50 times faster once they have enough RAM.

RING COUNTER:

A ring counter is a type of counter composed of a circular shift register. The output of the last shift register is fed to the input of the first register.

There are two types of ring counters:

A straight ring counter or Overbeck counter connects the output of the last shift register to the first shift register input and circulates a single one (or zero) bit around the ring. For example, in a 4-register one-hot counter, with initial register values of 1000, the repeating pattern is: 1000, 0100, 0010, 0001, 1000... . Note that one of the registers must be pre-loaded with a 1 (or 0) in order to operate properly.

A twisted ring counter (also called Johnson counter or Moebius counter) connects the complement of the output of the last shift register to its input and circulates a stream of ones followed by zeros around the ring. For example, in a 4-register counter, with initial register values of 0000, the repeating pattern is: 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000... .

If the output of a shift register is fed back to the input. a ring counter results. The data pattern contained within the shift register will recirculate as long as clock pulses are applied. For example, the data pattern will repeat every four clock pulses in the figure below. However, we must load a data pattern. All 0's or all 1's doesn't count. Is a continuous logic level from such a condition useful?

We make provisions for loading data into the parallel-in/ serial-out shift register configured as a ring counter below. Any random pattern may be loaded. The most generally useful pattern is a single 1.

Loading binary 1000 into the ring counter, above, prior to shifting yields a viewable pattern. The data pattern for a single stage repeats every four clock pulses in our 4-stage example. The waveforms for all four stages look the same, except for the one clock time delay from one stage to the next. See figure below.

Fig: Ring counter with SR flip-flops

The above block diagram shows the power controlled Ring counter.First, total block is devided into two blocks. Each block is having one SR FLIPFLOP controller.

PRESENT TECHNIQUE:

GATED DRIVER TREE:

derived from the same clock gating signals of the blocks that they drive. Thus, in a quad-tree clock distribution network, the “gate” signal of the th gate driver at the th level (CKE ) should be asserted when the active DET flip-flop .

MODIFIED RING COUNTER:

DET :(Double edge triggered flip-flops: double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half The logic construction of a double-edge-triggered (DET) flip-flop, which can receive input signal at two levels the clock, is analyzed and a new circuit design of CMOS DET In this paper, we propose to use double-edge-triggered (DET) flip-flops instead of traditional DFFs in the ring counter to halve the operating clock frequency. Double edge-triggered flipflops are becoming a popular technique for low-power designs since they effectively enable a halving of the clock frequency. The paper by Hossain et al[1] showed that while a single-edge triggered flipflop can be implemented by two transparent latches in series, a double edge-triggered flipflop can be implemented by two transparent latches in parallel; the circuit in Fig. 1 was given for the static flipflop implementation. The clock signal is assumed to be inverted locally. In high noise or low-voltage environments, Hossain et al noted that the p-type pass-transistors may be replaced by n-types or that all pass-transistors may be replaced by transmission gates.

C ELEMENT: The Muller C-element, or Muller C-gate, is a commonly used asynchronous logic component originally designed by David E. Muller. It applies logical operations on the inputs and has hysteresis. The output of the C-element reflects the inputs when the states of all inputs match. The output then remains in this state until the inputs all transition to the other state. This model can be extended to the Asymmetric C-element where some inputs only effect the operation in one of the transitions (positive or

negative). The figure shows the gate-level and transistor-level implementations and symbol of the C-element.

he C-element stores its previous state with two cross-coupled inverters, similar to an SRAM cell. One of the inverters is weaker than the rest of the circuit, so it can be overpowered by the pull-up and pull-down networks.

If both inputs are 0, then the pull-up network changes the latch's state, and the C-element outputs a 0. If both inputs are 1, then the pull-down network changes the latch's state, making the C-element output a 1. Otherwise, the input of the latch is not connected to either Vdd or ground, and so the weak inverter (drawn smaller in the diagram) dominates and the latch outputs its previous state.

The Muller C-element was first used in the arithmetic logic unit (ALU) of the ILLIAC II supercomputer, proposed in 1958, and operational in 1962.

Here is the truth table for a 2-input c-gate. Yn − 1 denotes a "no change" condition

7.VHDL INTRODUCTION

Why VHDL?A design engineer in electronic industry uses hardware description

language to keep pace with the productivity of the competitors. With VHDL we

can quickly describe and synthesize circuits of several thousand gates. In addition

VHDL provides the capabilities described as follows:

Power and flexibility

VHDL has powerful language constructs with which to write succinct code

description of complex control logic. It also has multiple levels of design description for

controlling design implementation. It supports design libraries and creation of

reusable components. It provides Design hierarchies to create modular designs. It is one

language fort design and simulation.

Device –Independent designVHDL permits to create a design without having to first choose a device foe

implementation. With one design description, we can target many device architectures.

Without being familiar with it, we can optimize our design for resource or performance.

It permits multiple style of design description.

PortabilityVHDL portability permits to simulate the same design description that we have

synthesized. Simulating a large design description before synthesizing can save

considerable time. As VHDL is a standard, design description can be taken from one

simulator to another, one synthesis tool to another; one platform to another-means

description can be used in multiple projects.

Benchmarking capabilities Device–independent design and portability allows benchmarking a design using

different device architectures and different synthesis tool. We can take a complete design

description and synthesize it, create logic for it, evaluate the results and finally choose the

device-a CPLD or an FPGA that fits our requirements.