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Memory Designing Memory Designing Using Josephson Using Josephson Gates Gates Susmit Biswas Susmit Biswas 02/07/2006 02/07/2006

Memory Designing Using Josephson Gates Susmit Biswas 02/07/2006

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Page 1: Memory Designing Using Josephson Gates Susmit Biswas 02/07/2006

Memory Designing Using Memory Designing Using Josephson GatesJosephson Gates

Susmit BiswasSusmit Biswas02/07/200602/07/2006

Page 2: Memory Designing Using Josephson Gates Susmit Biswas 02/07/2006

OutlineOutline

Refreshing MemoryRefreshing Memory Memory CircuitsMemory Circuits CMOS Memory CircuitsCMOS Memory Circuits

Need For New Memory TechnologyNeed For New Memory Technology Josephson PC MemoryJosephson PC Memory

Previous WorkPrevious Work Josephson JunctionJosephson Junction Memory Designing Using Josephson GateMemory Designing Using Josephson Gate Performance EvaluationPerformance Evaluation

ConclusionConclusion

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Standard Memory TechnologyStandard Memory Technology

The Memory HierarchyThe Memory Hierarchy CPU RegistersCPU Registers L1 Cache (SRAM)L1 Cache (SRAM) L2 Cache (SRAM)L2 Cache (SRAM) Main MemoryMain Memory

SRAMSRAM DRAMDRAM

FPM DRAM (Fast Page Mode DRAM)FPM DRAM (Fast Page Mode DRAM) EDORAM (Extended Data Out DRAM )EDORAM (Extended Data Out DRAM ) SDRAM (Synchronous DRAM)SDRAM (Synchronous DRAM) DDR DRAM (Double Data Rate DRAM)DDR DRAM (Double Data Rate DRAM)

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DRAMDRAM

High Density and low powerHigh Density and low power but Slower than SRAMbut Slower than SRAM

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DRAM PerformanceDRAM Performance

(August 2005)(August 2005)

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Need For New TechnologyNeed For New Technology

Memory is the main bottleneck nowMemory is the main bottleneck now Multiprocessor system suffers mostMultiprocessor system suffers most SIMD and MIMD architectureSIMD and MIMD architecture

Data hungryData hungry

Page 7: Memory Designing Using Josephson Gates Susmit Biswas 02/07/2006

Josephson Memory: Previous WorkJosephson Memory: Previous Work

Josephson Junction:Josephson Junction: Discovered and Demonstrated in early 60’sDiscovered and Demonstrated in early 60’s IBM till 1983IBM till 1983

Nearly functional 1kBit memory using lead-alloyNearly functional 1kBit memory using lead-alloy

1980s : ETL, NTT using Nb/Al0x/Nb1980s : ETL, NTT using Nb/Al0x/Nb 1993 : UC Berkeley designed a 4 kBit RAM1993 : UC Berkeley designed a 4 kBit RAM 1997 : NEC developed a 4 kBit Memory1997 : NEC developed a 4 kBit Memory 2002 : Hybrid Josephson memory2002 : Hybrid Josephson memory

Page 8: Memory Designing Using Josephson Gates Susmit Biswas 02/07/2006

Looking BackLooking Back

1962: 1962: Josephson predicted that a sandwich of S-I-S will show remarkable properties when the insulator is sufficiently thin ~ 10Å or so

Current can flow through the junction with no voltage appearing across the junction until a critical current IJ is exceeded

The magnitude of IJ, depends sensitively on magnetic fields. A voltage Vdc, impressed across the junction leads to an oscillating supercurrent whose frequency is proportional to the voltage. The frequency is very high for even modest voltages (483 MHz/μV).

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Josephson EffectJosephson Effect

Two-fluid model of Superconductor: One of the fluids is the normal fluid, the other the superfluid. Superfluid consists of paired electrons (Cooper pairs) of equal but opposite momentum and spin

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Josephson EffectJosephson Effect

Bound pairs electrons all lie near the Fermi energy EF of the normal metal; the resulting pairs are in an energy state lower than EF by an amount Δ (binding energy of the pair (per electron)

As T becomes less than Tc, pairs begin to form and condense into the superconducting state

At V = 2 Δ /e the tunneling current increases sharply (with +∞ slope)

For V >> 2 Δ/e the current increases linearly with V

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Josephson JunctionJosephson Junction

Josephson Effect: Josephson Effect: In superconducting state of certain metals, In superconducting state of certain metals, electrons are attracted by each other and form bound pairs, called electrons are attracted by each other and form bound pairs, called Cooper pairsCooper pairs. When these pairs of electrons tunnel through a thin . When these pairs of electrons tunnel through a thin insulating barrier placed between two superconductors, the whole is insulating barrier placed between two superconductors, the whole is called called Josephson junctionJosephson junction..

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Josephson Junction CharacteristicsJosephson Junction Characteristics

Control currents Control currents IIcc,,

Josephson threshold Josephson threshold IImm..

Gate current Gate current IIgg,,

I-V Curve Threshold Curve

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Josephson Junction As MemoryJosephson Junction As Memory

Consists of a loop with three Josephson junctions in Consists of a loop with three Josephson junctions in series that encloses a magnetic flux series that encloses a magnetic flux ФФ driven by an driven by an external magnet.external magnet.

The loop may have multiple stable persistent current The loop may have multiple stable persistent current states when the enclosed magnetic flux is close to half a states when the enclosed magnetic flux is close to half a superconducting flux quantum superconducting flux quantum ФФ

ФФ = = h h / 2/ 2ee System has two stable states System has two stable states

00׀׀ ›› and and 11׀׀ ›› with oppositewith opposite

circulating persistent currentscirculating persistent currents

Page 14: Memory Designing Using Josephson Gates Susmit Biswas 02/07/2006

Josephson Junction As Memory ( Josephson Junction As Memory ( contcont.).)

Operated by resonant microwave modulation of the Operated by resonant microwave modulation of the enclosed magnetic flux by a superconducting control line enclosed magnetic flux by a superconducting control line on top of the qubit, separated by a thin insulator. on top of the qubit, separated by a thin insulator.

The state of a bit (0 or 1) depends on the sum of the The state of a bit (0 or 1) depends on the sum of the external magnetic flux generated by the circulating external magnetic flux generated by the circulating currents on the surrounded loops: currents on the surrounded loops: 0 if magnetic field is < 1/2 0 if magnetic field is < 1/2 ФФ 1 if magnetic field is > 1 if magnetic field is > 1/2 1/2 ФФ

The state of the system is the superposition of all the The state of the system is the superposition of all the states generated by the circulating current in each loop.states generated by the circulating current in each loop.

Page 15: Memory Designing Using Josephson Gates Susmit Biswas 02/07/2006

Josephson Junction As Memory ( Josephson Junction As Memory ( contcont.).)

Combining several junctions results in different gates Combining several junctions results in different gates e.g. invertere.g. inverter Can be designed in two waysCan be designed in two ways

coupling two superconductive loops directly through coupling two superconductive loops directly through magnetic interferencemagnetic interference

Coupling two loops through a superconductive flux Coupling two loops through a superconductive flux transportertransporter

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Josephson Junction As Memory ( Josephson Junction As Memory ( contcont.).)

Stronger interaction between the PC loops and better coupling to Stronger interaction between the PC loops and better coupling to each other with the facilitation of transportereach other with the facilitation of transporter

But!But! Coupling between neighboring loops makes it difficult for long-range Coupling between neighboring loops makes it difficult for long-range

communicationcommunication

SolutionSolution Transporter: fast data propagationTransporter: fast data propagation

Page 17: Memory Designing Using Josephson Gates Susmit Biswas 02/07/2006

Josephson Junction As Memory ( Josephson Junction As Memory ( contcont.).)

NMV Gate can serve as NAND, NOR and NOT gate by setting NMV Gate can serve as NAND, NOR and NOT gate by setting instruction bits.instruction bits.

Not Majority Vote (NMV) Gate

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Memory Designing Using Memory Designing Using Josephson GateJosephson Gate

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Memory Designing Using Memory Designing Using Josephson Gate (cont.)Josephson Gate (cont.)

A memory cell can not be refreshed by either a row or a A memory cell can not be refreshed by either a row or a column addressing line independentlycolumn addressing line independently

the addressing lines are designed in such a way that the the addressing lines are designed in such a way that the states of other cells in the same column are suppressed states of other cells in the same column are suppressed during reading, the selected one gets the bit from its during reading, the selected one gets the bit from its adjacent memory cell, without interacting with its adjacent memory cell, without interacting with its neighbors in the same column.neighbors in the same column.

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Performance EvaluationPerformance Evaluation

Pros: Pros: SpeedSpeed: : 750GHz750GHz for single asynchronous cells and up to for single asynchronous cells and up to 320GHz 320GHz for LSI for LSI

devicesdevices

Low powerLow power consumption consumption 0.2nanowatt/GHz 0.2nanowatt/GHz per pulse and per pulse and 0.1mW 0.1mW for LSI devicesfor LSI devices

Simple fabrication technology : lithographySimple fabrication technology : lithography

Cons: Cons: Low densityLow density Operational temperature <20KOperational temperature <20K

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Performance Evaluation (cont.)Performance Evaluation (cont.)

Comparison of projected 2.5μm technology Josephson NDRO and DRO chip designs with advanced silicon memories having comparable line widths.

Page 22: Memory Designing Using Josephson Gates Susmit Biswas 02/07/2006

ConclusionConclusion

Josephson memory can become more and more Josephson memory can become more and more popular because of its speed and low power popular because of its speed and low power characteristicscharacteristics

Designing larger memory is difficultDesigning larger memory is difficult Low densityLow density Limitation of fabrication technologyLimitation of fabrication technology

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ReferencesReferences

1.1. ““Novel Computing Architecture on Arrays of Josephson Novel Computing Architecture on Arrays of Josephson Persistent Current Bits”Persistent Current Bits” : : Jie Han, Pieter Jonker [Jie Han, Pieter Jonker [Proc. Proc. MSM 2002MSM 2002 ] ]

2.2. ““Memory-Cell Design in Josephson Technology” : Memory-Cell Design in Josephson Technology” : Hans H. Zmpe [IEEE Transactions On Electron Hans H. Zmpe [IEEE Transactions On Electron Devices, VOL. ED-27, NO. 10, OCTOBER 1980]Devices, VOL. ED-27, NO. 10, OCTOBER 1980]

3.3. ““570-ps 13-mW Josephson 1kbit NDRO RAM” : 570-ps 13-mW Josephson 1kbit NDRO RAM” : Shuichi NagasawaShuichi Nagasawa et. al. et. al. [IEEE Journal of Solid-State [IEEE Journal of Solid-State Circuits, Vol 24, No 5, October, 1989] Circuits, Vol 24, No 5, October, 1989]

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ReferencesReferences

4.4. ““Design Of A 16-kbit Variable Threshold Josephson Design Of A 16-kbit Variable Threshold Josephson RAMRAM”: I. Kurosawa, [IEEE Transactions On Applied ”: I. Kurosawa, [IEEE Transactions On Applied Superconductivity, Vol. 3, No.l, March1993]Superconductivity, Vol. 3, No.l, March1993]

5.5. ““Josephson Type Superconductive Tunnel Junctions Josephson Type Superconductive Tunnel Junctions and Applications”and Applications” : Juri Matisoo [ : Juri Matisoo [IEEE TRANSACTIONS ON XAGNETICS, DECEMBER 1969]

6.6. httphttp://www.lne.fr/en/r_and_d/electrical_metrology/josephso://www.lne.fr/en/r_and_d/electrical_metrology/josephson_effect_ej.shtmln_effect_ej.shtml

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