ME/EE 561 Design of Digital Control Systemshpeng/ME561-Lecture-1 Introduction.pdf · – Computer Controlled Systems-Theory and Design, ... Volt amp Saturation1 ... • A simple way

Copyright G.Chiu and H.Peng ME561 Lecture1- 1

ME/EE 561 Design of Digital Control SystemsWinter 2012

Professor Huei Peng

G036 Auto [email protected]

734-936-0352

Office hours: Monday 3:35-4:30, Wednesday4:30-5:35or by appt.


Lecture 1-- Introduction and Motivation

Why Digital Control (Computer Controlled) Systems

About this course Objectives Course content Grading policy HW, Exams, Final project

Basics of Digital Control Systems


ME461EE460

ME561EE561


Motivation for Controls Feedback control has a long history which began with the

early desire of humans to harness the forces of nature, improve productivity, and to avoid hazardous/laborious/repetitive work.

Watts Fly Ball Governor had a major impact on the industrial revolution (mechanical control).

Most modern systems (aircrafts, automobiles, production lines, CD players, etc.) could not operate without the aid of control systems.

Photos from G. Goodwins lecture slides


Evolution of Control Systems

Mechanical control systems e.g., Watts Fly Ball Governor

Analog (electrical/electronics) control systems e.g., Op-amp plus RC circuits based controllers.

Digital (computer) control systems Apparently a lot more flexible than the two types above computer, DSP, microprocessor


Computer Controlled Systems Direct Digital Control (1960s)implementation

of PID control algorithms on large systems (chemical, power plants, space, military).

Now, complex and intelligent algorithms.

From: W. Powers, AVEC 2000


Microprocessor Based Control Systems--example on motor control

Source: http://www.ti.com/sc/docs/psheets/diagrams/dmc.htm


AD and DA

r

ReferenceComputerPlant

+

Outputy u e

D/A A/D

Clock

Digital control system deals with digitized (discretized) signals.

AD/DA devices translate continuous signals to/from digital signals.


Two Forms of Discretizations

Sampling (discretize in time)

Quantization (discretize in magnitude)

ContinuousSignal

DiscreteSignal

1 2 3 4 5 6 7 8 9 10 kT

uu(kT) u(t)

Average u(t)


Inherently Discrete-Time (Sampled) Systems

Economic Systems Radar, GPS Accurate emission measurement of internal

combustion engines, or some medical sensors Internal combustion engines control in general Signals transmitted in nervous systems Systems with embedded computers,

microprocessors or clocks


Objective of This Course

To introduce the concepts of sampling, discrete-time signals/systems, and the analysis and synthesis of digital control systems Upon completion of this course, you should be able to

construct discrete-time models, design digital control algorithms and analyze the openloop and closed-loop behavior.


This Course is NOT

EECS 461 Embedded Control Systems ME 552 Mechatronics System Design

MIT 6.111 Introductory Digital Systems Laboratory

http://ocw.mit.edu/OcwWeb/Electrical-Engineering-and-Computer-Science/index.htm


There is no textbookcourse pack provided Reference books

Computer Controlled Systems-Theory and Design, Prentice-Hall, 1997(3rd edition), Astrom, K. J. and Wittenmark, B.

Discrete-Time Control Systems, Prentice-Hall, 1995 (2nd edition), K. Ogata.

Course Material

http://www.amazon.com/exec/obidos/tg/detail/-/0133148998/103-5327290-9742228?v=glance

http://www.amazon.com/exec/obidos/tg/detail/-/0130342815/103-5327290-9742228?v=glance


Major course content

Chapter 1 Introduction to Computer Controlled SystemsChapter 2 Sampled Data AnalysisChapter 3 The Z-Transform and the Difference EquationsChapter 4 Discrete-Time System RepresentationChapter 5 Analysis of Discrete-Time SystemsChapter 6 Design of Discrete Time Controller

Input/Output ApproachesChapter 7 Design of Discrete Time Controller

Polynomial ApproachesChapter 8 Design of Discrete Time Controller

State Space ApproachesChapter 9 Linear Quadratic Optimal ControlChapter 10 Optimal Linear Feedback of Stochastic SystemsChapter 11 Optimal Design Methods: Input/Output Approach


CTool Course Web Site

https://ctools.umich.edu/portal


Grading Policy

Grading: Homeworks 45%

Midterm 20%

Final 35%


Grading Policy (cont.)

Homework: 7-8 HW assignments. Due at the endof class on the due date. Homework will be acceptedup to 48 hours late with a 25% penalty for each 24hours. Standard Michigan Honor Code applies.

Exams: Midterm: Mar. 5 (Tue.) in classFinal: April. 25 (Wed.) 1:30-3:30pmNo make-up exam.Regrade request within 3 days in writing(no exceptions!!)

tentative


Competing Resources

Better ActuatorsProvide more Muscle

Better SensorsProvide better Vision

Better ControlProvides more finesse by combining sensors and actuators in more intelligent ways


MATLAB/SIMULINK

http://www.engin.umich.edu/group/ctm/ or http://www.engin.umich.edu/class/ctms/


Vf

Vz

4Feed per tooth

3delta_Z

2Z Force

1Feed Force

d_nom

nomianl depth

-K-

feed->ft

Zero-OrderHold1

Zero-OrderHold

Sz

Z sti ffness

Kzs

tau_zs.s+1

Z sl ide

f(u)

Z forceKa

Volt amp1

Ka

Volt amp

Saturation1

Saturation

1

1Sampl ing

1

1Samp

s

1

Integrator

Kfd

Force ->Volt

Kfs

tau_fs.s+1Feed sl ide

f(u)

Feed force

Sf

F sti ffness

3Disturbance depth

2Vcz

1Vcf

2

2

Ex1_0 A Useful MATLAB Command

[A_c, B_c, C_c, D_c] = linmod(Ex1_0)[A_d, B_d, C_d, D_d] = dlinmod(Ex1_0, Ts)

Note the possibility to linearize at non-zero x and u ([A,B,C,D]=LINMOD('SYS',X,U), see help linmod)

Example from 2001 machining project

4x3 (why?)3x3 (why?)


A simple way to design a discrete-time control system is to start with classical techniques to design a continuous-time compensator for a plant.

The continuous-time compensator can then be approximated by a discrete-time, sampled-data system. This process is known as emulation.

Discrete-Time Design by Emulation


Emulation (cont.)

rControllerC(s)

PlantG(s)

+

y u e

rG(s)

+

y DigitizedControl

Algorithm

u(t)D/A A/D

Clock

C(s)

u(kT) e(t)e(kT)

T

Emulation (indirect design)

Sample and hold


Sample and Hold

Discrete-Time Control Systems, Ogata


A/D Several circuit design types

Successive-approximationn clock cycles for n-bit accuracy (Single-slope) Integration Counter (voltage to frequency) Parallel (Flash) encoding

Figure 1-9 from Discrete-Time Control Systems, Ogata

The Art of Electronics, Horowitz and Hill, pp.415


D/A Weighted resistors

R-2R ladder circuit

The Art of Electronics, Horowitz and Hill, pp.410-411


Emulation Methods

Approximate continuous-time operations (e.g., differentiation) with discrete-time operations (e.g., difference). (Forward) Euler Trapezoidal with Pre-warp Matched pole/zero Zero-Order Hold (ZOH)


Euler Approximation

limx xtt

0

( ) ( ) ( )x k x k x kT

1

where

T t tt kTkx k x tx k x t

k k

k

k

k

1

11

(the sampling period in seconds),for a constant sampling period

is an integer,is the value of at time , and

is the value of at time .

( ),

( )( )


Ex1_1 Emulation Using Euler Approximation

C s U sE s

K s as b

( ) ( )( )

rControllerC(s)

PlantG(s)

+

y u e

( ) ( ) ( ) ( )s b U s K s a E s ( )u bu K e a e Euler approximation:

( ) ( ) ( )x k x k x kT

1

u k u kT

b u k K e k e kT

a e k( ) ( ) ( ) ( ) ( ) ( ) LNMOQP

1 1

u k bT u k K aT e k K e k( ) ( ) ( ) ( ) ( ) ( ) 1 1 1 1

( ) (1 ) ( 1) ( 1) ( 1) ( )u k b u k K a e kT T K e k or


Ex1_2 Simulation of Euler-Emulated ControllerLead compensator

rControllerC(s)

PlantG(s)

+

y u e

C s ss

( )

50 210

G ss s

( )( )

1

1

Implement Euler-emulated digital controller at 5Hz, 10Hz and 30Hz

xxx o


Ex1_2 MATLAB Implementation of the Continuous-Time System

% Construct the plant transfer function:G_num = 1;G_den = [1 1 0];G = tf(G_num, G_den);

% Construct the compensator transfer function:C_num = 50*[1 2];C_den = [1 10];C = tf(C_num, C_den);

% The open-loop transfer function can be simply calculated by:OP = G*C;

% The closed-loop transfer function is:CL = feedback(OP,1,-1);% Or you can use the following arithmetic:CL1 = OP / (1+OP);% OrCL2 = OP * inv(1+OP);

% The unit step response of the closed-loop system:[y,t] = step(CL);

C s ss

( )

50 210

G ss s

( )( )

1

1

rControllerC(s)

PlantG(s)

+

y u e


Ex1_2 SIMULINK Implementation of the Continuous-Time System

t

Time

Step

Scope

y

Response (Output)

1

s +s2

Plant

50(s+2)

(s+10)

Lead Compensator

Clock


Ex1_2 Discrete-Time Controller

Zero-OrderHold

t_digital

Time

Step

Scope

1

1

Sampling

y_digital

Response(Output)

1

s +s2

Plant

50z+50*(-0.9333)

z-0.6667

Discrete Implementation of the Lead Compensator

Clock

MATLAB: see notes Coefficients dependon T

Time step = T


Ex1_2 Results

0 0.5 1 1.50

0.2

0.4

0.6

0.8

1

1.2

Time (sec)

Uni

t Ste

p Res

pons

e

Analog ControlDigital Control (10 Hz)

0 0.5 1 1.50

0.2

0.4

0.6

0.8

1

1.2

Time (sec)

Uni

t Ste

p Res

pons

e


30Hz10Hz

0 0.5 1 1.50

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

Time (sec)(b)

Unit St

ep R

espo

nse

Analog ControlSampled Digital Output (5 Hz)Actual Output

0 0.5 1 1.50

0.2

0.4

0.6

0.8

1

1.2

Time (sec)( )

Unit St

ep R

espo

nse


5Hz


Issues for Digital Control Systems

Sampling time for emulated designs need to be at least about 20-30 times closed-loop bandwidth. Else inter-sampling behavior becomes questionable

Clock Dependency. Aliasing (Though briefly discussed in Chapter 1,

explained in more details in Chapter 2) Time delay due to Sample/Hold. Need for discrete-time models.


Ex1_3 Clock Dependency

DigitizedControl

Algorithm

u(t)D/A A/D

Clock

C(s)

u(kT) e(t)e(kT)

T

0 1 2 3 4 5 60

0.2

0.4

0.6

0.8

1

Ste

p R

espo

nse

0 1 2 3 4 5 60

0.2

0.4

0.6

0.8

1

Ste

p R

espo

nse

Time

0 1 2 3 4 5 60

0.2

0.4

0.6

0.8

1

Ste

p R

espo

nse

0 1 2 3 4 5 60

0.2

0.4

0.6

0.8

1S

tep

Res

pons

e

Time

Reference StepContinuous-Time ResponseDigital Response

( ) aC ss a


Since sampling will lose information in between samples, digital control will always be inferior to its continuous-time counter part, i.e. we cannot expect better performance from digital control The above argument is true for emulation implementation

Although sampling inevitably loses information, digital control does pose some unique design flexibilities that are not achievable through continuous-time LTI control

Dead-beat control is one example.

Common Myth


Ex1_4 Dead-Beat Control

rController

C(s)ArmGA(s)

y uAmplifierk

Open-Loop Frequency Response

2( ) ( )AkG s k G s

J s Plant:

( ) ( ) ( )bK s bU s R s K Y sa s a

Control law:

102

3 20 0 0

1( )( )( ) 2 2 1

CL

sY sG sR s s s s

0 1 2 3 4 5 6 7 8 9 100

0.5

1

1.5

Posi

tion

0 1 2 3 4 5 6 7 8 9 10-0.2

0

0.2

0.4

0.6

0.8

Velo

city

0 1 2 3 4 5 6 7 8 9 10-1

-0.5

0

0.5

1

Time

Con

trol I

nput

Analog Control Response

0 1 2 3 4 5 6 7 8 9 100

0.5

1

1.5

Posi

tion

0 1 2 3 4 5 6 7 8 9 10-0.2

0

0.2

0.4

0.6

0.8

Velo

city

0 1 2 3 4 5 6 7 8 9 10-1

-0.5

0

0.5

1

Time

Con

trol I

nput

Analog Control ResponseDigital Control ResponseSampled Response


Ex1_5 Aliasing/Beating

C(s)e(t)u(t)

0 2 4 6 8 10

-1

-0.5

0

0.5

1

Time

Res

pons

e

0 2 4 6 8 10

-1

-0.5

0

0.5

1

Time

Res

pons

e

0 2 4 6 8 10

-1

-0.5

0

0.5

1

Time

Res

pons

e

0 2 4 6 8 10

-1

-0.5

0

0.5

1

Time

Res

pons

e

-1

-0.5

0

0.5

1

0 2 4 6 8 10

Inpu

t

-1

-0.5

0

0.5

1

0 2 4 6 8 10

Inpu

t

4.9 Hz sine wave

DigitizedControl

Algorithm

u(t)D/A A/D

Clock

C(s)

u(kT) e(t)e(kT)

T

10 Hz sampling

0 2 4 6 8 10

-1

-0.5

0

0.5

1Sa

mpl

ed In

put

0 2 4 6 8 10

-1

-0.5

0

0.5

1Sa

mpl

ed In

put

http://library.thinkquest.org/19537/java/Beats.html


4.9 Hz sine wave and 10Hz Sampling

Period = 1/4.9 sec = 204 msec

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

t=0:0.001:1;y=sin(9.8*pi*t);t2 = 0:0.1:1;y2 = sin(9.8*pi*t2);plot(t, y, t2, y2, 'ro')


Time Delay Due to Sample/Hold

Delay ~ T/2 which deteriorates phase margin and damping (see Example 1_6)

1 2 3 4 5 6 7 8 9 10 kT

uu(kT) uH(t)

Average u(t)


Ex1_6

ZOH introduces additional phase lag, which reduces the phase margin of the continuous-time design The amount of the phase lag is proportional to the frequency

Device in digital feedback loop that reduces phase margin Hold circuits (D/A) Low-pass (anti-aliasing) filter

1 2 3 4 5 6 7 8 9 10 kT

u u(t)u(kT) ZOH signal uH(t)

Averaged signal u(t)

2

( )2

( ) ( )T s

Tu t u t

U s U se

L

2 21 and 2T Tj j

Te e


Effect of Delay due to S/H Suppose we implement a virtual stiffness of

F= -kx. Due to the delay, a hysteresis is generated and positive energy may be added to the controlled plant.

F

x

m1k

Compression

Rebound


Digital Control Design Process

emulate

Physical Process(Plant)

Select SamplingFrequency

Discrete-TimeControl Model

Discrete-TimeController Design

PerformanceEvaluation & Analysis

Implementation

Continuous-TimeController Design

Continuous-TimeControl Model


Select SamplingFrequency


Detail Dynamic Model

(Simulation Model)

Direct DesignDirect DesignIndirect DesignIndirect Design

Documents

ME/EE 561 Design of Digital Control Systemshpeng/ME561-Lecture-1 Introduction.pdf · – Computer Controlled Systems-Theory and Design, ... Volt amp Saturation1 ... • A simple way