MECH466 Lecture 16

1MECH 466

Microelectromechanical Systems

University of VictoriaDept. of Mechanical Engineering

Lecture 16:

Microfabrication Technologies

N. Dechev, University of Victoria

2

Detailed look at Bulk Micromachining

Detailed look at Surface Micromachining

MUMPs Micromachining

SUMMiT Micromachining

Overview


3Microfabrication using Bulk Micromachining

Bulk Micromachining is based on the etching and bonding of thick sheets of material such as silicon oxides and crystalline silicon.

There are three main types of methods for Bulk Micromachining:

Anisotropic Wet Etching

Isotropic Wet Etching (Silicon & Glass)

Dry Etching

- Gas and Plasma Etching- Reactive Ion Etching- Deep Reactive Ion Etching


Fig 10.1 Definition of isotropic and anisotropic etching

[Foundations of MEMS, Chang Liu]

4

Anisotropic (directional) etching along crystal planes.

A liquid Wet etchant is used to remove the bulk material.



Silicon Crystal Orientations,

[Chang Liu]

5Anisotropic Wet Etching

Silicon Substrate

Wafer inserted into High Temp Furnace with oxygen gas,

to grow oxide layer


6

Silicon Substrate

HF Acid Etch

Oxide is patterned with photolithography (Not Shown)

Oxide



7Silicon Substrate

Wet Silicon Etchant



8

Silicon Substrate

54.7



9EDP (Ethylene diamine pyrocatechol) @ 90oC

- Etch rate ratio for and is as high as 35:1 or higher [Petersen]

- Etch rate for silicon nitride and silicon oxide is almost negligible.

- Native oxide becomes important in processing

- Highly directional selective, allows cheap oxide as mask.

Disadvantage: Expensive; chemically unstable.

- Aging: etch rate and color changes with time after exposure to oxygen.

KOH (Potassium hydroxide) @ 75-90oC

- Various concentrations can be used, 20-40 wt % is common.

- Etch rate ratio for and is much higher than that of EDP.

- Etch rate on silicon nitride (LPCVD) is negligible.

Disadvantages: Etch rate on silicon oxide is not negligible.

- 14 angstrom/min. (thermally grown oxide quality).

- e.g. a process that lasts for 10 hours consumes 0.84 mm of oxide.


Commonly Used Silicon Wet Etchants

10

Temperature control is critical in controlling etch rate. Solutions are usually heated on precision controlled hot plates to 90-100C depending on desired temperature.

Escaping vapour may alter concentration of solution. Therefore a Reflux System is used to recapture vapour, and divert it back into the solution.

Gas toxicity requires that etching be done with proper safety equipment (i.e. fume hoods)


Anisotropic Wet Etching Equipment

Reflux System

Reflux Wet Etch System [Image from Chang Liu]

11

Computer simulations of anisotropic wet etching can be done using ACES freeware.

Process begins with definition of mask shape as bitmap:

Simulation will predict etching of underlying silicon, based upon Mask alignment with respect to crystal planes, etchant used, and time of process.


Prediction of Anisotropic Wet Etching

Initial Bitmap MaskSimulation output based on Bitmap,

and other Parameters

3D Visualization of Simulation Output

12

Example of two bitmap shapes:



Initial Bitmap Mask Time T = 1

Time T = 2

13 N. Dechev, University of Victoria


Time T = 3

Time T = 4

Time T = 5

Time T = 50

14

Wet Etching of Rectangle Mask,

with edges oriented along vectorsWet Etching of Rectangle Mask,

with edges oriented along vectors

Wet Etching of Oval Mask,

with major axis oriented along [100] vector


Movies Anisotropic Wet Etching

15

Download ACES freeware software from the following website:

http://mass.micro.uiuc.edu/research/completed/aces/pages/home.html

Simulation the following Bitmap shapes:

Align top of bitmap shape with silicon direction, and later the silicon direction. Use KOH as the etchant.

Compare and contrast your results.


Homework

16

Examples of Bulk Micromachining

A Microthermal Sensor

Using a standard CMOS process, selectively exposed p-silicon (substrate) is etched, resulting in single-crystal silicon islands that are suspended above etched pits by oxide/aluminum members.

This approach allows for thermal isolation of entire active circuits or any subset of them, based on components that can be fabricated in an n-type well.

Demonstration of very highly thermally isolated (60,000 degrees/Watt) single-crystal silicon islands

Demonstration of digitally controlled, fully integrated thermal (Pirani-type) vacuum sensor.


17

Dry Etching:

Gas Phase Silicon Isotropic Etching

Utilizes a gas that has high selectivity. That is, it reacts well with the desired species, but does not react with mask material.

BrF3XeF2

XeF2 shows a very high selectivity of silicon versus photoresist, SiO2, silicon nitride, Al, Cr, and TiN. The XeF2 etch selectivity to silicon nitride is better than 100:1. The selectivity to silicon dioxide is reported to be better than 10,000:1


18



100um line width Cantilever100um line width Cantilever 60um line width Cantilever60um line width Cantilever

30 um Deep Etch (Gas Phase Iso Etch)

[Image from Chang Liu]

100um line width Cantilever100um line width Cantilever





19



Illustration of High-Q

Micro-toroidal Resonator

[www.vahala.caltech.edu]

SEM of High-Q Micro-toroidal Resonator

[www.vahala.caltech.edu]

20

Dry Etching:

DRIE (Deep Reactive Ion Etching)


High aspect ratio (depth/width ratio)

Large depth

Fast etch speed

Can use convenient mask layers (silicon oxide, photoresist)

Beams Fabricated with DRIE [Image from Liu Chang]


The BOSCH DRIE Micromachining Process

Step 1: Start with Masked

Silicon Substrate

Step 2: Etch Increment Depth Step 3: Stop, Passivate the Fresh

Etched Surface


The BOSCH DRIE Micromachining Process

Step 4: Repeat Etch Step 5: Repeat Deposition Step 6,7, Etc....:

-Repeat Etch by Increment Depth,

-Stop, Passivate the Fresh

Etched Surface

SEM of Micro-Part Produced by DRIE [www.bosch-sensortec.com]


Surface Micromachining is based on the successive deposition and etching of thin films of material such as silicon nitride, polysilicon, silicon oxide and gold.

There are two different ways to do this:

(A) Use a Standard Foundary Service:

Multi-User MEMS Processes (MUMPs)

Surface Micromachining with Planarization,(MEMX, formerly SUMMiT)

(B) Use a Custom Fabrication Laboratory:

NanoFab at the University of Alberta [http://www.nanofab.ualberta.ca/]

Or others...

Surface Micromachining

24


Multi-User MEMS Processes (MUMPs)MUMPs fabrication process to create a microgripper tip.

Substrate

Nitride

0.6 um thick, by CVD

Poly 0 0.5 um thick, LPCVD Oxide 1 2.0 um thick PSG, by LPCVD


25



Substrate

NitridePoly 0

Oxide 1

Poly 1 2.0 um thick, by LPCVD


26



Substrate

NitridePoly 0

Oxide 1

Poly 1Oxide 2 0.75 um thick PSG, by LPCVD Poly 2 1.5 um thick, by LPCVD


27



Substrate

NitridePoly 0

Oxide 1

Poly 1Oxide 2

Poly 2Metal

0.5 um thick Gold, by

lift-off patterning (requires no etch)


28



Oxide Release process to free microstructures from substrate.

Etch away Oxide 1 and Oxide 2 with HF.

Substrate

NitridePoly 0

Poly 1

Oxide 1

Oxide 2

Poly 2Metal


29



Oxide Release process to free microstructures from substrate.

Released Structure!

Substrate

NitridePoly 0

Poly 1

Poly 2Metal


30



Section A Poly 2

Gripper Tip

Poly 1 Lift

Structure

Poly 1

Poly 2

Substrate

Substrate

2 m

2.75 m

Poly 1

Poly 2

Oxide 1

Poly 2

Gripper TipGripper Tip

Upper Level

Poly 1 Lift Structure

Anchor 1

Oxide 2

Microgripper tip fabricated with MUMPs

[N. Dechev]


31

Advanced Surface Micromachining:

SUMMiT ProcessThe SUMMiT (Sandia Ultra-planar, Multi-level MEMS Technology) process was developed by Sandia National Laboratories.

It is a multi-layer surface micromachining process, very much like MUMPs. However, it has one unique feature, which is called Planarization.

Planarization allows for the flattening out of a conformaly deposited layer of material. This allows the SUMMiT process to create micro-mechanisms and devices that are not possible to do with MUMPs.

A series of images of SUMMiT are available at: http://mems.sandia.gov/scripts/images.asp

Movies are also available at: http://www.sandia.gov/mstc/technologies/micromachines/movies/index.html


32

SUMMiT 4-Layer Process


3D fold-out micro-mirror, actuated by comb-drive and gear train set

[Sandia National Laboratories]

Gear connected to X and Y direction actuator beams


33

SUMMiT 5-Layer Process


Pinion gear connected to X and Y direction actuator beams,

driving a linear rack (i.e. rack and pinion)


Multi-level gear train [Sandia National Laboratories]

34

Equipment used for Surface Micromachining

LPCVD - Low Pressure Chemical Vapour Deposition

LPCVD Chamber [Image from Liu Chang]


Chip Carrier Sliding into Bottle

[Image from Liu Chang]

35

LPCVD Process

Temperature range 500-800 degrees

Pressure range 200 - 400 mtorr (1 torr = 1/760 ATM)

Gas mixture: typically 2-3 gas mixture

Particle free environment to prevent defects on surface (pin holes)


Internal Operation of LPCVD Chamber Bottle

[Image from Liu Chang]

36

Examples of LPCVD Recipes for Depositing Various

MEMS MaterialsPolycrystalline silicon

Polysilicon is deposited at around 580-620 oC and can withstand more than 1000 oC temperature. The deposition is conducted by decomposing silane (SiH4) under high temperature and vacuum (SiH4> Si+2H2).

Polysilicon is used extensively in IC - transistor gate

Silicon nitride

Silicon nitride is deposited at around 800 oC by reacting silane (SiH4) or dichlorosilane (SiCl2H2) with ammonia (NH3) - SiH4+NH3 -> SixNy+ H.

Silicon nitride is widely used as an electrical isolation layer

Silicon oxide

The PSG is known to reflow under high temperature (e.g. above 900 oC); it is deposited at a relatively low temperature, e.g. 500 oC by reacting silane with oxygen (SiH4+O2-> SiO2+2H2). PSG can be deposited on top of Al metallization.

Silicon oxide is used for sealing IC circuits after processing.

The etch rate of HF on oxide is a function of doping concentration.


37

Other Surface Micromachined Layers

Structural layers

- evaporated and sputtered metals such as Gold, Copper

- electroplated metal (such as NiFe)

- plastic material (CVD plastic)

- silicon (such as epitaxy silicon or top silicon in SOI wafer)

Sacrificial layers

- photoresist, polyimide, and other organic materials

- copper

- copper can be electroplated or evaporated, and is relatively inexpensive.

- Oxide by plasma enhanced chemical vapor deposition (PECVD)

- PECVD is done at lower temperature, with lower quality. It is generally undoped.

- Thermally grown oxide

- relatively low etch rate in HF.

- Silicon or polysilicon

- removed by gas phase silicon etching


38

Etching of Surface Micromachined Layers

Selectivity

- etch rate on structural layer/etch rate on sacrificial layer must be high.

Etch rate

- rapid etching rate on sacrificial layer to reduce etching time

Deposition temperature

- in certain applications, it is required that the overall processing temperature be low (e.g. integration with CMOS, integration with biological materials)

Intrinsic stress of structural layer

- to remain flat after release, the structural layer must have low stress

Surface smoothness

- important for optical applications


Documents

MECH466 Lecture 16