MC9S12XHZ-Family rev4.1 - nxp.com · • Flexible assignment of interrupt sources to each interrupt level ... • Programmable sample time • Left/right, ... (BDM) • Background

© Freescale Semiconductor, Inc., 2006. All rights reserved.

Freescale SemiconductorProduct Brief

S12XHZ512PBRev. 4.1, 4-Jan-2007

MC9S12XHZ512Also covers MC9S12XHZ384 and MC9S12XHZ256

16-bit S12X Microcontroller with LCD and Stepper Motor Drivers

Introduction

Targeted at automotive instrumentation applications, the MC9S12XHZ512 microcontroller unit (MCU) is a fully pin-compatible extension to the existing MC9S12HZ-Family of microcontrollers. It offers not only a larger memory than the existing S12-based family but also incorporates all the architectural benefits of the new S12X-based family to deliver significantly higher performance. The MC9S12XHZ512 retains the low cost, power consumption, EMC and code-size efficiency advantages currently associated with the MC9S12HZ-Family products.

Based around S12X core, the MC9S12XHZ512 runs 16-bit wide accesses without wait states for all peripherals and memories. The MC9S12XHZ512 also features a new flexible interrupt handler, which allows multilevel nested interrupts.

The MC9S12XHZ512 features the performance boosting XGATE co-processor. The XGATE is programmable in “C” language and runs at twice the bus frequency of the S12. Its instruction set is optimized for data movement, logic and bit manipulation instructions. Any peripheral module can be serviced by the XGATE.

The MC9S12XHZ512 contains 512K bytes of Freescale Semiconductor’s industry leading, full automotive qualified Split-Gate Flash memory, with 4K bytes of additional integrated data EEPROM and 32K bytes of static RAM.

MC9S12XHZ512, Rev. 4.1

2 Freescale Semiconductor

Features

The MC9S12XHZ512 features a 32x4 liquid crystal display (LCD) controller/driver and a motor pulse width modulator (MC) consisting of up to 24 high current outputs suited to drive six stepper motors with stall detectors (SSD) to simultaneously calibrate the pointer reset position of each motor. It also features two MSCAN modules, each with a FIFO receiver buffer arrangement, and input filters optimized for Gateway applications handling numerous message identifiers.

In addition, the MC9S12XHZ512 is composed of standard on-chip peripherals including two asynchronous serial communications interfaces (SCI0 and SCI1), one serial peripheral interface (SPI), two IIC-bus interface (IIC0 and IIC1), an 8-channel 16-bit enhanced capture timer (ECT), a 16-channel, 10-bit analog-to-digital converter (ADC), and one 8-channel pulse width modulator (PWM).

The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. The new fast-exit from STOP mode feature can further improve system power consumption. In addition to the I/O ports available in each module, 8 general purpose I/O ports are available with interrupt capability allowing wake-up from STOP or WAIT mode.

The MC9S12XHZ512 is available in 112-pin LQFP and 144-pin LQFP packages. The 144-pin LQFP package option provides a full 16-bit wide non-multiplexed external bus interface.

Features

Features of the MC9S12XHZ512 are listed here. Please see Table 1 for the features that are available on the different family members.

16-Bit CPU12X

• Upward compatible with MC9S12 instruction set• Enhanced indexed addressing• Additional (superset) instructions to improve 32-bit calculations and

semaphore handling• Access large data segments independent of PPAGE

Enhanced InterruptModule

• Eight levels of nested interrupt• Flexible assignment of interrupt sources to each interrupt level• One non-maskable high priority interrupt (XIRQ)• Wakeup interrupt inputs (IRQ and XIRQ)

XGATE

• Programmable, high performance I/O co-processor - up to 80 MIPS RISC performance

• Transfers data to or from all peripherals and RAM without CPU intervention or CPU wait states

• Performs simple logical, shifts, arithmetic, and bit operations on data• Enables FullCAN capability when used in conjunction with MSCAN• Full LIN master or slave capability when used in conjunction with SCI.• Triggers from any hardware module as well as from the CPU

Features


Freescale Semiconductor 3

Memory Options

• 512K, 384K, 256K byte FLASH– Erase sector size 1024 bytes– Automated program and erase algorithm– Fast sector erase and word program operation– 2-stage command pipeline for faster multi-word program times– Sector erase abort feature for critical interrupt response– Protection scheme to prevent accidental program or erase– Security option to prevent unauthorized access– Code integrity check using built-in data compression– Sense-amp margin level setting for reads

• 4K byte EEPROM– Small erase sector 4 bytes– Automated program and erase algorithm– Fast sector erase and word program operation– 2-stage command pipeline for faster multi-word program times– Sector erase abort feature for critical interrupt response– Protection scheme to prevent accidental program or erase

• 32K, 28K, 16K byte RAM

Oscillator (OSC_LCP)

• Loop Control Pierce oscillator utilizing a 0.5Mhz to 16Mhz crystal• Option for full-swing Pierce without internal feedback resistor utilizing

a 0.5Mhz to 40Mhz crystal• Current gain control on amplitude output

– Signal with low harmonic distortion– Low power– Good noise immunity– Eliminates need for external current limiting resistor

• Transconductance sized for optimum start-up margin for typical crystals

• Clock monitor

Clock and ResetGenerator (CRG)

• Phase-locked-loop clock frequency multiplier– Reference divider– Automatic bandwidth control mode for low-jitter operation– Automatic frequency lock detector

• Fast wake up from STOP in self clock mode for power saving and immediate program execution

• Computer Operating Properly (COP) watchdog with optional safety window to initialize time-out counter

• Real Time Interrupt for task scheduling purposes or cyclic wake-up from low power modes

• System reset generation



Features

Liquid Crystal Display(LCD)

• 32 frontplanes and 4 backplanes• 5 modes of operation allow for different display sizes to meet

application requirements• Programmable frame clock generator and bias voltage level

Motor Controller (MC)

• 24 high current drivers suited for PWM motor control• Each PWM channel switchable between two drivers in an H-bridge

configuration• Support for sine and cosine drive• 11-bit resolution with selectable dithering function• Left, right or center aligned outputs• Slew rate control

Stepper Stall Detector(SSD0, SSD1,SSD2, SSD3,SSD4, SSD5)

• Flexible full step and polarity set up to return the pointer to its reset position in clockwise or counter clockwise direction.

• Integrator/Sigma Delta converter circuit to measure the induced voltage by the back EMF of non-powered coil during full step (only one of the two motor coils is powered) operation.

• 16-Bit Down Counter to monitor blanking and integration time to support stepper motors with different gear ratios.

• 16-Bit accumulator register to read integration value, compare to a threshold at the end of integration time, and decide if the motor is stalled under this value or moving above this value.

Analog-to-DigitalConverter (ADC)

• 8-bit or 10-bit resolution• Multiplexer for 16 analog input channels• 7µs, 10-bit single conversion time• Programmable sample time• Left/right, signed/unsigned result data• Continuous conversion mode• Multiple channel scans• External and internal conversion trigger capability

Enhanced CaptureTimer (ECT)

• Eight 16-bit channels for input capture or output compare• One 16-bit free-running counter with 8-bit precision prescaler• One 16-bit modulus down counter with 8-bit precision prescaler• Four 8-bit or two 16-bit pulse accumulators• Four channels have enhanced input capture capabilities:

– Delay counter for noise immunity– 16-bit capture buffer– 8-bit pulse accumulator buffer

Features



Periodic InterruptTimer (PIT)

• Four channel x 24-bit modulus down-count timers– Timeout interrupt– Timeout peripheral trigger

• Start of timers can be aligned

Pulse WidthModulator (PWM)

• Eight 8-bit or four 16-bit independent channels• Programmable period and duty cycle per channel• Center-aligned or left-aligned outputs• Programmable clock select and with a wide frequency range

Multi-scalableController

Area Networks(MSCAN0, MSCAN1)

• CAN 2.0 A, B software compatible– Standard and extended data frames– 0 - 8 bytes data length– Programmable bit rate up to 1 Mbps

• Five receive buffers with FIFO storage scheme• Three transmit buffers with internal prioritization• Flexible identifier acceptance filter programmable as:

– 2 x 32-bit– 4 x 16-bit– 8 x 8-bit

• Wake-up with integrated low pass filter option• Loop back for self test• Listen-only mode to monitor CAN bus• Bus-off recovery by software intervention or automatically• 16-bit time stamp of transmitted/received messages• FullCAN capability when used in conjuntion with XGATE

Serial CommunicationInterfaces (SCI0, SCI1)

• Full-duplex or single wire operation• Standard mark/space non-return-to-zero (NRZ) format• Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with

programmable pulse widths• 13-bit baud rate selection• Programmable character length• Programmable polarity for transmitter and receiver• Receive wakeup on active edge• Break detect and transmit collision detect supporting LIN



Features

Serial PeripheralInterface (SPI)

• Full-duplex or single-wire bidirectional• Double-buffered transmit and receive• Master or Slave mode• MSB-first or LSB-first shifting• Serial clock phase and polarity options

Inter-IC Bus(IIC0, IIC1)

• Compatible with I2C Bus standard• Supports 400 kbps• Multi-master operation• Software programmable for one of 256 different serial clock

frequencies• Software selectable acknowledge bit• Interrupt driven byte-by-byte data transfer• Arbitration lost interrupt with automatic switch from master to slave

mode• 7-bit or 10-bit calling address identication interrupt• Bus busy detection• Supports General Call address

Background Debug(BDM)

• Background debug controller (BDC) with single-wire interface– Non-intrusive memory access commands– Supports in-circuit programming of on-chip non-volatile memory– Supports security

Debugger (XDBG)

• Four comparators A, B, C and D– Each can monitor CPU or XGATE busses– A and C compares 23-bit address bus and 16-bit data bus with

mask register– B and D compares 23-bit address bus only– Three modes: simple address/data match, inside address range

or outside address range• 64 x 64-bit circular trace buffer to capture change-of-flow addresses

or address and data of every access• Tag-type or force-type hardware breakpoint requests

System Protection• Power-on reset (POR)• Illegal opcode and illegal address detection with reset• Low-voltage detection with interrupt or reset

Features



• Pin out explanations:– A/D is the number of A/D channels.– PWM is the number of PWM channels.– ECT is the number of ECT channels.– LCD denotes the number of front planes times the number of back planes.– Motor denotes the number of high current drive pins / number of stepper motors which can be

driven– SSD denotes whether this device features a Stepper Stall Detection Circuit– Versions with one SCI will use SCI0– Versions with one CAN will use CAN0– Versions with one IIC will use IIC0– I/O is the sum of ports capable to act as digital input or output.

Input/Output

• 115 general-purpose input/output (I/O) pins and 2 input-only pins• Hysteresis and configurable pull up/pull down device on all input pins• Configurable drive strength on all output pins• Eight interrupt pins with digital filtering and rising or falling edge

trigger

Package Options• 144-pin low-profile quad flat-pack (LQFP)• 112-pin low-profile quad flat-pack (LQFP)

Operating Conditions

• Ambient temperature range –40 to 125°C• Temperature options:

– –40 to 85°C– –40 to 105°C– –40 to 125°C

• Supply voltage 4.5 to 5.5 V• 40 MHz maximum CPU bus frequency in single chip mode• 80 Mhz maximum XGATE bus frequency

Table 1 Options of MC9S12XHZ-FamilyDevice Package Flash RAM EEPROM XGATE CAN SCI SPI IIC A/D ECT LCD PWM Motor SSD KWU EBI I/O

9S12XHZ512144 LQFP

512K 32K 4K yes 2 2 1 2 16 8 32x48 24/6 6

8Yes 117

112 LQFP 6 16/4 4 No 85

9S12XHZ384144 LQFP

384K 28K 4K yes 2 2 1 2 16 8 32x48 24/6 6

8Yes 117

112 LQFP 6 16/4 4 No 85

9S12XHZ256144 LQFP

256K 16K 4K yes 2 2 1 2 16 8 32x48 24/6 6

8Yes 117

112 LQFP 6 16/4 4 No 85



Block Diagram

Block Diagram

Figure 1. MC9S12XHZ512 Block Diagram

EXTALXTAL

BKGD

XIRQ

PLL

XFC

IRQ

ECLK

PA4PA3PA2PA1PA0

PA7PA6PA5

TEST

PB4

PB0

PB7PB6

FP4FP3FP2FP1FP0

FP7FP6

PE4PE5PE6

PE0PE1

MISOMOSI

PS4PS5

PS0PS1

PK3

PK0PK1

SCKSS

PS6PS7

SPI

RXCAN0TXCAN0

PM2PM3

DD

RA

DD

RB

PTA

PTB

DD

RE

PTE

PTK

DD

RK

PTS

DD

RS

PTM

DD

RM

PK2

FP12FP11FP10FP9FP8

FP15FP14

BP0BP1BP2BP3

PL3PL2PL1PL0

DDR

LPT

L FP19FP18FP17FP16

FP22

FP21FP20

VLCDVLCD

LCD

Driv

er

CAN0

MODB/TAGHIMODA/TAGLO/RE

RESET

VDDPLLVSSPLL

Clock andResetGenerationModule

FP13

PB5

PB3PB2PB1

FP5

ADDR16/IQSTAT0ADDR17/IQSTAT1ADDR18/IQSTAT2ADDR19/IQSTAT3

ADDR0ADDR1ADDR2ADDR3ADDR4ADDR5ADDR6ADDR7ADDR8ADDR9ADDR10ADDR11ADDR12ADDR13ADDR14ADDR15

FP24FP25FP26FP27

AN2

AN6

AN0

AN7

AN1

AN3AN4AN5

PAD3PAD4PAD5PAD6PAD7

PAD0PAD1PAD2

VRHVRL

VDDAVSSAAnalog to

DigitalConverter

DD

RA

D

VRHVRL

VDDAVSSA

512K, 284K, 256K Bytes Flash EEPROM4k Bytes EEPROM

32K, 28K, 16K Bytes RAM

EWAIT/ROMCTL

VDDRVDD1

VSS1,2Voltage Regulator

EnahancedCaptureTimer

PL7PL6PL5PL4

FP31FP30FP29FP28

Single-Wire BackgroundDebug Module

RXCAN1TXCAN1

PM4PM5CAN1

M0C0MM0C0P

PU0PU1

PTU

DD

RU

PWM0SSD0 M0C1M

M0C1PPU2PU3PWM1

M1C0MM1C0P

PU4PU5PWM2

SSD1 M1C1MM1C1P

PU6PU7PWM3

PulseWidthModulator

PW2

PW0PW1

PW3PW4PW5

PP3PP4PP5

PP0PP1PP2

PTP

DD

RP

RXD0TXD0SCI0

AN10

AN14

AN8

AN15

AN9

AN11AN12AN13

AN10

AN14

AN8

AN15

AN9

AN11AN12AN13

KWAD2

KWAD6

KWAD0

KWAD7

KWAD1

KWAD3KWAD4KWAD5

M0COSMM0COSPM0SINMM0SINP


PTA

D

M2C0MM2C0P

PV0PV1

PTV

DD

RV

PWM4SSD2 M2C1M

M2C1PPV2PV3PWM5

M3C0MM3C0P

PV4PV5PWM6

SSD3 M3C1MM3C1P

PV6PV7PWM7



RXD1TXD1SCI1 PS2

PS3

SDA0SCL0

PM1

IIC0

PP6PP7

A/D Converter &

VDDAVSSA

PLL Supply 2.5VVDDPLLVSSPLL

I/O Supply 5VVDDX1,2VSSX1,2

Internal 2.5VVDD1VSS1,2

Voltage Regulator 5VVDDR

Voltage Regulator 5V

PK7 FP23

PC4

PC0

PC7PC6

DD

RC

PTC

PC5

PC3PC2PC1

DATA8DATA9DATA10DATA11DATA12DATA13DATA14DATA15

PD4

PD0

PD7PD6

DD

RD

PTD

PD5

PD3PD2PD1

DATA0DATA1DATA2DATA3DATA4DATA5DATA6DATA7

PE7

PE2PE3

XCLKS/ECLKX2

LSTRB/LDS/EROMCTLRW/WE

PT4PT3PT2PT1PT0

PT7PT6PT5 D

DR

TP

TT

IOC0IOC1IOC2IOC3IOC4IOC5IOC6IOC7

Non

-Mul

tiple

xed

Ext

erna

l Bus

Inte

rface

SDA1SCL1IIC1

SDA0SCL0SDA1SCL1

CPU12X

Periodic InterruptCOP WatchdogClock Monitor

Breakpoints

XGATEPeripheral 4-Channel

Motor SuppliesVDDM1,2,3VSSM1,2,3

M4C0MM4C0P

PW0PW1

PTW

DD

RW

PWM8SSD4 M4C1M

M4C1PPW2PW3PWM9

M5C0MM5C0P

PW4PW5PWM10

SSD5 M5C1MM5C1P

PW6PW7PWM11



Pins and signals shown in BOLDare not available in the 112 QFP package

Co-Processor ProgrammableInterrupt Timer (PIT)for internal timebases

EnhancedMultilevelInterruptModule

PK4 ADDR20/ACC0PK5 ADDR21/ACC1PK6 ADDR22/ACC2

CS1

CS3

CS0CS2

PW6PW7

Mod

ule-

to-P

ort-R

outin

g

Pin Assignments



Pin Assignments

Figure 2. 144-Pin Package Signal Assignments

FP28/AN12/PL4FP29AN13//PL5FP30/AN14//PL6FP31/AN15/PL7

M4C0M/M4COSM/PW0M4C0P/M4COSP/PW1M4C1M/M4SINM/PW2M4C1P/M4SINP/PW3

VDDM1VSSM1

M0C0M/M0COSM/PU0M0C0P/M0COSP/PU1M0C1M/M0SINM/PU2M0C1P/M0SINP/PU3


VDDM2VSSM2

M2C0M/M2COSM/PV0M2C0P/M2COSP/PV1M2C1M/M2SINM/PV2M2C1P/M2SINP/PV3


VDDM3VSSM3

M5C0M/M5COSM/PW4M5C0P/M5COSP/PW5M5C1M/M5SINM/PW6M5C1P/M5SINP/PW7

SCL0/PWM5/PP5SDA0/PWM4/PP4

PW

M3/

PP

3R

XD

1/P

WM

2/P

P2

TXD

1/P

WM

0/P

P0

PW

M1/

PP

1C

S0/S

DA

1/PW

M6/

PP6

CS2

/SC

L1/P

WM

7/PP

7A

CC

0/A

DD

R20

/PK

4A

CC

1/A

DD

R21

/PK

5R

XD

0/P

S0

TXD

0/P

S1

CS3

/RXD

1/PS

2TX

D1/

PS3

VSS

2V

DD

RV

DD

X2

VSS

X2

MO

DC

/BK

GD

RE

SET

VD

DP

LLX

FCV

SSP

LLE

XTA

LX

TAL

TES

TA

CC

2/A

DD

R22

/PK

6C

S1/P

M1

RX

CA

N0/

PM

2TX

CA

N0/

PM

3R

XC

AN

1/P

M4

TXC

AN

1/P

M5

TAG

LO/R

E/M

OD

A/P

E5

MIS

O/P

S4

MO

SI/P

S5

SC

K/P

S6

SS

/PS

7IR

Q/P

E1

PB5/ADDR5/FP5PB4/ADDR4/FP4PB3/ADDR3/FP3PB2/ADDR2/FP2PB1/ADDR1/FP1PB0/ADDR0/FP0PK0/ADDR16/BP0PK1/ADDR17/BP1PK2/ADDR18/BP2PK3/ADDR19/BP3VLCDVSS1VDD1PD7/DATA7PD6/DATA6PD5/DATA5PD4/DATA4PD3/DATA3PD2/DATA2PD1/DATA1PD0/DATA0PAD7/KWAD7/AN7PAD6/KWAD6/AN6PAD5/KWAD5/AN5PAD4/KWAD4/AN4PAD3/KWAD3/AN3PAD2/KWAD2/AN2PAD1/KWAD1/AN1PAD0/KWAD0/AN0VDDAVRHVRLVSSAPE0/XIRQPE4/ECLKPE6/MODB/TAGHI

PT7/

IOC

7/S

CL1

PT6/

IOC

6/S

DA1

PT5/

IOC

5/S

CL0

PT4/

IOC

4/S

DA0

PT3

/IOC

3/FP

27P

T2/IO

C2/

FP26

PT1

/IOC

1/FP

25P

T0/IO

C0/

FP24

PC7/

DA

T15

PC6/

DA

T14

PC5/

DA

T13

PC4/

DA

T12

VSS

X1VD

DX

1PK

7/EW

AIT

/RO

MC

TL/F

P23

PE7/

ECLK

X2/X

CLK

S/F

P22

PE3/

LSTR

B/L

DS/

ERO

MC

TL/F

P21

PE2/

RW

/WE/

FP20

PC3/

DA

T11

PC2/

DA

T10

PC1/

DA

T9PC

0/D

AT8

PL3/

AN

11/F

P19

PL2/

AN

10/F

P18

PL1/

AN

9/FP

17PL

0/A

N8/

FP16

PA7/

AD

DR

15/F

P15

PA6/

AD

DR

14/F

P14

PA5/

AD

DR

13/F

P13

PA4/

AD

DR

12/F

P12

PA3/

AD

DR

11/F

P11

PA2/

AD

DR

10/F

P10

PA1/

AD

DR

9/FP

9PA

0/A

DD

R8/

FP8

PB7/

AD

DR

7/FP

7PB

6/A

DD

R6/

FP6

144 LQFP

Pins shown in BOLD are not available in the 112 QFP package

123456789101112131415161718192021222324252627282930313233343536

37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

108107106105104103102101100999897969594939291908988878685848382818079787776757473

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109



Figure 3. 112-Pin Package Signal Assignments

12345678910111213141516171819202122232425262728

112

111

110

109

108

107

106

105

104

103

102

101

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85

29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

112 LQFP

84838281807978777675747372717069686766656463626160595857

FP28/AN12/PL4FP29AN13//PL5

FP30/AN14//PL6FP31/AN15/PL7

VDDM1VSSM1



VDDM2VSSM2



VDDM3VSSM3

SCL0/PWM5/PP5SDA0/PWM4/PP4

PT7

/IOC

7/SC

L1P

T6/IO

C6/

SDA

1P

T5/IO

C5/

SCL0

PT4

/IOC

4/SD

A0

PT3

/IOC

3/FP

27P

T2/IO

C2/

FP26

PT1

/IOC

1/FP

25P

T0/IO

C0/

FP24

VSS

X1

VD

DX1

PK7

/FP

23P

E7/X

CLK

S/F

P22

PE3

/FP

21P

E2/F

P20

PL3

/AN

11/F

P19

PL2

/AN

10/F

P18

PL1

/AN

9/FP

17P

L0/A

N8/

FP16

PA7

/FP

15P

A6/F

P14

PA5

/FP

13P

A4/F

P12

PA3

/FP

11P

A2/F

P10

PA1

/FP

9P

A0/F

P8

PB7

/FP

7P

B6/F

P6

PB5/FP5PB4/FP4PB3/FP3PB2/FP2PB1/FP1PB0/FP0PK0/BP0PK1/BP1PK2/BP2PK3/BP3VLCDVSS1VDD1PAD7/KWAD7/AN7PAD6/KWAD6/AN6PAD5/KWAD5/AN5PAD4/KWAD4/AN4PAD3/KWAD3/AN3PAD2/KWAD2/AN2PAD1/KWAD1/AN1PAD0/KWAD0/AN0VDDAVRHVRLVSSAPE0/XIRQPE4/ECLKPE6

PWM

3/PP

3R

XD1/

PWM

2/PP

2TX

D1/

PWM

0/PP

0PW

M1/

PP1

RX

D0/

PS0

TXD

0/PS

1VS

S2

VD

DR

VDD

X2

VSS

X2

MO

DC

/BK

GD

RES

ET

VD

DPL

LX

FCVS

SPLL

EXT

AL

XTA

LTE

ST

RX

CAN

0/P

M2

TXC

AN0/

PM

3R

XCAN

1/PM

4TX

CAN

1/PM

5PE

5M

ISO

/PS

4M

OS

I/PS

5SC

K/PS

6SS

/PS

7IR

Q/P

E1



Table 2. Port and Peripheral Availability by Package Option

Port 144 LQFP 112 LQFPPort AD pins 8 8

Port A pins 8 8

Port B pins 8 8

Port C pins 8 0

Port D pins 8 0

Port E pins incl. IRQ/XIRQ input only 8 8

Port K pins 5 5

Port L pins 8 8

Port M pins 8 4

Port P pins 8 6

Port S pins 8 6

Port T pins 8 8

Port U pins 8 8

Port V pins 8 8

Port W pins 8 0

Sum of Ports 117 85

Table 3. Peripheral–Port Cross Reference(1)

NOTES:1. X denotes the reset condition and O denotes a possible rerouting under software

control

CA

N0

CA

N1

SCI0

SCI1

SPI

IIC0

IIC1

PM3:2 X

PM5:4 X

PS1:0 X

PP0,PP2 X

PP5:4 X

PP7:6 X

PS3:2 O

PS7:4 X

PT5:4 O

PT7:6 O



Memory Maps

Memory Maps

Figure 4 shows the CPU & BDM local address translation to the global memory map. It indicates also the location of the internal resources in the memory map.

Table 4 Device Internal Resources

Figure 5 shows XGATE local address translation to the global memory map. It indicates also the location of used internal resources in the memory map.

Table 5 XGATE Resources

Device RAMSIZE / RAM_LOW

EEPROMSIZE / EEPROM_LOW

FLASHSIZE0 / FLASH_LOW

FLASHSIZE1 / FLASH_HIGH

MC9S12XHZ512 32K / 0x0F_8000 4K / 0x13_F000 256K / 0x7B_FFFF 256K / 0x7C_0000

MC9S12XHZ384 28K / 0x0F_9000 4K / 0x13_F000 128K / 0x79_FFFF 256K / 0x7C_0000

MC9S12XHZ256 16K / 0x0F_C000 4K / 0x13_F000 128K / 0x79_FFFF 128K / 0x7E_0000

Device XGRAMSIZE / XGRAM_LOW

XGFLASHSIZE / XGFLASH_HIGH

MC9S12XHZ512 32K / 0x0F_8000 30K / 0x78_7FFF

MC9S12XHZ384 28K / 0x0F_9000

MC9S12XHZ256 16K / 0x0F_C000

Memory Maps



Figure 4. S12X CPU & BDM Global Address Mapping

0x7F_FFFF

0x00_0000

0x13_FFFF

0x0F_FFFF

EEPROM

RAM

0x00_07FF

EPAGE

RPAGE

PPAGE 0x3F_FFFF

CPU and BDMLocal Memory Map

Global Memory Map

FLAS

HSI

ZEE

EP

RO

MSI

ZER

AMS

IZE

UnimplementedEEPROM

UnimplementedFLASH

CS

3C

S2

CS

1C

S0

0x1F_FFFF

CS

20xFFFF Reset Vectors

0xC000

0x8000

Unpaged

0x4000

0x1000

0x0000

16K FLASH window

0x0C00

0x2000

0x0800

8K RAM

4K RAM window

1K EEPROM

2K REGISTERS

1K EEPROM window

16K FLASH

Unpaged 16K FLASH

2K REGISTERS

UnimplementedRAM

ExternalSpace

RAM_LOW

EEPROM_LOW

0x78_0000

FLASH1

FLASH0_LOW

FLASH1_HIGH

FLASH0

UnimplementedFLASH C

S0

FLA

SH

SIZE

0FL

AS

HS

IZE

1



Memory Maps

Figure 5. XGATE Global Address Mapping

0x7F_FFFF

0x00_0000

0x0F_FFFF

0xFFFF

0x0000

Registers

FLASH

RAM

0x0800

Registers0x00_07FF

XGATELocal Memory Map

Global Memory Map

FLA

SH

SIZ

E

XG

RA

MSI

ZE

RA

MS

IZE

0x78_0800FLASH

RAM

XGRAM_LOW

XGFLASH_HIGH

Mechanical Package Dimensions




Figure 6. 144-pin LQFP Mechanical Dimensions (case no. 918-03)

N0.20 T L-M

144

GAGE PLANE

73

109

37

SEATING

1081

36

72

PLANE

4X 4X 36 TIPS

PIN 1 IDENT

VIEW Y

B

B1 V1

A1S1

V

P

G

AS

0.1C2θ

VIEW AB

J1

J1

140X

4X

VIEW Y

PLATING

F AAJ

DBASEMETAL

SECTION J1-J1(ROTATED 90 )

144 PL°

N0.08 M T L-M

θ

DIMA

MIN MAX20.00 BSC

MILLIMETERS

A1 10.00 BSCB 20.00 BSCB1 10.00 BSCC 1.40 1.60C1 0.05 0.15C2 1.35 1.45D 0.17 0.27E 0.45 0.75F 0.17 0.23G 0.50 BSCJ 0.09 0.20K 0.50 REFP 0.25 BSC

R1 0.13 0.20R2 0.13 0.20S 22.00 BSCS1 11.00 BSCV 22.00 BSCV1 11.00 BSCY 0.25 REFZ 1.00 REF

AA 0.09 0.16θ 0

θ 0 7 θ 11 13

12

NOTES:1. DIMENSIONS AND TOLERANCING PER

ASME Y14.5M, 1994.2. DIMENSIONS IN MILLIMETERS.3. DATUMS L, M, N TO BE DETERMINED AT

THE SEATING PLANE, DATUM T.4. DIMENSIONS S AND V TO BE DETERMINED

AT SEATING PLANE, DATUM T.5. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H.

6. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE

°°°

°°

0.05

CL

(Z)

R2

E

C2

(Y)

R1

(K)C1

1θ

0.25

VIEW AB

N0.20 T L-M

ML

N

2θ

T

T 144X

X




Figure 7. 112-pin LQFP Mechanical Dimensions (case no. 987)

DIMA

MIN MAX20.000 BSC

MILLIMETERS

A1 10.000 BSCB 20.000 BSCB1 10.000 BSCC --- 1.600C1 0.050 0.150C2 1.350 1.450D 0.270 0.370E 0.450 0.750F 0.270 0.330G 0.650 BSCJ 0.090 0.170K 0.500 REFP 0.325 BSC

R1 0.100 0.200R2 0.100 0.200S 22.000 BSCS1 11.000 BSCV 22.000 BSCV1 11.000 BSCY 0.250 REFZ 1.000 REF

AA 0.090 0.160θ

θθθ 11 °

11 °13 °

7 °

13 °

VIEW Y

L-M0.20 NT4X 4X 28 TIPS

PIN 1IDENT

1

112 85

84

28 57

29 56

B V

V1B1

A1

S1A

S

VIEW AB

0.10

3

CC2

θ

2θ0.050

SEATINGPLANE

GAGE PLANE

1θ

θ

VIEW AB

C1

(Z)(Y)

E(K)

R2

R1 0.25

J1

VIEW Y

J1

P

G108X

4X

SECTION J1-J1

BASE

ROTATED 90 COUNTERCLOCKWISE°

METAL

J AA

FD

L-MM0.13 NT

123

CL

L-M0.20 NT

L

N

M

T

T

112X

XX=L, M OR N

R

R

NOTES:1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.2. DIMENSIONS IN MILLIMETERS.3. DATUMS L, M AND N TO BE DETERMINED AT

SEATING PLANE, DATUM T.4. DIMENSIONS S AND V TO BE DETERMINED AT

SEATING PLANE, DATUM T.5. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION. ALLOWABLE

8 ° 3 ° 0 °




S12XHZ512PBRev. 4.1, 4-Jan-2007

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MC9S12XHZ-Family rev4.1 - nxp.com · • Flexible assignment of interrupt sources to each interrupt level ... • Programmable sample time • Left/right, ... (BDM) • Background