Manual

A Student Introduction

to Cadence Design System

Torie Hadel

[email protected]

Electrical and Computer Engineering

Colorado State University

April 2012

Note: This manual is intended for electrical and computer engineering students at Colorado

State University. Students are expected to have basic knowledge of linux and circuit

analysis.

Hugh-PCText BoxEdited 08/2013 to remove dated information on accessingENS servers and starting Virtuoso. Please follow separate instructions.

An Introduction to Cadence

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Table of Contents Table of Contents ...................................................................................................................... 2

Table of Figures ........................................................................................................................ 4

I. Introduction ........................................................................................................................... 6

II. Accessing and Starting Cadence ......................................................................................... 7

2.1 Accessing the Cadence Software ..................................................................................... 7

2.2 Accessing Cadence from C105, C107 .............................................................................. 7

2.3 Accessing Cadence from Magellan.................................................................................. 9

III. Starting a Project ..............................................................................................................13

3.1 Choosing a Library .........................................................................................................13

3.2 Creating a Cellview ........................................................................................................14

3.3 Inserting Components ....................................................................................................16

IV. Performing Analysis ..........................................................................................................20

4.1 Check and Save ..............................................................................................................20

4.2 Analog Design Environment - L (ADE L) ......................................................................21

4.3 Annotating Node Voltages .............................................................................................24

4.4 Setting a Variable ..........................................................................................................26

4.5 Plotting Output ..............................................................................................................28

V. Advanced Techniques .........................................................................................................32

5.1 Parametric Analysis (Multi-Variable Sweep) ................................................................32

5.2 Building a Test Bench ....................................................................................................33

5.3 Test Bench Example ......................................................................................................34

VI. Reference Guide .................................................................................................................39

6.1 Hotkeys ...........................................................................................................................39

6.2 Troubleshooting..............................................................................................................39

6.2.1 Simulation not Working ..........................................................................................39

6.2.2 Editing Schematic ....................................................................................................39

6.2.3 Cadence is Extremely Slow .....................................................................................40

6.2.4 Error Message: Cell View is Locked by Another Server .........................................40

6.3 Tips .................................................................................................................................40

6.3.1 Create a Netlist .......................................................................................................40

6.3.2 Highlight FETs Operating in Linear Region ..........................................................40

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References ................................................................................................................................41

Glossary ...................................................................................................................................42

Index ........................................................................................................................................43

Table of Figures Figure 1: Cadence Logo [1] ....................................................................................................... 6

Figure 2: Starting xdmcp from Windows Environment .......................................................... 7

Figure 3: Solaris Login Screen ................................................................................................. 8

Figure 4: Opening a Terminal Window in Cygwin-X .............................................................. 8

Figure 5: Starting Cadence from Terminal .............................................................................. 9

Figure 6: PuTTY Screen - Entering Session Information.......................................................10

Figure 7: PuTTY Screen Enabling X11 Forwarding ............................................................11

Figure 8: PuTTY Security Alert ..............................................................................................12

Figure 9: Starting Cadence from Terminal .............................................................................12

Figure 10: Cadence Home Terminal Window .........................................................................13

Figure 11: Navigating to Create a New Library .....................................................................13

Figure 12: Creating a New Library .........................................................................................14

Figure 13: Navigating to Create a New Cellview ...................................................................14

Figure 14: Creating a New Cellview .......................................................................................15

Figure 15: Schematic Editor....................................................................................................15

Figure 16: Next License Error.................................................................................................16

Figure 17: Adding Components into Schematic .....................................................................16

Figure 18: Add Instance Window ............................................................................................17

Figure 19: Library Browser .....................................................................................................18

Figure 20: Add Resistor ...........................................................................................................19

Figure 21: Check and Save ......................................................................................................20

Figure 22: Cadence Highlighting Errors ................................................................................21

Figure 23: Launch ADE L .......................................................................................................22

Figure 24: Choose Analyses ....................................................................................................22

Figure 25: Choosing DC Analyses ...........................................................................................23

Figure 26: Running Analyses ..................................................................................................24

Figure 27: Annotate DC Node Voltages ..................................................................................25

Figure 28: Annotate DC Operating Points .............................................................................25

Figure 29: Setting a Variable ..................................................................................................26

Figure 30: Setting up a Sweep ................................................................................................27

Figure 31: Add Wire Name ......................................................................................................28

Figure 32: Wire Name .............................................................................................................29

Figure 33: Selecting a Node to Plot .........................................................................................29

Figure 34: Outputs to be Plotted .............................................................................................30

Figure 35: Choosing Nodes and Wires to Plot ........................................................................30

Figure 36: Example of Plot from Simple Voltage Divider ......................................................31

Figure 37: Parametric Analysis ..............................................................................................32

Figure 38: Example Parametric Analysis Plot .......................................................................33

Figure 39: Test Bench Example ..............................................................................................34

Figure 40: Voltage Reference Circuit Design ..........................................................................35

Figure 41: ADE L Window for Test Bench ..............................................................................36


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Figure 42: Sweeping NMOS Width .........................................................................................37

Figure 43: Sweeping PMOS Width .........................................................................................37

Figure 44: Results after Using Test Bench .............................................................................38

I. Introduction

The topics presented in this manual are intended to teach electrical and computer

engineering students how to successfully and efficiently use the Cadence software. It will

also serve as a useful reference in your academic career thought the ECE department at

Colorado State University.

Cadence is a powerful tool that allows the user to design fully custom circuits and simulate

them. Programs very similar to Cadence, are extensively used in industry and research.

Building essential Cadence skills will help you in your academic career as a student, and

your career as an engineer.

The manual is written so the user can start from the beginning and learn how to access

Cadence, build a simple circuit and ultimately simulate it. In addition, the end of this

manual contains an advanced technique section, tips, and troubleshooting guide.

This manual was written entirely by the author and all the screenshots were taken by her.

Figure 1: Cadence Logo [1]

II. Accessing and Starting Cadence

2.1 Accessing the Cadence Software

There are several ways to access the Cadence software on campus. All methods lead to a

Linux environment from which Cadence can be started.

2.2 Accessing Cadence from C105, C107

After logging on to your engineering account, you will need to access one of Engineering

Network Services (ENS) servers.

To do this, navigate to the start menu where you will log into a remote session using

Cygwin-X, essentially a Linux based environment for Windows. This program can be found

under All Programs > Communications & Internet > Cygwin-X > xdmcp.

Figure 2: Starting xdmcp from Windows Environment

This will open up a window where you can select one of the Linux servers, as shown in

Figure 3 below. Select one of the servers to continue.

Note: If a large amount of people are accessing Cadence at once, it would be useful to visit the Engineering

Network Services (ENS) website to see the load on each server and choose appropriately.

http://www.engr.colostate.edu/ens/tools/serverstatus/

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III. Starting a Project

3.1 Choosing a Library

Once you have started Cadence from a terminal window, the home Cadence terminal will

be on your screen and it looks as in Figure 10.

Figure 10: Cadence Home Terminal Window

It is useful to create a new library for each assignment or lab. This will be very helpful for

organization and if you ever need to refer back to a schematic.

Figure 11: Navigating to Create a New Library

You will want to reference an existing technology library for the technology file.

Note: Your course instructor will give you the technology file you will want to reference for your projects, this

should be in your Cadence folder and will end with a .tech extension.

Note: ECE202 students do not reference a technology file and can select Do not need process information


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Figure 12: Creating a New Library

3.2 Creating a Cellview

After the library has been created, go back to the home Cadence window that first came up

when you started the software and navigate to File > New > Cellview.

Figure 13: Navigating to Create a New Cellview

A New File window will open up as in Figure 14 and the only field you need to change is

next to Cell where you will enter the desired name of your schematic.


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Figure 14: Creating a New Cellview

You will now be in your schematic view where you can build your circuit. Your window will

look as in Figure 15.

Figure 15: Schematic Editor

If you receive the error in Figure 16, select Always.


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Figure 16: Next License Error

3.3 Inserting Components

You will now want to begin placing components of your circuit into the schematic. This can

be done by accessing the menu Create > Instance.

Figure 17: Adding Components into Schematic


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Figure 18: Add Instance Window

The window in Figure 18 will show up and click Browse to find the component you want.

Most of the basic components (capacitors, resistors, voltage/current supplies, etc.) are under

the analogLib library.

Transistors and more advanced components will be in the library provided by your lab

teacher or Professor.

Note: Always choose symbol under the View category.


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Figure 19: Library Browser

As an example, a resistor will be added to the circuit by selecting analogLib > res > symbol.


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Figure 20: Add Resistor

After you have selected the resistor, the Add Instance window should have expanded as in

Figure 20. Each component will have their own options to fill in.

Once you have entered the value of the resistance in you can hover your mouse over the and

click on the schematic where you would like to place the resistor.

You can either continue to insert more components, or press Esc to get out of the Add

Instance window.


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IV. Performing Analysis

For this portion of the manual, I will use a simple voltage divider as an example of how to

perform analyses on a circuit.

4.1 Check and Save

The first step is to check and make sure there are no errors. Do this by clicking the check

and save icon as in Figure 21.

Note: You cannot perform analyses unless you have a successful Check and Save.

Figure 21: Check and Save

You may get some warnings or errors about your circuit. It is okay to have warnings;

however, if you have errors in your circuit you will have to correct them before moving on to

analyses. Cadence will highlight your errors in your schematic as in Figure 22.


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Figure 22: Cadence Highlighting Errors

4.2 Analog Design Environment - L (ADE L)

Once you have completed a successful Check and Save, go to the top of your schematic

window and navigate to Launch > ADE L.

Note: Be sure to choose ADE L and not ADE XL or any of the other options, these are used for more advanced

analysis.


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Figure 23: Launch ADE L

The ADE L window will open and you can choose what type of analyses you would like. Do

this by navigating to Analyses > Choose... or select the second button down on the right

hand side in Figure 24.

Figure 24: Choose Analyses


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You can set up multiple analyses in ADE L at one time. In general, you should always

create a DC analysis so you can view the voltage and current at each node.

To do this, select the dc option and check the box next to Save DC Operating Point as in

Figure 25.

Figure 25: Choosing DC Analyses

Depending on what the goal of the project is, you will add more types of analyses. Once you

are done setting up the analyses, click the red OK button. All of the analyses you set up

will appear in the ADE L window in the analyses section.

Once you have completed setting up the analyses, you can simulate the circuit. To do this,

click the green arrow button in the ADE L window circled in Figure 26.


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Figure 26: Running Analyses

4.3 Annotating Node Voltages

After running a DC analysis, you can see the voltage at each node by selecting Results >

Annotate > DC Node Voltages in the ADE L window. To see the current through each node

select Results > Annotate > DC Operating Points. If you go back to your schematic, you will

see that the nodes are labeled with the voltage in Figure 27 and current as in Figure 28.

Note: To clear these annotations select Results > Annotate > Design Defaults.


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Figure 27: Annotate DC Node Voltages

Figure 28: Annotate DC Operating Points


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4.4 Setting a Variable

Cadence allows you to define variables in your schematic. Using DC analysis in ADE L, you

can sweep this variable and plot the effects on your circuits performance.

In the case of the simple voltage divider, you can sweep the resistance of one of the resistors

to see how it changes the output voltage.

To sweep a variable during analyses, you must first define the value in your schematic.

Define a variable by changing the value of a component to a desired variable name. An

example of this is shown in Figure 29. Click OK when you are done.

Note: Be sure to check and save before running analyses.

Figure 29: Setting a Variable

After you have checked and saved, return to the ADE L window and select Variables >

Copy from Cellview. The variables from your schematic will now be under the Design

Variable section in the ADE L window. Enter a base value for the component that you want

to sweep.


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Note: The base value of the variable will not have any effect on the sweep. However, when computing node

voltages and currents after analyses, ADE L will use the base value for the variable.

After you enter a base value for the variable, open the properties for DC analysis. Select the

box next to Design Variable and more options will appear as in Figure 30.

Enter in the variable name that you would like to sweep and its starting and ending value.

Select OK and your new DC analysis settings will be updated under the analyses section in

the ADE L window.

Figure 30: Setting up a Sweep


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4.5 Plotting Output

Plotting the results of the ADE L analysis gives the user a way to view the results of

analyses.

Before defining the outputs to be plotted, it is good practice to name the wires in your

schematic. This can be accomplished in the schematic window by selecting Create > Wire

Name

Figure 31: Add Wire Name

The menu in Figure 31 will show up and you can enter your desired wire name. Once you

are done typing, hit the Enter key and select the wire you are naming. The name will now

show up next to that wire as in Figure 32.


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Figure 32: Wire Name

Selecting to output a node or wire will plot all the available information from the analyses.

To select the nodes and wires to plot, navigate in the ADE L window to Outputs > To Be

Plotted > Select on Schematic. You can now select any node or wire in your schematic and it

will be plotted after your run the analyses.

Note: To plot voltage, select a wire. To plot current, select a node.

Figure 33: Selecting a Node to Plot


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The nodes or wires you select to plot will now show up under the Outputs section in the

ADE L window as in Figure 34.

In the case of the simple voltage divider, the output voltage and current through the

variable resistor will be plotted; these are shown selected in Figure 35.

Figure 34: Outputs to be Plotted

Figure 35: Choosing Nodes and Wires to Plot

Run the analyses to produce the plots. Sweeping the resistance of the voltage divider

produced the plot in Figure 36.


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Figure 36: Example of Plot from Simple Voltage Divider

V. Advanced Techniques

This section is intended to increase efficiency and to gain additional skills in using Cadence.

5.1 Parametric Analysis (Multi-Variable Sweep)

To sweep multiple variables at a time, you will need to set up a parametric analysis in the

ADE L window.

Prior to setting up the parametric analysis, define all your variables in the schematic and

choose one variable to sweep in the dc analysis.

To set up the parametric analysis, select Tools > Parametric Analysis and the window in

Figure 37 will open. Define the variable(s) to be swept and enter the starting value, ending

value, and step size.

Figure 37: Parametric Analysis

Click the green arrow button in the Parametric Analysis window to start the multi-variable

sweep. All outputs defined to plot in the ADE L will appear after the parametric analysis is

complete.

For the simple voltage divider case, the voltage source and resistance was varied and

parametric analysis produced the plot in Figure 38.


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Figure 38: Example Parametric Analysis Plot

5.2 Building a Test Bench

Test benches become extremely important when designing amplifiers and more complex

circuits. Building a test bench will allow you to effectively implement the desired node

voltages, widths and lengths, and current for each the FETs in a design.

To build a test bench, open a new schematic and insert one NFET and one PFET. These two

FETs will be used as your test bench for the entire design. In the properties of the FETs,

define their widths as lengths as variables.

Next, hook up a DC voltage supply to each node on both FETs and name them as variables.

Make sure to distinguish the PFET parameters from the NFET parameters. The completed

circuit should look something like Figure 39.

Note: Do not forget to hook up a DC voltage supply to the body of the FETs. For an NFET, connect the body to

ground and connect the PFET body to a DC voltage supply equivalent to VDD.


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Figure 39: Test Bench Example

After checking and saving, launch ADE L and copy the variables from the cell view into

ADE L. Enter the desired values next to the name of the variables.

Note: When there are a lot of variables in your circuit, it is useful to save the ADE L settings. Doing this gives

you the option to load your previous settings when you reopen the circuit at a later time. Save the settings in

the ADE L window by selecting Sessions > Save State. Load ADE L settings by selecting Sessions > Load State

in the ADE L window.

Define the outputs to be plotted and the variable swept in dc analysis. Run the simulation

to see the results of the sweep. These results will assist you in choosing values to use in

your design.

Test benches can be extremely helpful in designing circuits; however, before using a test

bench, you must design the circuit and know what voltages and current you want for each

component. Using the test bench without having a basic design will prove to be

unsuccessful.

5.3 Test Bench Example

To show how useful and accurate test benches are, the design of a simple voltage reference

circuit will be used as an example. This circuit consists of a diode-connected PFET and a


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diode connected NFET, shown in Figure 40. Before building the test bench, decide on the

current through the branches and the node voltages of each FET. For this example, the

values were chosen as in Figure 40.

Figure 40: Voltage Reference Circuit Design

For this example, the test bench will be used to find the widths and of the transistors that

when plugged into the voltage reference circuit, will result in a Vref of 900 mV and 50 uA

current.

Open up the test bench and enter in the desired node voltages with its corresponding

variable.

The node voltages are decided on in the original design and the lengths of the FETs were

left at the default of 220 nm.

Initial values are entered in for the FET widths before sweeping them in DC analysis. The

completed ADE L setup for this example is shown in Figure 41.


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Figure 41: ADE L Window for Test Bench

Once all the variables are correctly modeling the FETs in the voltage divider, individually

sweep the widths of each FET using DC analysis. The results from this example are shown

in Figure 42 and Figure 43.


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Figure 42: Sweeping NMOS Width

Figure 43: Sweeping PMOS Width

From the results of this test bench, the following widths and lengths were determined to

achieve the desired current and node voltages in the voltage reference circuit.

PMOS: l=220 nm, w=1.317 um

NMOS: l=220 nm, w=385 nm


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Take the width and length values obtained from the test bench and enter them into the

FET properties in the voltage reference circuit.

To verify that the test bench was used correctly, run a DC analysis on the voltage reference

circuit and annotate the DC node voltages and DC operating points.

The DC analysis of this voltage reference circuit resulted in Figure 44. The original desired

parameters of the circuit were Vref=900 mV and i=50 uA. Using the test bench to help

choose the sizing of the FETS, the voltage reference circuit resulted in i=49.92 uA and

Vref=900 mV.

Figure 44: Results after Using Test Bench


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VI. Reference Guide

6.1 Hotkeys

Hotkeys are keyboard shortcuts for accessing a tool or menu item. Below is a list of

commonly used hotkeys.

i add instance

q edit instance properties

u undo

w wire

r rotate instance

f fit design in window

x check and save

l add wire name

m add marker (when plotting)

6.2 Troubleshooting

6.2.1 Simulation not Working

Double check that you have checked and saved your schematic, Cadence will not run

analyses unless this has been done.

Make sure you are in the right ADE L window for the circuit you want to simulate.

6.2.2 Editing Schematic


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Cadence stacks commands which can cause problems when editing a design. In between

commands press Esc to return to the pointer, this should resolve many issues that come up

when editing the schematic.

6.2.3 Cadence is Extremely Slow

The server you are using may have a large load. Check the ENS website to find a server

that is not being heavily used.

Remove all annotations from analyses by going to the ADE L design window and selecting

Results > Annote > Design Defaults. If there are a lot of components in your design, having

the node voltages and currents annotated can really slow down Cadence.

6.2.4 Error Message: Cell View is Locked by Another Server

Check to see if the schematic is opened on another computer.

You may not have exited Cadence last properly. To unlock the schematic, navigate to the

folder your circuit is saved in (U:\Cadence\library_name\cell_name). In that folder, there

may be a file with the extension .cdslk. If this type of file is there, delete this file and

reopen the circuit.

6.3 Tips

6.3.1 Create a Netlist

A netlist describes the design of your circuit in code.

To create one for your circuit, go to the ADE L window and select Simulation > Netlist >

Create. A window will open up and you can save the netlist as a .txt file.

6.3.2 Highlight FETs Operating in Linear Region

A quick way to troubleshoot your circuit is to know what mode of operation the FETs are in.

To highlight what FETs are in linear region, run DC analysis and select Results > Circuit

Conditions in the ADE L window. The Circuit Conditions window will open up and select

the box next to Saturation or Linear then press Place. This will

highlight all the FETs in your circuit that are operating in linear region.


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References

[1] Cadence Design Systems, Inc., Virtuoso Analog Design Environment L Datasheet

[Online]. Available: http://www.cadence.com/rl/Resources/datasheets/virtuoso_adeL_ds.pdf

[2] Bruce Stotts, interview, April 2012

[3] Prof. Thomas Chen, interview, April 2012

[4] Sanja Manic, John Blatt, and Diana Peterson, Tutorial for using Cyqwin, Linux Servers

and Cadence for ECE 202 Lab 2 [Powerpoint], Spring 2011

[5] Wikipedia, Cadence Design Systems [Online]. Available:

http://en.wikipedia.org/wiki/Cadence_Design_Systems


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Glossary

ADE L Analog Design Environment - L

ENS Engineering Network Services

Hotkey Keyboard shortcuts

Cygwin-X GUI for servers

GUI graphical user interface

PuTTY ssh client

Netlist


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Index

ddd

Documents

Manual