LTM2887 - SPI/Digital or I2C µModule Isolator with …...LTM2887CY-5I#PBF LTM2887Y-5I 4.5V to 5.5V I2C 0 C to 70 C LTM2887IY-5I#PBF –40 C to 85 C LTM2887HY-5I#PBF –40 C to 125

LTM2887

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For more information www.linear.com/LTM2887

TYPICAL APPLICATION

FEATURES DESCRIPTION

SPI/Digital or I2C µModule Isolator with Dual Adjustable

5V Regulators

The LTM®2887 is a complete galvanic digital µModule® (micromodule) isolator. No external components are required. A single 3.3V or 5V supply powers both sides of the interface through an integrated, isolated DC/DC converter. A logic supply pin allows easy interfacing with different logic levels from 1.62V to 5.5V, independent of the main supply.

Available options are compliant with SPI and I2C (master mode only) specifications.

The isolated side includes two 5V nominal power supplies, including programmable current limit, each capable of providing more than 100mA of load current. The supplies may be adjusted from their nominal value using a single external resistor.

Coupled inductors and an isolation power transformer provide 2500VRMS of isolation between the input and out-put logic interface. This device is ideal for systems where the ground loop is broken, allowing for a large common mode voltage range. Communication is uninterrupted for common mode transients greater than 30kV/μs.L, LT, LTC, LTM, Linear Technology, the Linear logo and µModule are registered trademarks of Analog Devices, Inc. All other trademarks are the property of their respective owners.

Isolated 4MHz SPI Interface

APPLICATIONS

n 6-Channel Logic Isolator: 2500VRMS for 1 Minute n UL-CSA Recognized File #E151738 n Isolated DC Power:

n 1.8V to 5V Logic Supply at Up to 100mA n 0.6V to 5V Auxiliary Supply at Up to 100mA

n No External Components Required n SPI/Digital (LTM2887-S) or I2C (LTM2887-I) Options n High Common Mode Transient Immunity: 30kV/μs n High Speed Operation:

n 10MHz Digital Isolation n 4MHz/8MHz SPI Isolation n 400kHz I2C Isolation

n 3.3V (LTM2887-3) or 5V (LTM2887-5) Operation n 1.62V to 5.5V Logic Supply n ±10kV ESD HBM Across the Isolation Barrier n Maximum Continuous Working Voltage: 560VPEAK n Low Current Shutdown Mode (<10µA) n Low Profile 15mm × 11.25mm × 3.42mm BGA Package

n Isolated SPI or I2C Interfaces n Industrial Systems n Test and Measurement Equipment n Breaking Ground Loops

LTM2887 Operating Through 50kV/µs CM Transients

2887 TA01a

ON

CS CS2

LTM2887-5S

VL

VCC5V

GND GND2

SDI

SDOE

SDI2

DO2

SCK SCK2

CS

SDI

SCK

CS

SDI

SCK

VL2

AVL2

IVL2

AVCC2

IVCC2

VCC2

SDO SDO2SDO SDO

I2

DO1 I1

ISOL

ATIO

N BA

RRIE

R

5V AT 100mA

3.3V AT 100mA

1.15k

27.4k

1.15k

6.04k

20ns/DIV

5V/DIV

200V/DIV

SCKSD0SCK2 = SD02

2887 TA01b

REPETITIVECOMMON MODETRANSIENTSGND2 TO GND

http://www.linear.com/LTM2887


LTM2887

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LTM2887-I LTM2887-S

VCCGNDDO1

AVCC2IVL2GND2I1

BGA PACKAGE32-PIN (15mm × 11.25mm × 3.42mm)

TOP VIEW

AVL2

F

G

H

L

J

K

E

A

B

C

D

21 43 5 6 7 8

DNCDO2 SDASCL DI1 GND ON VL

DNCI2 SDA2SCL2 O1 VL2 IVCC2 VCC2

TJMAX = 125°C, θJA = 23.9°C/W, θJCbottom = 8.1°C/W,

θJCtop = 18.1°C/W, θJB = 9.3°C/W θ VALUES DETERMINED PER JESD51-9, WEIGHT = 1.2g

VCCGNDDO1

AVCC2IVL2GND2I1

BGA PACKAGE32-PIN (15mm × 11.25mm × 3.42mm)

TOP VIEW

AVL2

F

G

H

L

J

K

E

A

B

C

D

21 43 5 6 7 8

DO2SDO SDISCK CS SDOE ON VL

I2SDO2 SDI2SCK2 CS2 VL2 IVCC2 VCC2

TJMAX = 125°C, θJA = 23.9°C/W, θJCbottom = 8.1°C/W,

θJCtop = 18.1°C/W, θJB = 9.3°C/W θ VALUES DETERMINED PER JESD51-9, WEIGHT = 1.2g

ABSOLUTE MAXIMUM RATINGS

VCC to GND .................................................. –0.3V to 6VVL to GND .................................................... –0.3V to 6VVCC2, AVCC2, IVCC2 to GND2......................... –0.3V to 6VVL2, AVL2, IVL2 to GND2 .............................. –0.3V to 6VLogic Inputs

DI1, SCK, SDI, CS, SCL, SDA, SDOE, ON to GND ..................................–0.3V to (VL + 0.3V) I1, I2, SDA2, SDO2 to GND2 ..........................–0.3V to (VL2 + 0.3V)

(Note 1)

PIN CONFIGURATION

Logic Outputs DO1, DO2, SDO to GND ..............–0.3V to (VL + 0.3V) O1, SCK2, SDI2, CS2, SCL2 to GND2 ..........................–0.3V to (VL2 + 0.3V)

Operating Temperature Range (Note 4) LTM2887C ............................................... 0°C to 70°C LTM2887I ............................................–40°C to 85°C LTM2887H ......................................... –40°C to 125°C

Maximum Internal Operating Temperature ............ 125°CStorage Temperature Range .................. –55°C to 125°CPeak Body Reflow Temperature ............................ 245°C


LTM2887

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LTM2887 C Y -3 I #PBF

LEAD FREE DESIGNATORPBF = Lead Free

LOGIC OPTIONI = Inter-IC (I2C) Bus S = Serial Peripheral Interface (SPI) Bus

INPUT VOLTAGE RANGE3 = 3V to 3.6V 5 = 4.5V to 5.5V

PACKAGE TYPEY = Ball Grid Array (BGA)

TEMPERATURE GRADEC = Commercial Temperature Range (0°C to 70°C) I = Industrial Temperature Range (–40°C to 85°C) H = Automotive Temperature Range (–40°C to 125°C)

PRODUCT PART NUMBER

PRODUCT SELECTION GUIDE

ORDER INFORMATION

PART NUMBERPAD OR BALL

FINISH

PART MARKINGPACKAGE

TYPEMSL

RATINGINPUT VOLTAGE RANGE

LOGIC OPTION

TEMPERATURE RANGE DEVICE FINISH CODE

LTM2887CY-3I#PBF

SAC305 (RoHS)

LTM2887Y-3I

e1 BGA 3

3V to 3.6V

I2C

0°C to 70°C

LTM2887IY-3I#PBF –40°C to 85°C

LTM2887HY-3I#PBF –40°C to 125°C

LTM2887CY-3S#PBF

LTM2887Y-3S SPI

0°C to 70°C

LTM2887IY-3S#PBF –40°C to 85°C

LTM2887HY-3S#PBF –40°C to 125°C

LTM2887CY-5I#PBF

LTM2887Y-5I

4.5V to 5.5V

I2C

0°C to 70°C

LTM2887IY-5I#PBF –40°C to 85°C

LTM2887HY-5I#PBF –40°C to 125°C

LTM2887CY-5S#PBF

LTM2887Y-5S SPI

0°C to 70°C

LTM2887IY-5S#PBF –40°C to 85°C

LTM2887HY-5S#PBF –40°C to 125°C

• Device temperature grade is indicated by a label on the shipping container.

• Pad or ball finish code is per IPC/JEDEC J-STD-609.

• Terminal Finish Part Marking: www.linear.com/leadfree

• This product is not recommended for second side reflow. For more information, go to www.linear.com/BGA-assy

• Recommended BGA PCB Assembly and Manufacturing Procedures: www.linear.com/BGA-assy

• BGA Package and Tray Drawings: www.linear.com/packaging

• This product is moisture sensitive. For more information, go to: www.linear.com/BGA-assy

http://www.linear.com/product/LTM2887#orderinfo


http://www.linear.com/leadfree

http://www.linear.com/BGA-assy


http://www.linear.com/packaging


http://www.linear.com/product/LTM2887#orderinfo

LTM2887

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ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating temperature range, otherwise specifications are at TA = 25°C. LTM2887-3 VCC = 3.3V, LTM2887-5 VCC = 5V, VL = 3.3V, and GND = GND2 = 0V, ON = VL unless otherwise noted. Specifications apply to all options unless otherwise noted.SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITSInput SuppliesVCC Input Supply Range LTM2887-3

LTM2887-5l

l

3 4.5

3.3 5

3.6 5.5

V V

VL Logic Supply Range LTM2887-S LTM2887-I

l

l

1.62 3

5

5.5 5.5

V V

ICC Input Supply Current ON = 0V LTM2887-3, ON = VL, No Load LTM2887-5, ON = VL, No Load

l

l

l

0 25 19

10 30 25

µA mA mA

IL Logic Supply Current ON = 0V LTM2887-S, ON = VL LTM2887-I, ON = VL

l 0 10

10

150

µA µA µA

Output SuppliesVCC2 Regulated Output Voltage No Load, AVCC2 Open l 4.75 5 5.25 V

Output Voltage Operating Range (Note 2) 0.6 5.5 V

Line Regulation ILOAD = 1mA, MIN ≤ VCC ≤ MAX l 1 6 mV

Load Regulation ILOAD = 1mA to 100mA l 45 150 mV

ADJ Pin Voltage ILOAD = 1mA to 100mA l 540 580 620 mV

Voltage Ripple ILOAD = 100mA (Note 2) 1 mVRMS

Efficiency LTM2887-5, ILOAD = 100mA (Note 2) 62 %

ICC2 Output Short Circuit Current VCC2 = 0V, IVCC2 = 0V 200 mA

Internal Current Limit ΔVCC2 = –5%, IVCC2 = 0V l 100 mA

External Programmed Current Limit

VCC2 = 5V, R(IVCC2 to GND2) = 2.26k VCC2 = 5V, R(IVCC2 to GND2) = 1.5k VCC2 = 5V, R(IVCC2 to GND2) = 1.15k

l

l

l

49 71 91

53 79

103

57 87

115

mA mA mA

VL2 Regulated Output Voltage No Load, AVL2 Open l 4.75 5 5.25 V

Output Voltage Operating Range LTM2887-I (Note 2) LTM2887-S (Note 2)

3 1.8

5.5 5.5

V V

Line Regulation ILOAD = 1mA, MIN ≤ VCC ≤ MAX l 0.25 3 mV

Load Regulation ILOAD = 1mA to 100mA l 25 100 mV

ADJ Pin Voltage ILOAD = 1mA to 100mA l 540 580 620 mV

Voltage Ripple ILOAD = 100mA (Note 2) 1 mVRMS

Efficiency LTM2887-5, ILOAD = 100mA (Note 2) 62 %

IL2 Output Short Circuit Current VL2 = 0V, IVL2 = 0V 200 mA

Current Limit ΔVL2 = –5%, IVL2 = 0V l 100 mA

External Programmed Current Limit

VL2 = 5V, R(IVL2 to GND2) = 2.26k VL2 = 5V, R(IVL2 to GND2) = 1.5k VL2 = 5V, R(IVL2 to GND2) = 1.15k

l

l

l

49 71 91

53 79

103

57 87

115

mA mA mA

Logic/SPIVITH Input Threshold Voltage ON, DI1, SDOE, SCK, SDI, CS 1.62V ≤ VL < 2.35V

ON, DI1, SDOE, SCK, SDI, CS 2.35V ≤ VL I1, I2, SDO2

l

l

l

0.25 • VL 0.33 • VL 0.33 • VL2

0.75 • VL 0.67 • VL 0.67 • VL2

V V V

IINL Input Current l ±1 µA


LTM2887

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ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITSVHYS Input Hysteresis 150 mV

VOH Output High Voltage DO1, DO2, SDO ILOAD = –1mA, 1.62V ≤ VL < 3V ILOAD = –4mA, 3V ≤ VL ≤ 5.5V

l VL – 0.4 V

O1, SCK2, SDI2, CS2, ILOAD = –4mA l VL2 – 0.4 V

VOL Output Low Voltage DO1, DO2, SDO ILOAD = 1mA, 1.62V ≤ VL < 3V ILOAD = 4mA, 3V ≤ VL ≤ 5.5V

l 0.4 V

O1, SCK2, SDI2, CS2, ILOAD = 4mA l 0.4 V

ISC Short-Circuit Current 0V ≤ (DO1, DO2, SDO) ≤ VL 0V ≤ (O1, SCK2, SDI2, CS2) ≤ VL2

l ±60

±85 mA mA

I2CVIL Low Level Input Voltage SCL, SDA

SDA2l

l

0.3 • VL 0.3 • VL2

V V

VIH High Level Input Voltage SCL, SDA SDA2

l

l

0.7 • VL 0.7 • VL2

V V

IINL Input Current SCL, SDA = VL or 0V SDA2 = VL2, SDA2 = VL2 = 0V

l

l

±1 ±1

µA µA

VHYS Input Hysteresis SCL, SDA SDA2

0.05 • VL 0.05 • VL2

mV mV

VOH Output High Voltage SCL2, ILOAD = –2mA DO2, ILOAD = –2mA

l VL2 – 0.4 VL – 0.4

V V

VOL Output Low Voltage SDA, ILOAD = 3mA DO2, ILOAD = 2mA SCL2, ILOAD = 2mA SDA2, No Load, SDA = 0V, 4.5V ≤ VL2 < 5.5V SDA2, No Load, SDA = 0V, 3V < VL2 < 4.5V

l

l

l

l

l

0.3

0.4 0.4 0.4

0.45 0.55

V V V V V

CIN Input Pin Capacitance SCL, SDA, SDA2 (Note 2) l 10 pF

CB Bus Capacitive Load SCL2, Standard Speed (Note 2) SCL2, Fast Speed SDA, SDA2, SR ≥ 1V/µs, Standard Speed (Note 2) SDA, SDA2, SR ≥ 1V/µs, Fast Speed

l

l

l

l

400 200 400 200

pF pF pF pF

Minimum Bus Slew Rate SDA, SDA2 l 1 V/µs

ISC Short-Circuit Current SDA2 = 0, SDA = VL 0V ≤ SCL2 ≤ VL2 0V ≤ DO2 ≤ VL SDA = 0, SDA2 = VL2 SDA = VL, SDA2 = 0

l ±30 ±30 6

–1.8

100 mA mA mA mA mA

ESD (HBM) (Note 2)Isolation Boundary (VCC2, VL2, GND2) to (VCC, VL, GND) ±10 kV

The l denotes the specifications which apply over the specified operating temperature range, otherwise specifications are at TA = 25°C. LTM2887-3 VCC = 3.3V, LTM2887-5 VCC = 5V, VL = 3.3V, and GND = GND2 = 0V, ON = VL unless otherwise noted. Specifications apply to all options unless otherwise noted.


LTM2887

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SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Logic

Maximum Data Rate DI1 → O1, Ix → DOx, CL = 15pF (Note 3) l 10 MHz

tPHL, tPLH Propagation Delay CL = 15pF (Figure 1) l 35 60 100 ns

tR Rise Time CL = 15pF (Figure 1) LTM2887-I, DO2, CL = 15pF (Figure 1)

l

l

3 20

12.5 35

ns ns

tF Fall Time CL = 15pF (Figure 1) LTM2887-I, DO2, CL = 15pF (Figure 1)

l

l

3 20

12.5 35

ns ns

SPI

Maximum Data Rate Bidirectional Communication (Note 3) Unidirectional Communication (Note 3)

l

l

4 8

MHz MHz

tPHL, tPLH Propagation Delay CL = 15pF (Figure 1) l 35 60 100 ns

tPWU Output Pulse Width Uncertainty SDO, SDI2, CS2 (Note 2) ±50 ns

tR Rise Time CL = 15pF (Figure 1) l 3 12.5 ns

tF Fall Time CL = 15pF (Figure 1) l 3 12.5 ns

tPZH, tPZL Output Enable Time SDOE = ↓, RL = 1kΩ, CL = 15pF (Figure 2) l 50 ns

tPHZ, tPLZ Output Disable Time SDOE = ↑, RL = 1kΩ, CL = 15pF (Figure 2) l 50 ns

I2C

Maximum Data Rate (Note 3) l 400 kHz

tPHL, tPLH Propagation Delay SCL → SCL2, CL = 15pF (Figure 1) SDA → SDA2, RL = Open, CL = 15pF (Figure 3) SDA2 → SDA, RL = 1.1kΩ, CL = 15pF (Figure 3)

l

l

l

150 150 300

225 250 500

ns ns ns

tPWU Output Pulse Width Uncertainty SDA, SDA2 (Note 2) ±50 ns

tHD;DAT Data Hold Time (Note 2) 600 ns

tR Rise Time SDA2, CL = 200pF (Figure 3) SDA, RL = 1.1kΩ, CL = 200pF (Figure 3) SCL2, CL = 200pF (Figure 1)

l

l

l

40 40

300 250 250

ns ns ns

tF Fall Time SDA2, CL = 200pF (Figure 3) SDA, RL = 1.1kΩ, CL = 200pF (Figure 3) SCL2, CL = 200pF (Figure 1)

l

l

l

40 40

250 250 250

ns ns ns

tSP Pulse Width of Spikes Suppressed by Input Filter

l 0 50 ns

Power Supply

Power-Up Time ON = ↑ to VCC2 (Min) ON = ↑ to VL2 (Min)

l

l

3 3

5 5

ms ms

SWITCHING CHARACTERISTICS The l denotes the specifications which apply over the specified operating temperature range, otherwise specifications are at TA = 25°C. LTM2887-3 VCC = 3.3V, LTM2887-5 VCC = 5V, VL = 3.3V, and GND = GND2 = 0V, ON = VL unless otherwise noted. Specifications apply to all options unless otherwise noted.


LTM2887

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Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2: Guaranteed by design and not subject to production test.Note 3: Maximum Data rate is guaranteed by other measured parameters and is not tested directly.

Note 4: This Module includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above specified maximum operating junction temperature may result in device degradation or failure.Note 5: Device considered a 2-terminal device. Pin group A1 through B8 shorted together and pin group K1 through L8 shorted together.Note 6: The rated dielectric insulation voltage should not be interpreted as a continuous voltage rating.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VISO Rated Dielectric Insulation Voltage 1 Minute, Derived from 1 Second Test 1 Second (Notes 5, 6)

2500 3000

VRMS VRMS

Common Mode Transient Immunity LTM2887-3 VCC = 3.3V, LTM2887-5 VCC = 5V, VL = ON = 3.3V, VCM = 1kV, Δt = 33ns (Note 2)

30 kV/µs

VIORM Maximum Continuous Working Voltage (Notes 2, 5) 560

400

VPEAK, VDC

VRMS

Partial Discharge VPD = 750VRMS (Note 5) 5 pC

Input to Output Resistance (Notes 2, 5) 109 Ω

CTI Comparative Tracking Index IEC 60112 (Note 2) 600 VRMS

Depth of Erosion IEC 60112 (Note 2) 0.017 mm

DTI Distance Through Insulation (Note 2) 0.06 mm

Input to Output Capacitance (Notes 2, 5) 6 pF

Creepage Distance (Note 2) 9.5 mm

ISOLATION CHARACTERISTICS TA = 25°C.


LTM2887

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TYPICAL PERFORMANCE CHARACTERISTICS

VCC2 or VL2 Output Voltage vs Input Voltage and Load Current

VCC2 or VL2 Output Voltage vs Input Voltage and Load Current

VCC Supply Current vs Temperature

VCC2 and VL2 Voltage vs Equal Load Current

TA = 25°C, LTM2887-3 VCC = 3.3V, LTM2887-5 VCC = 5V, VL = 3.3V, GND = GND2 = 0V, ON = VL unless otherwise noted.

VCC2 or VL2 Load Regulation vs Temperature

VCC2 or VL2 EfficiencyVCC2 or VL2 Voltage and VCC Input Current vs Load Current

VCC2 or VL2 Load Regulation vs Temperature

TEMPERATURE (°C)–50

SUPP

LY C

URRE

NT (m

A)

30

25

15

10

20

5500 100

2887 G01

12525–25 75

NO LOAD, REFRESH DATA ONLY

LTM2887-3VCC = 3.3V

LTM2887-5VCC = 5V

LOAD CURRENT (mA)0

OUTP

UT V

OLTA

GE (V

)

5.25

4.50

4.25

4.75

5.00

4.0010050 7525

2887 G02

125

LTM2887-3, VCC = 3.3VLTM2887-5, VCC = 5V

LOAD CURRENT (mA)0

OUTP

UT V

OLTA

GE (V

)

5.25

4.25

4.50

4.75

5.00

4.0010050

2887 G03

200150

LTM2887-3, VCC = 3VLTM2887-3, VCC = 3.3VLTM2887-3, VCC = 3.6V

LOAD CURRENT (mA)0

OUTP

UT V

OLTA

GE (V

)

5.25

4.25

4.50

4.75

5.00

4.0015010050 200

2887 G04

250

LTM2887-5, VCC = 4.5VLTM2887-5, VCC = 5VLTM2887-5, VCC = 5.5V

TEMPERATURE (°C)–50

OUTP

UT V

OLTA

GE (V

)

5.10

4.95

5.00

5.05

4.90250–25 50

2887 G05

12510075

LTM2887-3VCC = 3.3V

ILOAD = 1mAILOAD = 10mAILOAD = 100mA

5.10

5.05

5.00

4.95

4.90

TEMERATURE (°C)–50

OUTP

UT V

OLTA

GE (V

)

7550250–25

2887 G06

125100

ILOAD = 1mAILOAD = 10mAILOAD = 100mA

LTM2887-5VCC = 5V

LOAD CURRENT (mA)0

EFFI

CIEN

CY (%

)

POWER LOSS (W

)

70

10

20

30

40

50

60

0

1.4

0.2

0.4

0.6

0.8

1.0

1.2

0.0125100755025 175150

2887 G07

225200

EFFICIENCY

POWER LOSS

LTM2887-3, VCC = 3.3VLTM2887-5, VCC = 5V

LOAD CURRENT (mA)0

OUTP

UT V

OLTA

GE (V

) ICC CURRENT (mA)

5.5

2.0

3.0

2.5

3.5

4.0

4.5

5.0

1.5

800

100

200

300

400

500

600

700

0.0125100755025 175150

2887 G08

225200

LTM2887-3, VCC = 3.3VLTM2887-5, VCC = 5V

VOLTAGE

CURRENT


LTM2887

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TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, LTM2887-3 VCC = 3.3V, LTM2887-5 VCC = 5V, VL = 3.3V, GND = GND2 = 0V, ON = VL unless otherwise noted.

VCC2 or VL2 Transient Response 100mA Load Step VCC2 or VL2 Ripple

200µs/DIV

2887 G09

0.2V/DIV

50mA/DIV

400ns/DIV

2887 G10

5mV/DIV

LOAD = 100mA

LOAD = 1mA

VCC2 or VL2 Noise

10ms/DIV

2887 G11

2mV/DIV

LOAD = 100mA

LOAD = 1mA

VCC Supply Current vs Single Channel Data Rate

Logic Input Threshold vs VL Supply Voltage

Logic Output Voltage vs Load Current

DATA RATE (Hz)1k

V CC

CURR

ENT

(mA)

70

60

20

30

40

50

10100k10k 1M

2887 G12

100M10M

LTM2887-5CL = 1nFCL = 330pFCL = 100pFCL = 20pF

VL SUPPLY VOLTAGE (V)1

THRE

SHOL

D VO

LTAG

E (V

)

3.5

2.5

0.5

1.0

2.0

3.0

1.5

04 52

2887 G13

63

INPUT RISING

INPUT FALLING

|LOAD CURRENT| (mA)0

OUTP

UT V

OLTA

GE (V

)

6

1

2

3

4

5

021 3

2887 G14

10987654

VL = 5.5VVL = 3.3VVL = 1.62V

Power On SequenceVCC2 and VL2 Efficiency with Equal Load Current

2887 G15

1V/DIV

1ms/DIV

5V/DIV

ON

VCC2 or VL2

VL = 5V

LOAD CURRENT (mA)0

EFFI

CIEN

CY (%

)

POWER LOSS (W

)

70

20

10

30

40

50

60

0

1.4

0.8

0.4

0.6

0.2

1.0

1.2

0.0755025 100

2887 G16

125

LTM2887-3, VCC = 3.3VLTM2887-5, VCC = 5V

POWER LOSS

EFFICIENCY

BASED ON THERMAL IMAGINGOF DEMO CIRCUIT 1791AVCC2 and VL2 EQUALLY LOADED

LTM2887-3, VCC = 3.3VLTM2887-5, VCC = 5V

TEMPERATURE (°C)0 25 50 75 100 125

0

100

200

300

400

500

600

V CC

SUPP

LY C

URRE

NT (m

A)

2887 G17

Derating for 125°C Maximum Internal Operating Temperature


LTM2887

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PIN FUNCTIONSLTM2887-I Logic Side

DO2 (A1): Digital Output, Referenced to VL and GND. Logic output connected to I2 through isolation barrier. Under the condition of an isolation communication failure this output is in a high impedance state.

DNC (A2): Do Not Connect. Pin connected internally.

SCL (A3): Serial I2C Clock Input, Referenced to VL and GND. Logic input connected to isolated side SCL2 pin through isolation barrier. Clock is unidirectional from logic to isolated side. Do not float.

SDA (A4): Serial I2C Data Pin, Referenced to VL and GND. Bidirectional logic pin connected to isolated side SDA2 pin through isolation barrier. Under the condition of an isola-tion communication failure this pin is in a high impedance state. Do not float.

DI1 (A5): Digital Input, Referenced to VL and GND. Logic input connected to O1 through isolation barrier. The logic state on DI1 translates to the same logic state on O1. Do not float.

GND (A6, B2 to B6): Circuit Ground.

ON (A7): Enable, Referenced to VL and GND. Enables power and data communication through the isolation barrier. If ON is high the part is enabled and power and communications are functional to the isolated side. If ON is low the logic side is held in reset, all digital outputs are in a high impedance state, and the isolated side is unpowered. Do not float.

VL (A8): Logic Supply. Interface supply voltage for pins DI1, SCL, SDA, DO1, DO2, and ON. Operating voltage is 1.62V to 5.5V. Internally bypassed with 1µF.

DO1 (B1): Digital Output, Referenced to VL and GND. Logic output connected to I1 through isolation barrier. Under the condition of an isolation communication failure this output is in a high impedance state.

VCC (B7 to B8): Supply Voltage. Operating voltage is 3V to 3.6V for LTM2887-3 and 4.5V to 5.5V for LTM2887-5. Internally bypassed with 2.2µF.

LTM2887-I Isolated Side

I2 (L1): Digital Input, Referenced to VL2 and GND2. Logic input connected to DO2 through isolation barrier. The logic state on I2 translates to the same logic state on DO2. Do not float.

DNC (L2): Do Not Connect. Pin connected internally.

SCL2 (L3): Serial I2C Clock Output, Referenced to VL2 and GND2. Logic output connected to logic side SCL pin through isolation barrier. Clock is unidirectional from logic to isolated side. SCL2 has a push-pull output stage, do not connect an external pull-up device. Under the condition of an isolation communication failure this output defaults to a high state.

SDA2 (L4): Serial I2C Data Pin, Referenced to VL2 and GND2. Bidirectional logic pin connected to logic side SDA pin through isolation barrier. Output is biased high by a 1.8mA current source. Do not connect an external pull-up device to SDA2. Under the condition of an isolation communication failure this output defaults to a high state.

O1 (L5): Digital Output, Referenced to VL2 and GND2. Logic output connected to DI1 through isolation barrier. Under the condition of an isolation communication failure O1 defaults to a high state.

VL2 (L6): 3V to 5.5V Adjustable Isolated Supply Voltage. Internally generated from VCC by an isolated DC/DC con-verter and regulated to 5V with no external components. Internally bypassed with 4.7µF.

IVCC2 (L7): VCC2 precision current limit adjust pin. Current limit threshold is set by connecting a resistor between IVCC2 and GND2. For detailed information on how to set the current limit resistor value, see the Application Infor-mation section. If not used, tie IVCC2 to GND2. Internally bypassed with 10nF.

VCC2 (L8): 0.6V to 5.5V Adjustable Isolated Supply Volt-age. Internally generated from VCC by an isolated DC/DC converter and regulated to 5V with no external components. Internally bypassed with 4.7µF.

I1 (K1): Digital Input, Referenced to VL2 and GND2. Logic input connected to DO1 through isolation barrier. The logic state on I1 translates to the same logic state on DO1. Do not float.

GND2 (K2 to K5): Isolated Ground.


LTM2887

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PIN FUNCTIONSLTM2887-I Isolated Side

AVL2 (K6): 5V Nominal Isolated Supply Voltage Adjust. The adjust pin voltage is 600mV referenced to GND2. See Applications Information section for details.

IVL2 (K7): VL2 precision current limit adjust pin. Current limit threshold is set by connecting a resistor between IVL2 and GND2. For detailed information on how to set the current limit resistor value, see the Application Infor-mation section. If not used, tie IVL2 to GND2. Internally bypassed with 10nF.

AVCC2 (K8): 5V Nominal Isolated Supply Voltage Adjust. The adjust pin voltage is 600mV referenced to GND2. See Applications Information section for details.

LTM2887-S Logic Side

SDO (A1): Serial SPI Digital Output, Referenced to VL and GND. Logic output connected to isolated side SDO2 pin through isolation barrier. Under the condition of an isolation communication failure this output is in a high impedance state.

DO2 (A2): Digital Output, Referenced to VL and GND. Logic output connected to I2 through isolation barrier. Under the condition of an isolation communication failure this output is in a high impedance state.

SCK (A3): Serial SPI Clock Input, Referenced to VL and GND. Logic input connected to isolated side SCK2 pin through isolation barrier. Do not float.

SDI (A4): Serial SPI Data Input, Referenced to VL and GND. Logic input connected to isolated side SDI2 pin through isolation barrier. Do not float.

CS (A5): Serial SPI Chip Select, Referenced to VL and GND. Logic input connected to isolated side CS2 pin through isolation barrier. Do not float.

SDOE (A6): Serial SPI Data Output Enable, Referenced to VL and GND. A logic high on SDOE places the logic side SDO pin in a high impedance state, a logic low enables the output. Do not float.

ON (A7): Enable, Referenced to VL and GND. Enables power and data communication through the isolation barrier. If ON is high the part is enabled and power and

communications are functional to the isolated side. If ON is low the logic side is held in reset, all digital outputs are in a high impedance state, and the isolated side is unpowered. Do not float.

VL (A8): Logic Supply. Interface supply voltage for pins SDI, SCK, SDO, SDOE, DO1, DO2, CS, and ON. Operating voltage is 1.62V to 5.5V. Internally bypassed with 1µF.

DO1 (B1): Digital Output, Referenced to VL and GND. Logic output connected to I1 through isolation barrier. Under the condition of an isolation communication failure this output is in a high impedance state.

GND (B2 to B6): Circuit Ground.

VCC (B7 to B8): Supply Voltage. Operating voltage is 3V to 3.6V for LTM2887-3 and 4.5V to 5.5V for LTM2887-5. Internally bypassed with 2.2µF.

LTM2887-S Isolated Side

SDO2 (L1): Serial SPI Digital Input, Referenced to VL2 and GND2. Logic input connected to logic side SDO pin through isolation barrier. Do not float.

I2 (L2): Digital Input, Referenced to VL2 and GND2. Logic input connected to DO2 through isolation barrier. The logic state on I2 translates to the same logic state on DO2. Do not float.

SCK2 (L3): Serial SPI Clock Output, Referenced to VL2 and GND2. Logic output connected to logic side SCK pin through isolation barrier. Under the condition of an isolation communication failure this output defaults to a low state.

SDI2 (L4): Serial SPI Data Output, Referenced to VL2 and GND2. Logic output connected to logic side SDI pin through isolation barrier. Under the condition of an isolation communication failure this output defaults to a low state.

CS2 (L5): Serial SPI Chip Select, Referenced to VL2 and GND2. Logic output connected to logic side CS pin through isolation barrier. Under the condition of an isolation com-munication failure this output defaults to a high state.

VL2 (L6): 1.8V to 5.5V Adjustable Isolated Supply Voltage. Internally generated from VCC by an isolated DC/DC con-verter and regulated to 5V with no external components. Internally bypassed with 4.7µF.


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PIN FUNCTIONSLTM2887-S Isolated Side

IVCC2 (L7): VCC2 precision current limit adjust pin. Current limit threshold is set by connecting a resistor between IVCC2 and GND2. For detailed information on how to set the current limit resistor value, please see the Applica-tion Information section. If not used, tie IVCC2 to GND2. Internally bypassed with 10nF.

VCC2 (L8): 0.6V to 5.5V Adjustable Isolated Supply Volt-age. Internally generated from VCC by an isolated DC/DC converter and regulated to 5V with no external components. Internally bypassed with 4.7µF.

I1 (K1): Digital Input, Referenced to VL2 and GND2. Logic input connected to DO1 through isolation barrier. The logic state on I1 translates to the same logic state on DO1. Do not float.

GND2 (K2 to K5): Isolated Ground.

AVL2 (K6): 5V Nominal Isolated Supply Voltage Adjust. The adjust pin voltage is 600mV Referenced to GND2. See Applications Information section for details..

IVL2 (K7): VL2 precision current limit adjust pin. Current limit threshold is set by connecting a resistor between IVL2 and GND2. For detailed information on how to set the current limit resistor value, please see the Applica-tion Information section. If not used, tie IVL2 to GND2. Internally bypassed with 10nF.

AVCC2 (K8): 5V Nominal Isolated Supply Voltage Adjust. The adjust pin voltage is 600mV Referenced to GND2. See Applications Information section for details.


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BLOCK DIAGRAMSLTM2887-I

2887 BDa

1µF

VCC

IVCC2

AVCC2

IVL2

VL2

VCC2

VL 2.2µF

GND

ON

SDA

DI1

DO2

DO1

SCL

O1

AVL2

I2

I1

SCL2

SDA2

GND2

DC/DCCONVERTER

ISOLATEDCOMMUNI-CATIONS

INTERFACE


INTERFACE

REG

REG

REG

4.7µF

4.7µF

10nF

10nF


LTM2887

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BLOCK DIAGRAMS

2887 BDb

1µF

VCC

IVCC2

AVCC2

IVL2

VL2

VCC2

VL 2.2µF

GND

ON

SDI

CS

SDO

DO2

SDOE

DO1

SCK

CS2

AVL2

SDO2

I2

I1

SCK2

SDI2

GND2

DC/DCCONVERTER


INTERFACE


INTERFACE

REG

REG

REG

4.7µF

4.7µF

10nF

10nF

LTM2887-S


LTM2887

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TEST CIRCUITS

INPUT

OUTPUT

CLtPLH tPHL

tR tF

90%

10%

10%

90%½VL2

½VL

VL

VOL

VOH

0V

INPUT

OUTPUT

INPUT

OUTPUT

CL

2887 F01

tPLH tPHL

tR tF

90%

10%

10%

90%½VL

½VL2

VL2

VOL

VOH

0V

INPUT

OUTPUT

Figure 1. Logic Timing Measurements

Figure 2. Logic Enable/Disable Time

Figure 3. I2C Timing Measurements

2887 F02

SDOE

tPZH

tPZL

tPHZ

tPLZ

VOL + 0.5V

VOH – 0.5V

½VL

VL

VOH

VOL

0V

0VVL

SDO

SDO

SDOE

½VL

½VL

SDO

VL OR 0V

0V OR VL2

SDO2

CL

RL

tPHL tPLH

tF tR

30%½VL 70%

70%

30%VOL

VOH

SDA

SDA2

CL

VL

VOL

VOH

0V

SDA

SDA2

VL

RL

2887 F03

½VL2

tPHL tPLH

tF tR

30%½VL2 70%

70%

30%

½VL

VL2

0V

SDA2

SDA

SDA

CL

VL

RL

SDA2


LTM2887

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APPLICATIONS INFORMATIONOverview

The LTM2887 digital µModule isolator provides a galvanically-isolated robust logic interface, powered by an integrated, regulated DC/DC converter, complete with decoupling capacitors. The LTM2887 is ideal for use in networks where grounds can take on different voltages. Isolation in the LTM2887 blocks high voltage differences, eliminates ground loops and is extremely tolerant of com-mon mode transients between ground planes. Error-free operation is maintained through common mode events greater than 30kV/μs providing excellent noise isolation.

Isolator µModule Technology

The LTM2887 utilizes isolator µModule technology to translate signals and power across an isolation barrier. Signals on either side of the barrier are encoded into pulses and translated across the isolation boundary using core-less transformers formed in the µModule substrate. This system, complete with data refresh, error checking, safe shutdown on fail, and extremely high common mode im-munity, provides a robust solution for bidirectional signal isolation. The µModule technology provides the means to combine the isolated signaling with multiple regulators and a powerful isolated DC/DC converter in one small package.

DC/DC Converter

The LTM2887 contains a fully integrated DC/DC converter, including the transformer, so that no external components are necessary. The logic side contains a full-bridge driver, running at 1.6MHz, and is AC-coupled to a single trans-former primary. A series DC blocking capacitor prevents transformer saturation due to driver duty cycle imbalance. The transformer scales the primary voltage, and is recti-fied by a full-wave voltage doubler. This topology allows for a single diode drop, as in a center tapped full-wave bridge, and eliminates transformer saturation caused by secondary imbalances.

Three low dropout regulators (LDOs) are connected to the output of the voltage doubler. One LDO powers the internal circuitry and is not available externally. The other two LDOs provide regulated 5V nominally for the VCC2 and VL2 outputs. VL2 corresponds to the voltage levels on the isolated logic pins.

The internal power solution is sufficient to provide a minimum of 100mA of current from VCC2 and VL2. VCC is bypassed with 2.2µF, VCC2 and VL2 are each bypassed with 4.7µF.

VL Logic Supply

A separate logic supply pin VL allows the LTM2887 to in-terface with any logic signal from 1.62V to 5.5V as shown in Figure 4. Simply connect the desired logic supply to VL.

There is no interdependency between VCC and VL; they may simultaneously operate at any voltage within their specified operating ranges and sequence in any order. VL is bypassed internally by a 1µF capacitor.

Hot-Plugging Safely

Caution must be exercised in applications where power is plugged into the LTM2887’s power supplies, VCC or VL, due to the integrated ceramic decoupling capacitors. The parasitic cable inductance along with the high Q char-acteristics of ceramic capacitors can cause substantial ringing which could exceed the maximum voltage ratings and damage the LTM2887. Refer to Linear Technology Ap-plication Note 88, entitled Ceramic Input Capacitors Can Cause Overvoltage Transients for a detailed discussion and mitigation of this phenomenon.

2887 F04

ON

DI1 O1

LTM2887-I

ANY VOLTAGE FROM1.62V TO 5.5V

3V TO 3.6V LTM2887-34.5V TO 5.5V LTM2887-5

EXTERNALDEVICE

VL

VCC

GND GND2

SDA SDA2

SCL SCL2

VL2

AVL2

IVL2

AVCC2

IVCC2

VCC2

DO2 I2

DO1 I1

ISOL

ATIO

N BA

RRIE

R

Figure 4. VCC and VL Are Independent


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APPLICATIONS INFORMATION

Figure 5. Adjustable Voltage Rails

Isolated Supply Adjustable Operation

The two isolated power rails may be adjusted by connection of external resistive dividers. The unadjusted output volt-ages represent the maximums for guaranteed performance. Figure 5 illustrates configuration of the output power rails for VCC2 = 3.3V, and VL2 = 2.5V.

The output adjustment range for VCC2 is 0.6V to 5.5V. Output voltage is calculated by:

VCC2 = 0.6V(1 + R2/R1)

Adjustment range for VL2 is 3V to 5.5V for the LTM2887-I, and 1.8V to 5.5V for the LTM2887-S. Output voltage is calculated by:

VL2 = 0.6V(1 + R5/R4)

The value of R1 or R4 should be no greater than 6.04k to minimize errors in the output voltage caused by the adjust pin bias currents and internal voltage dividers.

Operation at low output voltages may result in thermal shutdown due to low dropout regulator power dissipation.

Isolated Supply Programmable Current Limit

The IVCC2 pin and IVL2 pin allow programming of the maximum current available from VCC2 and VL2 respec-tively. The current adjustments may be used to limit the

maximum output power, insuring that either voltage rail does not collapse if the opposing rail is loaded beyond its capability. The current limit threshold (ILIMIT) is set by attaching a resistor (RIMAX) from IVCC2 or IVL2 to GND2: RIMAX = [119.22-(0.894 • (VCC2, VL2))]/ILIMIT

The accuracy of this equation for setting the resistor value is approximately ±1%. Unit values are amps, volts, and ohms. Figure 5 shows the current limit programmed for 75mA on VCC2 and 25mA on VL2. If the external program-mable current limit is not needed, the IVCC2 pin or IVL2 must be connected to GND2. The current limit pins are internally decoupled with 10nF capacitors.

Channel Timing Uncertainty

Multiple channels are supported across the isolation bound-ary by encoding and decoding of the inputs and outputs. Up to three signals in each direction are assembled as a packet and transferred across the isolation barrier. The time required to transfer all 3 bits is 100ns maximum, and sets the limit for how often a signal can change on the opposite side of the barrier. Encoding transmission is independent for each data direction. The technique used assigns SCK or SCL on the logic side, and SDO2 or I2 on the isolated side, the highest priority such that there is

2887 F05

CS CS2

LTM2887-5S

VL

VCC5V

GND GND2

SDI SDI2

DO2

SCK SCK2

VL2

AVL2

IVL2

AVCC2

IVCC2

VCC2

SDO SDO2

I2

DO1 I1

ISOL

ATIO

N BA

RRIE

R

3.3V AT 75mA2.5V AT 25mA

R64.64k

R519.1k

R31.54k

R16.04k

R227.4k

R46.04k

ON

SDOE


LTM2887

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no jitter on the associated output channels, only delay. This preemptive scheme will produce a certain amount of uncertainty on the other isolation channels. The resulting pulse width uncertainty on these low priority channels is typically ±6ns, but may vary up to ±50ns if the low priority channels are not encoded within the same high priority serial packet.

Serial Peripheral Interface (SPI) Bus

The LTM2887-S provides a SPI compatible isolated inter-face. The maximum data rate is a function of the inherent channel propagation delays, channel to channel pulse width uncertainty, and data direction requirements. Chan-nel timing is detailed in Figures 6 through 9 and Tables 2 and 3. The SPI protocol supports four unique timing configurations defined by the clock polarity (CPOL) and clock phase (CPHA) summarized in Table 1.

Table 1. SPI ModeCPOL CPHA DATA TO (CLOCK) RELATIONSHIP

0 0 Sample (Rising) Set-Up (Falling)

0 1 Set-Up (Rising) Sample (Falling)

1 0 Sample (Falling) Set-Up (Rising)

1 1 Set-Up (Falling) Sample (Rising)

The maximum data rate for bidirectional communication is 4MHz, based on a synchronous system, as detailed in the timing waveforms. Slightly higher data rates may be achieved by skewing the clock duty cycle and minimiz-ing the SDO to SCK set-up time, however the clock rate is still dominated by the system propagation delays. A discussion of the critical timing paths relative to Figure 6 and 7 follows.

• CS to SCK (master sample SDO, 1st SDO valid)

t0 → t1 ≈50ns, CS to CS2 propagation delay

t1 → t1+ Isolated slave device propagation (response time), asserts SDO2

t1 → t3 ≈50ns, SDO2 to SDO propagation delay

t3 → t5 Set-up time for master SDO to SCK

APPLICATIONS INFORMATION• SDI to SCK (master data write to slave)

t2 → t4 ≈50ns, SDI to SDI2 propagation delay

t5 → t6 ≈50ns, SCK to SCK2 propagation delay

t2 → t5 ≥50ns, SDI to SCK, separate packet non-zero set-up time

t4 → t6 ≥50ns, SDI2 to SCK2, separate packet non-zero set-up time

• SDO to SCK (master sample SDO, subsequent SDO valid)

t8 set-up data transition SDI and SCK

t8 → t10 ≈50ns, SDI to SDI2 and SCK to SCK2 propagation delay

t10 SDO2 data transition in response to SCK2

t10 → t11 ≈50ns, SDO2 to SDO propagation delay

t11 → t12 Set-up time for master SDO to SCK

Maximum data rate for single direction communication, master to slave, is 8MHz, limited by the systems encod-ing/decoding scheme or propagation delay. Timing details for both variations of clock phase are shown in Figures 8 and 9 and Table 3.

Additional requirements to insure maximum data rate are:

• CS is transmitted prior to (asynchronous) or within the same (synchronous) data packet as SDI

• SDI and SCK set-up data transition occur within the same data packet. Referencing Figure 6, SDI can pre-cede SCK by up to 13ns (t7 → t8) or lag SCK by 3ns (t8 → t9) and not violate this requirement. Similarly in Figure 8, SDI can precede SCK by up to 13ns (t4 → t5) or lag SCK by 3ns (t5 → t6).


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Figure 6. SPI Timing, Bidirectional, CPHA = 0

Figure 7. SPI Timing, Bidirectional, CPHA = 1

2887 F06

SDO2

SDO

SCK2 (CPOL = 1)

SCK (CPOL = 1)

SCK2 (CPOL = 0)

SCK (CPOL = 0)

SDI2

SDI

CS2

CS = SDOE

CPHA = 0

t0 t1 t2 t3 t4 t5 t6 t7t8

t9 t10 t11 t12 t13 t14 t15 t17 t18

INVALID

2887 F07

SDO2

SDO

SCK2 (CPOL = 1)

SCK (CPOL = 1)

SCK2 (CPOL = 0)

SCK (CPOL = 0)

SDI2

SDI

CS2

CS = SDOE

CPHA = 1

t0 t1 t2 t3 t4 t5 t6 t7t8

t9 t10 t11 t12 t13 t14 t15 t16 t17 t18

INVALID


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Figure 8. SPI Timing, Unidirectional, CPHA = 0

Figure 9. SPI Timing, Unidirectional, CPHA = 1

2887 F08

SCK2 (CPOL = 1)

SCK (CPOL = 1)

SCK2 (CPOL = 0)

SCK (CPOL = 0)

SDI2

SDI

CS2

CS = SDOE

CPHA = 0

t0 t1 t2 t3 t4 t5 t7t6

t9t8 t11 t12

2887 F09

SCK2 (CPOL = 1)

SCK (CPOL = 1)

SCK2 (CPOL = 0)

SCK (CPOL = 0)

SDI2

SDI

CS2

CS = SDOE

CPHA = 1

t0 t1 t2 t3 t4 t5 t7t6

t9t8 t11t10 t12


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Table 2. Bidirectional SPI Timing Event DescriptionTIME CPHA EVENT DESCRIPTION

t0 0, 1 Asynchronous chip select, may be synchronous to SDI but may not lag by more than 3ns. Logic side slave data output enabled, initial data is not equivalent to slave device data output

t0 to t1, t17 to t18 0, 1 Propagation delay chip select, logic to isolated side, 50ns typical

t1 0, 1 Slave device chip select output data enable

t2 0 Start of data transmission, data set-up

1 Start of transmission, data and clock set-up. Data transition must be within –13ns to 3ns of clock edge

t1 to t3 0, 1 Propagation delay of slave data, isolated to logic side, 50ns typical

t3 0, 1 Slave data output valid, logic side

t2 to t4 0 Propagation delay of data, logic side to isolated side

1 Propagation delay of data and clock, logic side to isolated side

t5 0, 1 Logic side data sample time, half clock period delay from data set-up transition

t5 to t6 0, 1 Propagation delay of clock, logic to isolated side

t6 0, 1 Isolated side data sample time

t8 0, 1 Synchronous data and clock transition, logic side

t7 to t8 0, 1 Data to clock delay, must be ≤13ns

t8 to t9 0, 1 Clock to data delay, must be ≤3ns

t8 to t10 0, 1 Propagation delay clock and data, logic to isolated side

t10, t14 0, 1 Slave device data transition

t10 to t11, t14 to t15 0, 1 Propagation delay slave data, isolated to logic side

t11 to t12 0, 1 Slave data output to sample clock set-up time

t13 0 Last data and clock transition logic side

1 Last sample clock transition logic side

t13 to t14 0 Propagation delay data and clock, logic to isolated side

1 Propagation delay clock, logic to isolated side

t15 0 Last slave data output transition logic side

1 Last slave data output and data transition, logic side

t15 to t16 1 Propagation delay data, logic to isolated side

t17 0, 1 Asynchronous chip select transition, end of transmission. Disable slave data output logic side

t18 0, 1 Chip select transition isolated side, slave data output disabled



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APPLICATIONS INFORMATIONTable 3. Unidirectional SPI Timing Event DescriptionTIME CPHA EVENT DESCRIPTION

t0 0, 1 Asynchronous chip select, may be synchronous to SDI but may not lag by more than 3ns

t0 to t1 0, 1 Propagation delay chip select, logic to isolated side

t2 0 Start of data transmission, data set-up

1 Start of transmission, data and clock set-up. Data transition must be within –13ns to 3ns of clock edge

t2 to t3 0 Propagation delay of data, logic side to isolated side

1 Propagation delay of data and clock, logic side to isolated side

t3 0, 1 Logic side data sample time, half clock period delay from data set-up transition

t3 to t5 0, 1 Clock propagation delay, clock and data transition

t4 to t5 0, 1 Data to clock delay, must be ≤13ns

t5 to t6 0, 1 Clock to data delay, must be ≤3ns

t5 to t7 0, 1 Data and clock propagation delay

t8 0 Last clock and data transition

1 Last clock transition

t8 to t9 0 Clock and data propagation delay

1 Clock propagation delay

t9 to t10 1 Data propagation delay

t11 0, 1 Asynchronous chip select transition, end of transmission

t12 0, 1 Chip select transition isolated side

Inter-IC Communication (I2C) Bus

The LTM2887-I provides an I2C compatible isolated in-terface. Clock (SCL) is unidirectional, supporting master mode only, and data (SDA) is bidirectional. The maximum data rate is 400kHz which supports fast-mode I2C. Timing is detailed in Figure 10. The data rate is limited by the slave acknowledge setup time (tSU;ACK), consisting of the I2C

Figure 10. I2C Timing Diagram

2887 F10

SDA

1 8 9

SDA2

SCL

SCL2

START tPROP tSU;DAT tHD;DAT tSU;ACK

SLAVE ACK

STOP

standard minimum setup time (tSU;DAT) of 100ns, maximum clock propagation delay of 225ns, glitch filter and isolated data delay of 500ns maximum, and the combined isolated and logic data fall time of 300ns at maximum bus load-ing. The total setup time reduces the I2C data hold time (tHD;DAT) to a maximum of 175ns, guaranteeing sufficient data setup time (tSU;ACK).


LTM2887

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The isolated side bidirectional serial data pin, SDA2, simplified schematic is shown in Figure 11. An internal 1.8mA current source provides a pull-up for SDA2. Do not connect any other pull-up device to SDA2. This current source is sufficient to satisfy the system requirements for bus capacitances greater than 200pF in FAST mode and greater than 400pF in STANDARD mode.


CBUS (pF)10

R PUL

L_UP

(kΩ

)

30

25

5

10

15

20

0100

2887 F12

1000

V = 3VV = 3.3VV = 3.6VV = 4.5V TO 5.5V

CBUS (pF)10

R PUL

L_UP

(kΩ

)

10

9

1

3

5

7

2

4

6

8

0100

2887 F13

1000

V = 3VV = 3.3VV = 3.6VV = 4.5V TO 5.5V

Figure 12. Maximum Standard Speed Pull-Up Resistance on SDA

Figure 13. Maximum Fast Speed Pull-Up Resistance on SDA

Additional proprietary circuitry monitors the slew rate on the SDA and SDA2 signals to manage directional control across the isolation barrier. Slew rates on both pins must be greater than 1V/µs for proper operation.

The logic side bidirectional serial data pin, SDA, requires a pull-up resistor or current source connected to VL. Follow the requirements in Figures 12 and 13 for the appropri-ate pull-up resistor on SDA that satisfies the desired rise time specifications and VOL maximum limits for FAST and STANDARD modes. The resistance curves represent the maximum resistance boundary; any value may be used to the left of the appropriate curve.

The isolated side clock pin, SCL2, has a weak push-pull output driver; do not connect an external pull-up device. SCL2 is compatible with I2C devices without clock stretch-ing. On lightly loaded connections, a 100pF capacitor form SCL2 to GND2 or RC lowpass filter (R = 500Ω, C = 100pF) can be used to increase the rise and fall times and minimize noise.

Some consideration must be given to signal coupling between SCL2 and SDA2. Separate these signals on a printed circuit board or route with ground between. If these signals are wired off board, twist SCL2 with VCC2 and/or GND2 and SDA2 with GND2 and/or VCC2, do not twist SCL2 and SDA2 together. If coupling between SCL2 and SDA2 is unavoidable, place the aforementioned RC filter at the SCL2 pin to reduce noise injection onto SDA2.

Figure 11. Isolated SDA2 Pin Schematic

2887 F11

SDA2

1.8mA

FROMLOGIC

SIDE

TOLOGIC

SIDE

GLITCH FILTER


LTM2887

242887fb


APPLICATIONS INFORMATIONRF, Magnetic Field Immunity

The isolator µModule technology used within the LTM2887 has been independently evaluated, and successfully passed the RF and magnetic field immunity testing requirements per European Standard EN 55024, in accordance with the following test standards:

EN 61000-4-3 Radiated, Radio-Frequency, Electromagnetic Field Immunity

EN 61000-4-8 Power Frequency Magnetic Field Immunity

EN 61000-4-9 Pulsed Magnetic Field Immunity

Tests were performed using an unshielded test card de-signed per the data sheet PCB layout recommendations. Specific limits per test are detailed in Table 4.

Table 4. EMC Immunity TestsTEST FREQUENCY FIELD STRENGTH

EN 61000-4-3 Annex D 80MHz to 1GHz 10V/m

1.4MHz to 2GHz 3V/m

2GHz to 2.7GHz 1V/m

EN 61000-4-8 Level 4 50Hz and 60Hz 30A/m

EN 61000-4-8 Level 5 60Hz 100A/m*

EN 61000-4-9 Level 5 Pulse 1000A/m

*non IEC method

PCB Layout

The high integration of the LTM2887 makes PCB layout very simple. However, to optimize its electrical isolation characteristics, EMI, and thermal performance, some layout considerations are necessary.

• Under heavily loaded conditions VCC and GND current can exceed 300mA. Sufficient copper must be used on the PCB to insure resistive losses do not cause the supply voltage to drop below the minimum allowed level. Similarly, the VCC2 and GND2 conductors must be sized to support any external load current. These heavy copper traces will also help to reduce thermal stress and improve the thermal conductivity.

• Input and output decoupling is not required, since these components are integrated within the package. An ad-ditional bulk capacitor with a value of 6.8µF to 22µF is recommended. The high ESR of this capacitor reduces board resonances and minimizes voltage spikes caused by hot plugging of the supply voltage. For EMI sensitive applications, an additional low ESL ceramic capacitor of 1µF to 4.7µF, placed as close to the power and ground terminals as possible, is recommended. Alternatively, a number of smaller value parallel capacitors may be used to reduce ESL and achieve the same net capacitance.

• Do not place copper on the PCB between the inner col-umns of pads. This area must remain open to withstand the rated isolation voltage.

• The use of solid ground planes for GND and GND2 is recommended for non-EMI critical applications to optimize signal fidelity, thermal performance, and to minimize RF emissions due to uncoupled PCB trace conduction. The drawback of using ground planes, where EMI is of concern, is the creation of a dipole antenna structure which can radiate differential voltages formed between GND and GND2. If ground planes are used it is recommended to minimize their area, and use contiguous planes as any openings or splits can exacerbate RF emissions.

• For large ground planes a small capacitance (≤330pF) from GND to GND2, either discrete or embedded within the substrate, provides a low impedance current return path for the module parasitic capacitance, minimizing any high frequency differential voltages and substantially reducing radiated emissions. Discrete capacitance will not be as effective due to parasitic ESL. In addition, volt-age rating, leakage, and clearance must be considered for component selection. Embedding the capacitance within the PCB substrate provides a near ideal capacitor and eliminates component selection issues; however, the PCB must be 4 layers. Care must be exercised in applying either technique to ensure the voltage rating of the barrier is not compromised.


LTM2887

252887fb



Figure 14. LTM2887 Low EMI Demo Board Layout

• In applications without an embedded PCB substrate capacitance a slot may be added between the logic side and isolated side device pins. The slot extends the creepage path between terminals on the PCB side, and may reduce leakage caused by PCB contamination. The slot should be placed in the middle of the device and extend beyond the package perimeter.

The PCB layout in Figures 14 and 15 shows the low EMI demo board for the LTM2887. The demo board uses a combination of EMI mitigation techniques, including both embedded PCB bridge capacitance and discrete GND to GND2 capacitors. Two safety rated type Y2 capacitors are used in series, manufactured by MuRata, part number GA342QR7GF471KW01L. The embedded capacitor ef-fectively suppresses emissions above 400MHz, whereas the discrete capacitors are more effective below 400MHz.EMI performance is shown in Figure 16, measured using a Gigahertz Transverse Electromagnetic (GTEM) cell and method detailed in IEC 61000-4-20, Testing and Measure-ment Techniques – Emission and Immunity Testing in Transverse Electromagnetic Waveguides.


LTM2887

262887fb


Top Layer Inner Layer 2

Inner Layer 1 Bottom Layer

Figure 15. LTM2887 Low EMI Demo Board Layout (DC1791A)



LTM2887

272887fb


2887 F17

LTM2887-5I

5V

A2

A5

A4

A3

A8

A6

B8

A7

A1

B1

B3

L2

L5

L4

L3

K8

L7

K7

1µF

K6

L8

L6

L1

K1

K2

SCLµCSDA

VCC

GND

VREF

LTC2301, ADC

SDA

VDD GND

AD0

AD1

REFC

GND IN–

IN+

12

10

11

1

2

7

9

8

6

5

GNDSCL3 4

REF

LTC2631A-HZ12, DAC

CA0 CA1

SCL

SDA

VOUT

GND VCC

3

1

2

4

6

8

7

5

0.1µF

1.7k

1.7k

ON

DI1

DNC

O1

VL

VCC

GND

SDA SDA2

GND

SCL

DNC

SCL2

AVCC2

IVCC2

IVL2

AVL2

VCC2

VL2

DO2 I2

DO1 I1

GND2

1µF 10µF

0.1µF 1µF

0.1µF0V TO 4.096V IN

0V TO 4.096V OUT

Figure 17. Isolated I2C 12-Bit, 0V to 4.096V Analog Input and Output

TYPICAL APPLICATIONS


Figure 16. LTM2887 Low EMI Demo Board Emissions

2887 F16

0 100 200 300 400 500 600 700 900 800 1000

Frequency (MHz)

CISPR 22 CLASS B LIMIT

DC1791A-B

DC1791A-A

DETECTOR=QUASIPEAKRBW=120kHzVBW=300kHzSWEEP TIME=17s# of POINTS=501

dBµV

/m

60

–20

10

0

–10

20

50

40

30

–30


LTM2887

282887fb



Figure 18. Isolated SPI Device Expansion

2887 F18

ON

CS

I2

CS2

LTM2887-3S

VL

VCC

GND

SDI SDI2

SDOE

SCK

DO2

SCK2

AVCC2

IVCC2

IVL2

AVL2

VCC2

VL2

SDO SDO2

CSA

MOSI

SCK

CSB

MISO

DO1 I1

GND2

A2

A5

A4

A3

A8

A6

B8

A7

A1

B1

B2

L2

L5

L4

L3

K8

L7

K7

K6

L8

L6

L1

K1

K2

74LVC1G123

Rx/Cx Cx

CLR

A

B Q

3.3V

1µF

1nF

µC

CSA

CSB

MISO

VCC

GND

MOSI

SCK

CSA

CSB

MOSI

SCK

10k

Figure 19. Isolated I2C Buffer with Dual Outputs

2887 F19

ON

DI1

DNC

O1

VL

VCC

GND

SDA SDA2

GND

SCL

ENABLE

5V

SDA

SCLIN

READY

ALERT

DNC

SCL2

AVCC2

IVCC2

IVL2

AVL2

VCC2

VL2

DO2 I2

DO1 I1

GND2

A2

A5

A4

A3

A8

A6

B8

A7

A1

B1

B3

L2

L5

L4

L3

K8

L7

K7

K6

L8

L610k

L1

K1

K2

ALERT1

LTC4305SCLIN

ALERT2 SCL2

ALERT

SDAIN

SDA2

GND

ADR0

ENABLE

VCC

SDA1

SCL1

ALERT1

ALERT2

SCL2

SDA2

SDA1

SCL1

READY

ADR2

ADR1

3

1

2

4

5

6

7

8

14

16

15

13

12

11

10

9

10k

LTM2887-5I

10k 10k 0.01µF 10k 10k 10k 10k 10k 10k


LTM2887

292887fb



Figure 20. 16-Channel Isolated Temperature to Frequency Converter

5V

1µF

OxµC

Oz

Oy

Iy

Ix

VCC

GND

2887 F20

ON

CS

I2

CS2

LTM2887-5S

VL

VCC

GND

SDI SDI2

SDOE

SCK

DO2

SCK2

AVCC2

IVCC2

IVL2

AVL2

VCC2

VL2

SDO SDO2

DO1 I1

GND2

A2

A5

A4

A3

A8

A6

B8

A7

A1

B1

B2

L2

L5

L4

L3

K8

L7

K7

K6

L8

L6

L1

K1

K2

1M

1M

X2

DG4051A

NTC THERMISTORS, MURATA NTSD1WD104, 100k

C

VCC X0

X

A

X1

B X3

X4

11

16

3

10

9

15

13

–t°

14

12

1

X5

GND

ENABLE

VEE X6

X7

6

7

8

5

2

4

SET

LTC1799

OUT V+

DIV

GND4

5

3

1

23.01k

SET

LTC1799

TEMPERATURE (°C) FREQUENCY (kHz)

–40–30–20–100102030405060708090100110120

1.231.461.872.583.775.678.6413.0919.5328.4740.6555.8774.4596.08119.83144.73169.36

OUT V+

DIV

GND4

5

3

1

23.01k

–t°

–t°

–t°

–t°

–t°

–t°

–t°

X2

DG4051A

C

VCC X0

X

A

X1

B X3

X4

11

16

3

10

9

15

13

–t°

14

12

1

X5

GND

ENABLE

VEE X6

X7

6

7

8

5

2

4

–t°

–t°

–t°

–t°

–t°

–t°

–t°


LTM2887

302887fb


2887 F21

ON

CS

I2

CS2

LTM2887-5S

VL

VCC

GND

SDI SDI2

SDOE

SCK

5V

DO2

SCK2

AVCC2

IVCC2

IVL2

AVL2

VCC2

VL2

SDO SDO2

DO1 I15V UV

5V ENABLE

3.3V UV

3.3V ENABLE

SWITCHED 3.3V

SWITCHED 5V

GND2

A2

A5

A4

A3

A8

A6

B8

A7

A1

B1

B2

L2

L5

L4

L3

K8

L7

K7

K6

L8

L6

L1

K1

K2

V2

LTC2902

CRT

COMP3 COMP2

COMP1

V3

COMP4

V1 V4

VREF

3

1

2

4

5

14

16

15

13

12

VPG

RDIS

RST

T0 GND

T1

6

7

8

11

10

9

0.1µF

51.1k

10k

9.53k

93.1k

100k

27.4k1.15k

1.15k

IRF7509

100k

IRF7509

6.04k


Figure 21. Digitally Switched Dual Power Supply with Undervoltage Monitor


LTM2887

312887fb



Figure 22. Quad 16-Bit 0 to 4.096V Output Range DAC

Figure 23. Parallel Output Supplies for Higher Current

2887 F22

LTM2887-3S

3.3V

A2

A5

A4

A3

A8

A6

B8

A7

A1

B1

B2

L2

L5

L4

L3

K8

L7

K7

1µF

K6

L8

L6

L1

K1

K2

SCKµC

MOSI

VCC

GND

VOUTC

LTC2654-H16

0V TO 4.096V OUTA

0V TO 4.096V OUTB

0V TO 4.096V OUTC

0V TO 4.096V OUTD

SDO

CS VOUTA

SDI

SCK

VOUTB

CLR VOUTD

REFLO

8

7

9

11

10

13

2

VCC REFOUT

LDAC REFC

4

14

1

15

6

5

3

GNDPORSEL12 4

ON

CS

I2

CS2

VL

VCC

GND

SDI SDI2

SDOE

SCK

DO2

SCK2

AVCC2

IVCC2

IVL2

AVL2

VCC2

VL2

SDO

CS

MISO SDO2

DO1 I1

GND2

0.1µF 0.1µF

ON

CSCS

I2

CS2

LTM2887-5S

VL

VCC

GND

SDISDI SDI2

SCKSCK

DO2

SCK2

AVCC2

IVCC2

IVL2

AVL2

VCC2

VL2

SDOSDO

CS

SDI

5V@200mA5V

SCK

SDOSDO2

DO1 I1

GND2

A2

A5

A4

A3

A8

A6

B8

A7

A1

B1

B2

L2

L5

L4

L3

K8

L7

K7

K6

L8

L6

L1

K1

K2

SDOE

2887 F23


LTM2887

322887fb



Figure 24. –48V, 200W Hot Swap Controller with Isolated I2C Interface

2887 F24

LTM2887-5I

5V

A2

A5

A4

A3

A8

A6

B8

A7

A1

B1

B2

L2

L5

L4

L3

L7

K81µF

K6

L8

L6

K7

L1

K1

K2

SCL

1x

Ox

µCSDA

VCC

GND

10k

10k

ON

DI1

DNC

O1

IVL2

AVCC2VL

VCC

GND

SDA SDA2

GND

SCL

DNC

SCL2

IVCC2

AVL2

VCC2

VL2

DO2 I2

DO1 I1

GND2 VEE

VEE

VOUT

SDAI

LTC4261CGNSS

UVL FLTIN

UVH

ADIN2

SCL

OV SDAO

ALERT

10

8

9

11

19

5

22

6

4

3

ONTMR20

ADR0

EN

PGI

ADR1

1

26

25

24ADIN

PGI0

PG

PWRGD2

–48V RTN

–48V INPUTIRF1310NS

PWRGD1

28

27

23

VEE

13

SENSE

14

GATE

15

INTVCC

7

VIN

21

DRAIN

16

RAMP

18

2

10nF100V0.1µF47nF

100nF 220nF1µF

0.1µF

330µF100V

1k

16.9k

11.8k

453k 1k, ×4 IN SERIES1/4W EACH

47nF10Ω

10k 402k0.008Ω

1%

1M

+

10k


LTM2887

332887fb


Figure 25. 12-Cell Battery Stack Monitor with Isolated SPI Interface and Low Power Shutdown


ON

CS

I2

CS2

LTM2887-3S

VL

VCC

GND

SDI SDI2

SCK

DO2

SCK2

AVCC2

IVCC2

IVL2

AVL2

VCC2

VL2

SDO SDO2

DO1 I1

GND2

A2

A5

A4

A3

A8

A6

B8

A7

A1

B1

B2

L2

L5

L4

L3

K8

L7

K7

K6

L8

L6

L1

K1

K2

SCKO

LTC6803-1

VMODE

CSI CSO

SDO

SDI

SDOI

SCKI V+

C12

42

44

43

41

40

S12

WDT

GPIO2

GPIO1 C11

S11

39

38

37

3

1

2

4

5

6

7

8

1µF

µC

CS

MISO

VCC

GND

3.3V

MOSI

SCK

S10

VREF

NC

TOS

C10

VREG C9

S9

35

36

34

33

10

9

11

12

C8

NC

VTEMP2

VTEMP1 S8

C7

32

31

30

13

14

15

C6

S2

V–

S1

S7

C1 S6

C5

28

29

27

26

17

16

18

19

S5

C3

C2

S3 C4

S4

25

24

23

20

21

22

1µF1µF

100k

100k

100k

100k

3.3k3.3k 3.3k 3.3k

SDOE

2887 F25

74LVC3G07


LTM2887

342887fb


TYPICAL APPLICATIONSLTM2887-3I

3.3V

A2

A5

A4

A3

A8

A6

B8

A7

A1

B1

B2

L2

L5

L4

L3

K8

L7

K7

1µF

K6

L8

L6

L1

K1

K2

SCLµC

SDA

VCC

GND

10k

10k

ON

DI1

DNC

O1

VL

VCC

GND

SDA SDA2

GND

SCL

DNC

SCL2

AVCC2

IVCC2

IVL2

AVL2

VCC2

VL2

DO2 I2

DO1 I1

GND2

LTC4151

SHDN

ADINSDA

SCL

GND

ADR0

ADR1

48V

SENSE–SENSE+ VIN

VOUT

1.37k1%

0.02Ω

100k AT 25°C, 1%VISHAY 2381 6154.104

NADIN IS THE DIGITAL CODE MEASUREDBY THE ADC AT THE ADIN PIN

T(°C) = 3950

8.965+LN 1000NADIN

−1

− 273,−40°C < T < 150°C

2887 F26

Figure 26. Isolated I2C Voltage, Current and Temperature Power Supply Monitor


LTM2887

352887fb


LTM2887-5I

5V

SHUTDOWN

ENABLE

SDA

SCLIN

INTERRUPT

A2

A5

A4

A3

A8

A6

B8

A7

A1

B1

B2

L2

L5

L4

L3

K8

L7

K7

K6

L8

L6

L1

K1

K2

10k

10k

100k

27.4k

6.04k

ON

DI1

DNC

O1

VL

VCC

GND

SDA SDA2

GND

SCL

DNC

SCL2

AVCC2

IVCC2

IVL2

AVL2

VCC2

VL2

DO2 I2

DO1 I1

GND2

1/4 LTC4266

PHY

(NETWORKPHYSICAL

LAYERCHIP)

RESET

INT

DETECT

BYP

SDAIN

SCL

AD0

AD1

AD2

AD3

SDAOUT

AUTO

SHDN1 VDD

DGND AGND VEE SENSE GATE OUTQ1: FAIRCHILD IRFM120A OR PHILIPS PHT6NQ10TFB1, FB2: TDK MPZ2012S601AT1: PULSE H609NL OR COILCRAFT ETH1-230LD

2887 F27

1µFSMAJ58A

–48V

0.1µF

0.1µF

0.22µF

0.25Ω

S1B

Q1

S1B

CMPD3003

FB2

RJ45CONNECTOR

FB1

T1•

•

•

•

••

75Ω 75Ω10nF 10nF

1

2

3

•

•

•

•

••

75Ω 75Ω10nF 10nF

4

6

7

8

5

1nF


Figure 27. One Complete Isolated Powered Ethernet Port


LTM2887

362887fb


PACKAGE DESCRIPTION

BGA

Pack

age

32-L

ead

(15m

m ×

11.

25m

m ×

3.4

2mm

)(R

efer

ence

LTC

DWG

# 05

-08-

1851

Rev

D)

5. P

RIM

ARY

DAT

UM

-Z-

IS S

EATI

NG

PLA

NE

6. S

OLD

ER B

ALL

COM

POSI

TIO

N IS

96.

5% S

n/3.

0% A

g/0.

5% C

u

7PA

CKAG

E R

OW

AN

D C

OLU

MN

LAB

ELIN

G M

AY V

ARY

AMO

NG

µM

odul

e PR

OD

UCT

S. R

EVIE

W E

ACH

PAC

KAG

E LA

YOU

T CA

REF

ULL

Y!

NO

TES:

1. D

IMEN

SIO

NIN

G A

ND

TO

LER

ANCI

NG

PER

ASM

E Y1

4.5M

-199

4

2. A

LL D

IMEN

SIO

NS

ARE

IN M

ILLI

MET

ERS

BAL

L D

ESIG

NAT

ION

PER

JES

D M

S-02

8 AN

D J

EP95

43

DET

AILS

OF

PIN

#1

IDEN

TIFI

ER A

RE

OPT

ION

AL,

BUT

MU

ST B

E LO

CATE

D W

ITH

IN T

HE

ZON

E IN

DIC

ATED

.TH

E PI

N #

1 ID

ENTI

FIER

MAY

BE

EITH

ER A

MO

LD O

R

MAR

KED

FEA

TUR

E

PACK

AGE

TOP

VIEW

4

PIN

“A1

”CO

RN

ER

X

Y

aaa

Z

aaa Z

PACK

AGE

BOTT

OM

VIE

W

3

SEE

NO

TES

SUG

GES

TED

PCB

LAY

OU

TTO

P VI

EWBG

A 32

111

2 R

EV D

LTM

XXXX

XXµM

odul

e

TRAY

PIN

1BE

VEL

PACK

AGE

IN T

RAY

LO

ADIN

G O

RIE

NTA

TIO

N

COM

PON

ENT

PIN

“A1

”

DET

AIL

A

PIN

1

0.0000.635

0.635

1.905

1.905

3.175

3.175

4.445

4.445

6.35

0

6.35

0

5.08

0

5.08

0

0.00

0

DET

AIL

A

Øb

(32

PLAC

ES)

F G H LJ KEA B C D

21

43

56

78

DET

AIL

B

SUBS

TRAT

E

0.27

– 0

.37

2.45

– 2

.55

// bbb Z

D

A

A1

b1

ccc

Z

DET

AIL

BPA

CKAG

E SI

DE

VIEW

MO

LDCA

P

Z

MX

YZ

ddd

MZ

eee

0.63

0 ±0

.025

Ø 3

2x

SYM

BOL

A A1 A2 b b1 D E e F G aaa

bbb

ccc

ddd

eee

MIN

3.22

0.50

2.72

0.60

0.60

NO

M3.

420.

602.

820.

750.

6315

.011

.25

1.27

12.7

08.

89

MAX

3.62

0.70

2.92

0.90

0.66

0.15

0.10

0.20

0.30

0.15

NO

TES

DIM

ENSI

ON

S

TOTA

L N

UM

BER

OF

BALL

S: 3

2

E

b

e

e

b

A2

F

G

BGA

Pack

age

32-L

ead

(15m

m ×

11.

25m

m ×

3.4

2mm

)(R

efer

ence

LTC

DW

G #

05-

08-1

851

Rev

D)

7

SEE

NO

TES

Please refer to http://www.linear.com/product/LTM2887#packaging for the most recent package drawings.


http://www.linear.com/product/LTM2887#packaging

LTM2887

372887fb


Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORYREV DATE DESCRIPTION PAGE NUMBER

A 03/17 Added UL-CSA File Number 1

B 07/17 Changed MIN limit for tPWU (SPI and I2C) 6


LTM2887

382887fb

For more information www.linear.com/LTM2887 LINEAR TECHNOLOGY CORPORATION 2016

LT 0717 REV B • PRINTED IN USAwww.linear.com/LTM2887

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TYPICAL APPLICATION

PART NUMBER DESCRIPTION COMMENTS

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LTM2887-3S

1.15k

3.3V

A2

A5

A4

A3

A8

A6

B8

A7

A1

B1

B2

L2

L5

L4

L3

K8

L7

K7

1µF

10µF

19.1kK6

L8

L6

L1

K1

K2

SCK

MISO

µC

Ox

VCC

GND

ON

CS

I2

CS2

VL

VCC

GND

SDI SDI2

SDOE

SCK

DO2

SCK2

AVCC2

IVCC2

IVL2

AVL2

VCC2

VL2

SDO SDO2

DO1 I1

GND22887 TA02

VREF

LTC1407A

GND

CONV CH0+

SCK

SDO

CH0–

VDD CH1+

CH1–

CH0+

CH0–

CH1+

CH1–

8

10

9

7

6

3

1

2

4

5

10µF

6.04k










http://www.linear.com/LTC1535

http://www.linear.com/LTC4310

http://www.linear.com/LTC6803-1

http://www.linear.com/LTC6803-2

Documents

LTM2887 - SPI/Digital or I2C µModule Isolator with …...LTM2887CY-5I#PBF LTM2887Y-5I 4.5V to 5.5V I2C 0 C to 70 C LTM2887IY-5I#PBF –40 C to 85 C LTM2887HY-5I#PBF –40 C to 125